1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * cs35l32.h -- CS35L32 ALSA SoC audio driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2014 CirrusLogic, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Brian Austin <brian.austin@cirrus.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CS35L32_H__ 11*4882a593Smuzhiyun #define __CS35L32_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct cs35l32_platform_data { 14*4882a593Smuzhiyun /* Low Battery Threshold */ 15*4882a593Smuzhiyun unsigned int batt_thresh; 16*4882a593Smuzhiyun /* Low Battery Recovery */ 17*4882a593Smuzhiyun unsigned int batt_recov; 18*4882a593Smuzhiyun /* LED Current Management*/ 19*4882a593Smuzhiyun unsigned int led_mng; 20*4882a593Smuzhiyun /* Audio Gain w/ LED */ 21*4882a593Smuzhiyun unsigned int audiogain_mng; 22*4882a593Smuzhiyun /* Boost Management */ 23*4882a593Smuzhiyun unsigned int boost_mng; 24*4882a593Smuzhiyun /* Data CFG for DUAL device */ 25*4882a593Smuzhiyun unsigned int sdout_datacfg; 26*4882a593Smuzhiyun /* SDOUT Sharing */ 27*4882a593Smuzhiyun unsigned int sdout_share; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CS35L32_CHIP_ID 0x00035A32 31*4882a593Smuzhiyun #define CS35L32_DEVID_AB 0x01 /* Device ID A & B [RO] */ 32*4882a593Smuzhiyun #define CS35L32_DEVID_CD 0x02 /* Device ID C & D [RO] */ 33*4882a593Smuzhiyun #define CS35L32_DEVID_E 0x03 /* Device ID E [RO] */ 34*4882a593Smuzhiyun #define CS35L32_FAB_ID 0x04 /* Fab ID [RO] */ 35*4882a593Smuzhiyun #define CS35L32_REV_ID 0x05 /* Revision ID [RO] */ 36*4882a593Smuzhiyun #define CS35L32_PWRCTL1 0x06 /* Power Ctl 1 */ 37*4882a593Smuzhiyun #define CS35L32_PWRCTL2 0x07 /* Power Ctl 2 */ 38*4882a593Smuzhiyun #define CS35L32_CLK_CTL 0x08 /* Clock Ctl */ 39*4882a593Smuzhiyun #define CS35L32_BATT_THRESHOLD 0x09 /* Low Battery Threshold */ 40*4882a593Smuzhiyun #define CS35L32_VMON 0x0A /* Voltage Monitor [RO] */ 41*4882a593Smuzhiyun #define CS35L32_BST_CPCP_CTL 0x0B /* Conv Peak Curr Protection CTL */ 42*4882a593Smuzhiyun #define CS35L32_IMON_SCALING 0x0C /* IMON Scaling */ 43*4882a593Smuzhiyun #define CS35L32_AUDIO_LED_MNGR 0x0D /* Audio/LED Pwr Manager */ 44*4882a593Smuzhiyun #define CS35L32_ADSP_CTL 0x0F /* Serial Port Control */ 45*4882a593Smuzhiyun #define CS35L32_CLASSD_CTL 0x10 /* Class D Amp CTL */ 46*4882a593Smuzhiyun #define CS35L32_PROTECT_CTL 0x11 /* Protection Release CTL */ 47*4882a593Smuzhiyun #define CS35L32_INT_MASK_1 0x12 /* Interrupt Mask 1 */ 48*4882a593Smuzhiyun #define CS35L32_INT_MASK_2 0x13 /* Interrupt Mask 2 */ 49*4882a593Smuzhiyun #define CS35L32_INT_MASK_3 0x14 /* Interrupt Mask 3 */ 50*4882a593Smuzhiyun #define CS35L32_INT_STATUS_1 0x15 /* Interrupt Status 1 [RO] */ 51*4882a593Smuzhiyun #define CS35L32_INT_STATUS_2 0x16 /* Interrupt Status 2 [RO] */ 52*4882a593Smuzhiyun #define CS35L32_INT_STATUS_3 0x17 /* Interrupt Status 3 [RO] */ 53*4882a593Smuzhiyun #define CS35L32_LED_STATUS 0x18 /* LED Lighting Status [RO] */ 54*4882a593Smuzhiyun #define CS35L32_FLASH_MODE 0x19 /* LED Flash Mode Current */ 55*4882a593Smuzhiyun #define CS35L32_MOVIE_MODE 0x1A /* LED Movie Mode Current */ 56*4882a593Smuzhiyun #define CS35L32_FLASH_TIMER 0x1B /* LED Flash Timer */ 57*4882a593Smuzhiyun #define CS35L32_FLASH_INHIBIT 0x1C /* LED Flash Inhibit Current */ 58*4882a593Smuzhiyun #define CS35L32_MAX_REGISTER 0x1C 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CS35L32_MCLK_DIV2 0x01 61*4882a593Smuzhiyun #define CS35L32_MCLK_RATIO 0x01 62*4882a593Smuzhiyun #define CS35L32_MCLKDIS 0x80 63*4882a593Smuzhiyun #define CS35L32_PDN_ALL 0x01 64*4882a593Smuzhiyun #define CS35L32_PDN_AMP 0x80 65*4882a593Smuzhiyun #define CS35L32_PDN_BOOST 0x04 66*4882a593Smuzhiyun #define CS35L32_PDN_IMON 0x40 67*4882a593Smuzhiyun #define CS35L32_PDN_VMON 0x80 68*4882a593Smuzhiyun #define CS35L32_PDN_VPMON 0x20 69*4882a593Smuzhiyun #define CS35L32_PDN_ADSP 0x08 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CS35L32_MCLK_DIV2_MASK 0x40 72*4882a593Smuzhiyun #define CS35L32_MCLK_RATIO_MASK 0x01 73*4882a593Smuzhiyun #define CS35L32_MCLK_MASK 0x41 74*4882a593Smuzhiyun #define CS35L32_ADSP_MASTER_MASK 0x40 75*4882a593Smuzhiyun #define CS35L32_BOOST_MASK 0x03 76*4882a593Smuzhiyun #define CS35L32_GAIN_MGR_MASK 0x08 77*4882a593Smuzhiyun #define CS35L32_ADSP_SHARE_MASK 0x08 78*4882a593Smuzhiyun #define CS35L32_ADSP_DATACFG_MASK 0x30 79*4882a593Smuzhiyun #define CS35L32_SDOUT_3ST 0x08 80*4882a593Smuzhiyun #define CS35L32_BATT_REC_MASK 0x0E 81*4882a593Smuzhiyun #define CS35L32_BATT_THRESH_MASK 0x30 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define CS35L32_RATES (SNDRV_PCM_RATE_48000) 84*4882a593Smuzhiyun #define CS35L32_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 85*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | \ 86*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif 90