xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/cs35l32.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * cs35l32.c -- CS35L32 ALSA SoC audio driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2014 CirrusLogic, Inc.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Brian Austin <brian.austin@cirrus.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/moduleparam.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/gpio.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
21*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
22*4882a593Smuzhiyun #include <linux/of_device.h>
23*4882a593Smuzhiyun #include <sound/core.h>
24*4882a593Smuzhiyun #include <sound/pcm.h>
25*4882a593Smuzhiyun #include <sound/pcm_params.h>
26*4882a593Smuzhiyun #include <sound/soc.h>
27*4882a593Smuzhiyun #include <sound/soc-dapm.h>
28*4882a593Smuzhiyun #include <sound/initval.h>
29*4882a593Smuzhiyun #include <sound/tlv.h>
30*4882a593Smuzhiyun #include <dt-bindings/sound/cs35l32.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #include "cs35l32.h"
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define CS35L32_NUM_SUPPLIES 2
35*4882a593Smuzhiyun static const char *const cs35l32_supply_names[CS35L32_NUM_SUPPLIES] = {
36*4882a593Smuzhiyun 	"VA",
37*4882a593Smuzhiyun 	"VP",
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun struct  cs35l32_private {
41*4882a593Smuzhiyun 	struct regmap *regmap;
42*4882a593Smuzhiyun 	struct snd_soc_component *component;
43*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[CS35L32_NUM_SUPPLIES];
44*4882a593Smuzhiyun 	struct cs35l32_platform_data pdata;
45*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun static const struct reg_default cs35l32_reg_defaults[] = {
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	{ 0x06, 0x04 }, /* Power Ctl 1 */
51*4882a593Smuzhiyun 	{ 0x07, 0xE8 }, /* Power Ctl 2 */
52*4882a593Smuzhiyun 	{ 0x08, 0x40 }, /* Clock Ctl */
53*4882a593Smuzhiyun 	{ 0x09, 0x20 }, /* Low Battery Threshold */
54*4882a593Smuzhiyun 	{ 0x0A, 0x00 }, /* Voltage Monitor [RO] */
55*4882a593Smuzhiyun 	{ 0x0B, 0x40 }, /* Conv Peak Curr Protection CTL */
56*4882a593Smuzhiyun 	{ 0x0C, 0x07 }, /* IMON Scaling */
57*4882a593Smuzhiyun 	{ 0x0D, 0x03 }, /* Audio/LED Pwr Manager */
58*4882a593Smuzhiyun 	{ 0x0F, 0x20 }, /* Serial Port Control */
59*4882a593Smuzhiyun 	{ 0x10, 0x14 }, /* Class D Amp CTL */
60*4882a593Smuzhiyun 	{ 0x11, 0x00 }, /* Protection Release CTL */
61*4882a593Smuzhiyun 	{ 0x12, 0xFF }, /* Interrupt Mask 1 */
62*4882a593Smuzhiyun 	{ 0x13, 0xFF }, /* Interrupt Mask 2 */
63*4882a593Smuzhiyun 	{ 0x14, 0xFF }, /* Interrupt Mask 3 */
64*4882a593Smuzhiyun 	{ 0x19, 0x00 }, /* LED Flash Mode Current */
65*4882a593Smuzhiyun 	{ 0x1A, 0x00 }, /* LED Movie Mode Current */
66*4882a593Smuzhiyun 	{ 0x1B, 0x20 }, /* LED Flash Timer */
67*4882a593Smuzhiyun 	{ 0x1C, 0x00 }, /* LED Flash Inhibit Current */
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
cs35l32_readable_register(struct device * dev,unsigned int reg)70*4882a593Smuzhiyun static bool cs35l32_readable_register(struct device *dev, unsigned int reg)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	switch (reg) {
73*4882a593Smuzhiyun 	case CS35L32_DEVID_AB ... CS35L32_AUDIO_LED_MNGR:
74*4882a593Smuzhiyun 	case CS35L32_ADSP_CTL ... CS35L32_FLASH_INHIBIT:
75*4882a593Smuzhiyun 		return true;
76*4882a593Smuzhiyun 	default:
77*4882a593Smuzhiyun 		return false;
78*4882a593Smuzhiyun 	}
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
cs35l32_volatile_register(struct device * dev,unsigned int reg)81*4882a593Smuzhiyun static bool cs35l32_volatile_register(struct device *dev, unsigned int reg)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun 	switch (reg) {
84*4882a593Smuzhiyun 	case CS35L32_DEVID_AB ... CS35L32_REV_ID:
85*4882a593Smuzhiyun 	case CS35L32_INT_STATUS_1 ... CS35L32_LED_STATUS:
86*4882a593Smuzhiyun 		return true;
87*4882a593Smuzhiyun 	default:
88*4882a593Smuzhiyun 		return false;
89*4882a593Smuzhiyun 	}
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun 
cs35l32_precious_register(struct device * dev,unsigned int reg)92*4882a593Smuzhiyun static bool cs35l32_precious_register(struct device *dev, unsigned int reg)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	switch (reg) {
95*4882a593Smuzhiyun 	case CS35L32_INT_STATUS_1 ... CS35L32_LED_STATUS:
96*4882a593Smuzhiyun 		return true;
97*4882a593Smuzhiyun 	default:
98*4882a593Smuzhiyun 		return false;
99*4882a593Smuzhiyun 	}
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 300, 0);
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun static const struct snd_kcontrol_new imon_ctl =
105*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 6, 1, 1);
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun static const struct snd_kcontrol_new vmon_ctl =
108*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 7, 1, 1);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun static const struct snd_kcontrol_new vpmon_ctl =
111*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 5, 1, 1);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun static const struct snd_kcontrol_new cs35l32_snd_controls[] = {
114*4882a593Smuzhiyun 	SOC_SINGLE_TLV("Speaker Volume", CS35L32_CLASSD_CTL,
115*4882a593Smuzhiyun 		       3, 0x04, 1, classd_ctl_tlv),
116*4882a593Smuzhiyun 	SOC_SINGLE("Zero Cross Switch", CS35L32_CLASSD_CTL, 2, 1, 0),
117*4882a593Smuzhiyun 	SOC_SINGLE("Gain Manager Switch", CS35L32_AUDIO_LED_MNGR, 3, 1, 0),
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun static const struct snd_soc_dapm_widget cs35l32_dapm_widgets[] = {
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("BOOST", CS35L32_PWRCTL1, 2, 1, NULL, 0),
123*4882a593Smuzhiyun 	SND_SOC_DAPM_OUT_DRV("Speaker", CS35L32_PWRCTL1, 7, 1, NULL, 0),
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L32_PWRCTL2, 3, 1),
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("VP"),
128*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("ISENSE"),
129*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("VSENSE"),
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("VMON ADC", CS35L32_PWRCTL2, 7, 1, &vmon_ctl),
132*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("IMON ADC", CS35L32_PWRCTL2, 6, 1, &imon_ctl),
133*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("VPMON ADC", CS35L32_PWRCTL2, 5, 1, &vpmon_ctl),
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun static const struct snd_soc_dapm_route cs35l32_audio_map[] = {
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	{"Speaker", NULL, "BOOST"},
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	{"VMON ADC", NULL, "VSENSE"},
141*4882a593Smuzhiyun 	{"IMON ADC", NULL, "ISENSE"},
142*4882a593Smuzhiyun 	{"VPMON ADC", NULL, "VP"},
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	{"SDOUT", "Switch", "VMON ADC"},
145*4882a593Smuzhiyun 	{"SDOUT",  "Switch", "IMON ADC"},
146*4882a593Smuzhiyun 	{"SDOUT", "Switch", "VPMON ADC"},
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	{"Capture", NULL, "SDOUT"},
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
cs35l32_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)151*4882a593Smuzhiyun static int cs35l32_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
156*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
157*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS35L32_ADSP_CTL,
158*4882a593Smuzhiyun 				    CS35L32_ADSP_MASTER_MASK,
159*4882a593Smuzhiyun 				CS35L32_ADSP_MASTER_MASK);
160*4882a593Smuzhiyun 		break;
161*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
162*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, CS35L32_ADSP_CTL,
163*4882a593Smuzhiyun 				    CS35L32_ADSP_MASTER_MASK, 0);
164*4882a593Smuzhiyun 		break;
165*4882a593Smuzhiyun 	default:
166*4882a593Smuzhiyun 		return -EINVAL;
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	return 0;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun 
cs35l32_set_tristate(struct snd_soc_dai * dai,int tristate)172*4882a593Smuzhiyun static int cs35l32_set_tristate(struct snd_soc_dai *dai, int tristate)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	return snd_soc_component_update_bits(component, CS35L32_PWRCTL2,
177*4882a593Smuzhiyun 					CS35L32_SDOUT_3ST, tristate << 3);
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun static const struct snd_soc_dai_ops cs35l32_ops = {
181*4882a593Smuzhiyun 	.set_fmt = cs35l32_set_dai_fmt,
182*4882a593Smuzhiyun 	.set_tristate = cs35l32_set_tristate,
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun static struct snd_soc_dai_driver cs35l32_dai[] = {
186*4882a593Smuzhiyun 	{
187*4882a593Smuzhiyun 		.name = "cs35l32-monitor",
188*4882a593Smuzhiyun 		.id = 0,
189*4882a593Smuzhiyun 		.capture = {
190*4882a593Smuzhiyun 			.stream_name = "Capture",
191*4882a593Smuzhiyun 			.channels_min = 2,
192*4882a593Smuzhiyun 			.channels_max = 2,
193*4882a593Smuzhiyun 			.rates = CS35L32_RATES,
194*4882a593Smuzhiyun 			.formats = CS35L32_FORMATS,
195*4882a593Smuzhiyun 		},
196*4882a593Smuzhiyun 		.ops = &cs35l32_ops,
197*4882a593Smuzhiyun 		.symmetric_rates = 1,
198*4882a593Smuzhiyun 	}
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun 
cs35l32_component_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)201*4882a593Smuzhiyun static int cs35l32_component_set_sysclk(struct snd_soc_component *component,
202*4882a593Smuzhiyun 			      int clk_id, int source, unsigned int freq, int dir)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	unsigned int val;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	switch (freq) {
207*4882a593Smuzhiyun 	case 6000000:
208*4882a593Smuzhiyun 		val = CS35L32_MCLK_RATIO;
209*4882a593Smuzhiyun 		break;
210*4882a593Smuzhiyun 	case 12000000:
211*4882a593Smuzhiyun 		val = CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO;
212*4882a593Smuzhiyun 		break;
213*4882a593Smuzhiyun 	case 6144000:
214*4882a593Smuzhiyun 		val = 0;
215*4882a593Smuzhiyun 		break;
216*4882a593Smuzhiyun 	case 12288000:
217*4882a593Smuzhiyun 		val = CS35L32_MCLK_DIV2_MASK;
218*4882a593Smuzhiyun 		break;
219*4882a593Smuzhiyun 	default:
220*4882a593Smuzhiyun 		return -EINVAL;
221*4882a593Smuzhiyun 	}
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	return snd_soc_component_update_bits(component, CS35L32_CLK_CTL,
224*4882a593Smuzhiyun 			CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO_MASK, val);
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_cs35l32 = {
228*4882a593Smuzhiyun 	.set_sysclk		= cs35l32_component_set_sysclk,
229*4882a593Smuzhiyun 	.controls		= cs35l32_snd_controls,
230*4882a593Smuzhiyun 	.num_controls		= ARRAY_SIZE(cs35l32_snd_controls),
231*4882a593Smuzhiyun 	.dapm_widgets		= cs35l32_dapm_widgets,
232*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(cs35l32_dapm_widgets),
233*4882a593Smuzhiyun 	.dapm_routes		= cs35l32_audio_map,
234*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(cs35l32_audio_map),
235*4882a593Smuzhiyun 	.idle_bias_on		= 1,
236*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
237*4882a593Smuzhiyun 	.endianness		= 1,
238*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun /* Current and threshold powerup sequence Pg37 in datasheet */
242*4882a593Smuzhiyun static const struct reg_sequence cs35l32_monitor_patch[] = {
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	{ 0x00, 0x99 },
245*4882a593Smuzhiyun 	{ 0x48, 0x17 },
246*4882a593Smuzhiyun 	{ 0x49, 0x56 },
247*4882a593Smuzhiyun 	{ 0x43, 0x01 },
248*4882a593Smuzhiyun 	{ 0x3B, 0x62 },
249*4882a593Smuzhiyun 	{ 0x3C, 0x80 },
250*4882a593Smuzhiyun 	{ 0x00, 0x00 },
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun static const struct regmap_config cs35l32_regmap = {
254*4882a593Smuzhiyun 	.reg_bits = 8,
255*4882a593Smuzhiyun 	.val_bits = 8,
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	.max_register = CS35L32_MAX_REGISTER,
258*4882a593Smuzhiyun 	.reg_defaults = cs35l32_reg_defaults,
259*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(cs35l32_reg_defaults),
260*4882a593Smuzhiyun 	.volatile_reg = cs35l32_volatile_register,
261*4882a593Smuzhiyun 	.readable_reg = cs35l32_readable_register,
262*4882a593Smuzhiyun 	.precious_reg = cs35l32_precious_register,
263*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun 
cs35l32_handle_of_data(struct i2c_client * i2c_client,struct cs35l32_platform_data * pdata)266*4882a593Smuzhiyun static int cs35l32_handle_of_data(struct i2c_client *i2c_client,
267*4882a593Smuzhiyun 				    struct cs35l32_platform_data *pdata)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun 	struct device_node *np = i2c_client->dev.of_node;
270*4882a593Smuzhiyun 	unsigned int val;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	if (of_property_read_u32(np, "cirrus,sdout-share", &val) >= 0)
273*4882a593Smuzhiyun 		pdata->sdout_share = val;
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	if (of_property_read_u32(np, "cirrus,boost-manager", &val))
276*4882a593Smuzhiyun 		val = -1u;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	switch (val) {
279*4882a593Smuzhiyun 	case CS35L32_BOOST_MGR_AUTO:
280*4882a593Smuzhiyun 	case CS35L32_BOOST_MGR_AUTO_AUDIO:
281*4882a593Smuzhiyun 	case CS35L32_BOOST_MGR_BYPASS:
282*4882a593Smuzhiyun 	case CS35L32_BOOST_MGR_FIXED:
283*4882a593Smuzhiyun 		pdata->boost_mng = val;
284*4882a593Smuzhiyun 		break;
285*4882a593Smuzhiyun 	case -1u:
286*4882a593Smuzhiyun 	default:
287*4882a593Smuzhiyun 		dev_err(&i2c_client->dev,
288*4882a593Smuzhiyun 			"Wrong cirrus,boost-manager DT value %d\n", val);
289*4882a593Smuzhiyun 		pdata->boost_mng = CS35L32_BOOST_MGR_BYPASS;
290*4882a593Smuzhiyun 	}
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	if (of_property_read_u32(np, "cirrus,sdout-datacfg", &val))
293*4882a593Smuzhiyun 		val = -1u;
294*4882a593Smuzhiyun 	switch (val) {
295*4882a593Smuzhiyun 	case CS35L32_DATA_CFG_LR_VP:
296*4882a593Smuzhiyun 	case CS35L32_DATA_CFG_LR_STAT:
297*4882a593Smuzhiyun 	case CS35L32_DATA_CFG_LR:
298*4882a593Smuzhiyun 	case CS35L32_DATA_CFG_LR_VPSTAT:
299*4882a593Smuzhiyun 		pdata->sdout_datacfg = val;
300*4882a593Smuzhiyun 		break;
301*4882a593Smuzhiyun 	case -1u:
302*4882a593Smuzhiyun 	default:
303*4882a593Smuzhiyun 		dev_err(&i2c_client->dev,
304*4882a593Smuzhiyun 			"Wrong cirrus,sdout-datacfg DT value %d\n", val);
305*4882a593Smuzhiyun 		pdata->sdout_datacfg = CS35L32_DATA_CFG_LR;
306*4882a593Smuzhiyun 	}
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	if (of_property_read_u32(np, "cirrus,battery-threshold", &val))
309*4882a593Smuzhiyun 		val = -1u;
310*4882a593Smuzhiyun 	switch (val) {
311*4882a593Smuzhiyun 	case CS35L32_BATT_THRESH_3_1V:
312*4882a593Smuzhiyun 	case CS35L32_BATT_THRESH_3_2V:
313*4882a593Smuzhiyun 	case CS35L32_BATT_THRESH_3_3V:
314*4882a593Smuzhiyun 	case CS35L32_BATT_THRESH_3_4V:
315*4882a593Smuzhiyun 		pdata->batt_thresh = val;
316*4882a593Smuzhiyun 		break;
317*4882a593Smuzhiyun 	case -1u:
318*4882a593Smuzhiyun 	default:
319*4882a593Smuzhiyun 		dev_err(&i2c_client->dev,
320*4882a593Smuzhiyun 			"Wrong cirrus,battery-threshold DT value %d\n", val);
321*4882a593Smuzhiyun 		pdata->batt_thresh = CS35L32_BATT_THRESH_3_3V;
322*4882a593Smuzhiyun 	}
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	if (of_property_read_u32(np, "cirrus,battery-recovery", &val))
325*4882a593Smuzhiyun 		val = -1u;
326*4882a593Smuzhiyun 	switch (val) {
327*4882a593Smuzhiyun 	case CS35L32_BATT_RECOV_3_1V:
328*4882a593Smuzhiyun 	case CS35L32_BATT_RECOV_3_2V:
329*4882a593Smuzhiyun 	case CS35L32_BATT_RECOV_3_3V:
330*4882a593Smuzhiyun 	case CS35L32_BATT_RECOV_3_4V:
331*4882a593Smuzhiyun 	case CS35L32_BATT_RECOV_3_5V:
332*4882a593Smuzhiyun 	case CS35L32_BATT_RECOV_3_6V:
333*4882a593Smuzhiyun 		pdata->batt_recov = val;
334*4882a593Smuzhiyun 		break;
335*4882a593Smuzhiyun 	case -1u:
336*4882a593Smuzhiyun 	default:
337*4882a593Smuzhiyun 		dev_err(&i2c_client->dev,
338*4882a593Smuzhiyun 			"Wrong cirrus,battery-recovery DT value %d\n", val);
339*4882a593Smuzhiyun 		pdata->batt_recov = CS35L32_BATT_RECOV_3_4V;
340*4882a593Smuzhiyun 	}
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	return 0;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun 
cs35l32_i2c_probe(struct i2c_client * i2c_client,const struct i2c_device_id * id)345*4882a593Smuzhiyun static int cs35l32_i2c_probe(struct i2c_client *i2c_client,
346*4882a593Smuzhiyun 				       const struct i2c_device_id *id)
347*4882a593Smuzhiyun {
348*4882a593Smuzhiyun 	struct cs35l32_private *cs35l32;
349*4882a593Smuzhiyun 	struct cs35l32_platform_data *pdata =
350*4882a593Smuzhiyun 		dev_get_platdata(&i2c_client->dev);
351*4882a593Smuzhiyun 	int ret, i;
352*4882a593Smuzhiyun 	unsigned int devid = 0;
353*4882a593Smuzhiyun 	unsigned int reg;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	cs35l32 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l32), GFP_KERNEL);
356*4882a593Smuzhiyun 	if (!cs35l32)
357*4882a593Smuzhiyun 		return -ENOMEM;
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	i2c_set_clientdata(i2c_client, cs35l32);
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	cs35l32->regmap = devm_regmap_init_i2c(i2c_client, &cs35l32_regmap);
362*4882a593Smuzhiyun 	if (IS_ERR(cs35l32->regmap)) {
363*4882a593Smuzhiyun 		ret = PTR_ERR(cs35l32->regmap);
364*4882a593Smuzhiyun 		dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
365*4882a593Smuzhiyun 		return ret;
366*4882a593Smuzhiyun 	}
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	if (pdata) {
369*4882a593Smuzhiyun 		cs35l32->pdata = *pdata;
370*4882a593Smuzhiyun 	} else {
371*4882a593Smuzhiyun 		pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
372*4882a593Smuzhiyun 				     GFP_KERNEL);
373*4882a593Smuzhiyun 		if (!pdata)
374*4882a593Smuzhiyun 			return -ENOMEM;
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 		if (i2c_client->dev.of_node) {
377*4882a593Smuzhiyun 			ret = cs35l32_handle_of_data(i2c_client,
378*4882a593Smuzhiyun 						     &cs35l32->pdata);
379*4882a593Smuzhiyun 			if (ret != 0)
380*4882a593Smuzhiyun 				return ret;
381*4882a593Smuzhiyun 		}
382*4882a593Smuzhiyun 	}
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(cs35l32->supplies); i++)
385*4882a593Smuzhiyun 		cs35l32->supplies[i].supply = cs35l32_supply_names[i];
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	ret = devm_regulator_bulk_get(&i2c_client->dev,
388*4882a593Smuzhiyun 				      ARRAY_SIZE(cs35l32->supplies),
389*4882a593Smuzhiyun 				      cs35l32->supplies);
390*4882a593Smuzhiyun 	if (ret != 0) {
391*4882a593Smuzhiyun 		dev_err(&i2c_client->dev,
392*4882a593Smuzhiyun 			"Failed to request supplies: %d\n", ret);
393*4882a593Smuzhiyun 		return ret;
394*4882a593Smuzhiyun 	}
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	ret = regulator_bulk_enable(ARRAY_SIZE(cs35l32->supplies),
397*4882a593Smuzhiyun 				    cs35l32->supplies);
398*4882a593Smuzhiyun 	if (ret != 0) {
399*4882a593Smuzhiyun 		dev_err(&i2c_client->dev,
400*4882a593Smuzhiyun 			"Failed to enable supplies: %d\n", ret);
401*4882a593Smuzhiyun 		return ret;
402*4882a593Smuzhiyun 	}
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	/* Reset the Device */
405*4882a593Smuzhiyun 	cs35l32->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
406*4882a593Smuzhiyun 		"reset", GPIOD_OUT_LOW);
407*4882a593Smuzhiyun 	if (IS_ERR(cs35l32->reset_gpio))
408*4882a593Smuzhiyun 		return PTR_ERR(cs35l32->reset_gpio);
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	gpiod_set_value_cansleep(cs35l32->reset_gpio, 1);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	/* initialize codec */
413*4882a593Smuzhiyun 	ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_AB, &reg);
414*4882a593Smuzhiyun 	devid = (reg & 0xFF) << 12;
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_CD, &reg);
417*4882a593Smuzhiyun 	devid |= (reg & 0xFF) << 4;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_E, &reg);
420*4882a593Smuzhiyun 	devid |= (reg & 0xF0) >> 4;
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	if (devid != CS35L32_CHIP_ID) {
423*4882a593Smuzhiyun 		ret = -ENODEV;
424*4882a593Smuzhiyun 		dev_err(&i2c_client->dev,
425*4882a593Smuzhiyun 			"CS35L32 Device ID (%X). Expected %X\n",
426*4882a593Smuzhiyun 			devid, CS35L32_CHIP_ID);
427*4882a593Smuzhiyun 		return ret;
428*4882a593Smuzhiyun 	}
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	ret = regmap_read(cs35l32->regmap, CS35L32_REV_ID, &reg);
431*4882a593Smuzhiyun 	if (ret < 0) {
432*4882a593Smuzhiyun 		dev_err(&i2c_client->dev, "Get Revision ID failed\n");
433*4882a593Smuzhiyun 		return ret;
434*4882a593Smuzhiyun 	}
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	ret = regmap_register_patch(cs35l32->regmap, cs35l32_monitor_patch,
437*4882a593Smuzhiyun 				    ARRAY_SIZE(cs35l32_monitor_patch));
438*4882a593Smuzhiyun 	if (ret < 0) {
439*4882a593Smuzhiyun 		dev_err(&i2c_client->dev, "Failed to apply errata patch\n");
440*4882a593Smuzhiyun 		return ret;
441*4882a593Smuzhiyun 	}
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	dev_info(&i2c_client->dev,
444*4882a593Smuzhiyun 		 "Cirrus Logic CS35L32, Revision: %02X\n", reg & 0xFF);
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	/* Setup VBOOST Management */
447*4882a593Smuzhiyun 	if (cs35l32->pdata.boost_mng)
448*4882a593Smuzhiyun 		regmap_update_bits(cs35l32->regmap, CS35L32_AUDIO_LED_MNGR,
449*4882a593Smuzhiyun 				   CS35L32_BOOST_MASK,
450*4882a593Smuzhiyun 				cs35l32->pdata.boost_mng);
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	/* Setup ADSP Format Config */
453*4882a593Smuzhiyun 	if (cs35l32->pdata.sdout_share)
454*4882a593Smuzhiyun 		regmap_update_bits(cs35l32->regmap, CS35L32_ADSP_CTL,
455*4882a593Smuzhiyun 				    CS35L32_ADSP_SHARE_MASK,
456*4882a593Smuzhiyun 				cs35l32->pdata.sdout_share << 3);
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	/* Setup ADSP Data Configuration */
459*4882a593Smuzhiyun 	if (cs35l32->pdata.sdout_datacfg)
460*4882a593Smuzhiyun 		regmap_update_bits(cs35l32->regmap, CS35L32_ADSP_CTL,
461*4882a593Smuzhiyun 				   CS35L32_ADSP_DATACFG_MASK,
462*4882a593Smuzhiyun 				cs35l32->pdata.sdout_datacfg << 4);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	/* Setup Low Battery Recovery  */
465*4882a593Smuzhiyun 	if (cs35l32->pdata.batt_recov)
466*4882a593Smuzhiyun 		regmap_update_bits(cs35l32->regmap, CS35L32_BATT_THRESHOLD,
467*4882a593Smuzhiyun 				   CS35L32_BATT_REC_MASK,
468*4882a593Smuzhiyun 				cs35l32->pdata.batt_recov << 1);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	/* Setup Low Battery Threshold */
471*4882a593Smuzhiyun 	if (cs35l32->pdata.batt_thresh)
472*4882a593Smuzhiyun 		regmap_update_bits(cs35l32->regmap, CS35L32_BATT_THRESHOLD,
473*4882a593Smuzhiyun 				   CS35L32_BATT_THRESH_MASK,
474*4882a593Smuzhiyun 				cs35l32->pdata.batt_thresh << 4);
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	/* Power down the AMP */
477*4882a593Smuzhiyun 	regmap_update_bits(cs35l32->regmap, CS35L32_PWRCTL1, CS35L32_PDN_AMP,
478*4882a593Smuzhiyun 			    CS35L32_PDN_AMP);
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	/* Clear MCLK Error Bit since we don't have the clock yet */
481*4882a593Smuzhiyun 	ret = regmap_read(cs35l32->regmap, CS35L32_INT_STATUS_1, &reg);
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(&i2c_client->dev,
484*4882a593Smuzhiyun 			&soc_component_dev_cs35l32, cs35l32_dai,
485*4882a593Smuzhiyun 			ARRAY_SIZE(cs35l32_dai));
486*4882a593Smuzhiyun 	if (ret < 0)
487*4882a593Smuzhiyun 		goto err_disable;
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	return 0;
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun err_disable:
492*4882a593Smuzhiyun 	regulator_bulk_disable(ARRAY_SIZE(cs35l32->supplies),
493*4882a593Smuzhiyun 			       cs35l32->supplies);
494*4882a593Smuzhiyun 	return ret;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun 
cs35l32_i2c_remove(struct i2c_client * i2c_client)497*4882a593Smuzhiyun static int cs35l32_i2c_remove(struct i2c_client *i2c_client)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun 	struct cs35l32_private *cs35l32 = i2c_get_clientdata(i2c_client);
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	/* Hold down reset */
502*4882a593Smuzhiyun 	gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	return 0;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun #ifdef CONFIG_PM
cs35l32_runtime_suspend(struct device * dev)508*4882a593Smuzhiyun static int cs35l32_runtime_suspend(struct device *dev)
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun 	struct cs35l32_private *cs35l32 = dev_get_drvdata(dev);
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	regcache_cache_only(cs35l32->regmap, true);
513*4882a593Smuzhiyun 	regcache_mark_dirty(cs35l32->regmap);
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	/* Hold down reset */
516*4882a593Smuzhiyun 	gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	/* remove power */
519*4882a593Smuzhiyun 	regulator_bulk_disable(ARRAY_SIZE(cs35l32->supplies),
520*4882a593Smuzhiyun 			       cs35l32->supplies);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	return 0;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun 
cs35l32_runtime_resume(struct device * dev)525*4882a593Smuzhiyun static int cs35l32_runtime_resume(struct device *dev)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun 	struct cs35l32_private *cs35l32 = dev_get_drvdata(dev);
528*4882a593Smuzhiyun 	int ret;
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	/* Enable power */
531*4882a593Smuzhiyun 	ret = regulator_bulk_enable(ARRAY_SIZE(cs35l32->supplies),
532*4882a593Smuzhiyun 				    cs35l32->supplies);
533*4882a593Smuzhiyun 	if (ret != 0) {
534*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable supplies: %d\n",
535*4882a593Smuzhiyun 			ret);
536*4882a593Smuzhiyun 		return ret;
537*4882a593Smuzhiyun 	}
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	gpiod_set_value_cansleep(cs35l32->reset_gpio, 1);
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	regcache_cache_only(cs35l32->regmap, false);
542*4882a593Smuzhiyun 	regcache_sync(cs35l32->regmap);
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun 	return 0;
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun #endif
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun static const struct dev_pm_ops cs35l32_runtime_pm = {
549*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(cs35l32_runtime_suspend, cs35l32_runtime_resume,
550*4882a593Smuzhiyun 			   NULL)
551*4882a593Smuzhiyun };
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun static const struct of_device_id cs35l32_of_match[] = {
554*4882a593Smuzhiyun 	{ .compatible = "cirrus,cs35l32", },
555*4882a593Smuzhiyun 	{},
556*4882a593Smuzhiyun };
557*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, cs35l32_of_match);
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun static const struct i2c_device_id cs35l32_id[] = {
561*4882a593Smuzhiyun 	{"cs35l32", 0},
562*4882a593Smuzhiyun 	{}
563*4882a593Smuzhiyun };
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, cs35l32_id);
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun static struct i2c_driver cs35l32_i2c_driver = {
568*4882a593Smuzhiyun 	.driver = {
569*4882a593Smuzhiyun 		   .name = "cs35l32",
570*4882a593Smuzhiyun 		   .pm = &cs35l32_runtime_pm,
571*4882a593Smuzhiyun 		   .of_match_table = cs35l32_of_match,
572*4882a593Smuzhiyun 		   },
573*4882a593Smuzhiyun 	.id_table = cs35l32_id,
574*4882a593Smuzhiyun 	.probe = cs35l32_i2c_probe,
575*4882a593Smuzhiyun 	.remove = cs35l32_i2c_remove,
576*4882a593Smuzhiyun };
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun module_i2c_driver(cs35l32_i2c_driver);
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC CS35L32 driver");
581*4882a593Smuzhiyun MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
582*4882a593Smuzhiyun MODULE_LICENSE("GPL");
583