1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun #ifndef __AW_SPIN_H__ 3*4882a593Smuzhiyun #define __AW_SPIN_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /*#define AW_MTK_PLATFORM_SPIN*/ 6*4882a593Smuzhiyun /*#define AW_QCOM_PLATFORM_SPIN*/ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define AW_DSP_TRY_TIME (3) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define AW_DSP_MSG_HDR_VER (1) 11*4882a593Smuzhiyun #define AFE_MSG_ID_MSG_0 (0X10013D2A) 12*4882a593Smuzhiyun #define AFE_MSG_ID_MSG_1 (0X10013D2B) 13*4882a593Smuzhiyun #define AW_RX_PORT_ID (0x1006) 14*4882a593Smuzhiyun #define AW_RX_TOPO_ID (0x1000FF01) 15*4882a593Smuzhiyun #define AW_MSG_ID_SPIN (0x10013D2E) 16*4882a593Smuzhiyun #define AW_INLINE_ID_AUDIO_MIX (0x0000000B) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun enum { 19*4882a593Smuzhiyun AW_DEV_CH_PRI_L = 0, 20*4882a593Smuzhiyun AW_DEV_CH_PRI_R = 1, 21*4882a593Smuzhiyun AW_DEV_CH_SEC_L = 2, 22*4882a593Smuzhiyun AW_DEV_CH_SEC_R = 3, 23*4882a593Smuzhiyun AW_DEV_CHAN_MAX, 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun enum aw_dsp_msg_type { 27*4882a593Smuzhiyun AW_DSP_MSG_TYPE_DATA = 0, 28*4882a593Smuzhiyun AW_DSP_MSG_TYPE_CMD = 1, 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum { 32*4882a593Smuzhiyun AW_SPIN_OFF = 0, 33*4882a593Smuzhiyun AW_SPIN_ON = 1, 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun enum { 37*4882a593Smuzhiyun AW_SPIN_0 = 0, 38*4882a593Smuzhiyun AW_SPIN_90, 39*4882a593Smuzhiyun AW_SPIN_180, 40*4882a593Smuzhiyun AW_SPIN_270, 41*4882a593Smuzhiyun AW_SPIN_MAX, 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun enum { 45*4882a593Smuzhiyun AW_SPIN_OFF_MODE = 0, 46*4882a593Smuzhiyun AW_ADSP_SPIN_MODE, 47*4882a593Smuzhiyun AW_REG_SPIN_MODE, 48*4882a593Smuzhiyun AW_REG_MIXER_SPIN_MODE, 49*4882a593Smuzhiyun AW_SPIN_MODE_MAX, 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun enum { 53*4882a593Smuzhiyun AW_AUDIO_MIX_DISABLE = 0, 54*4882a593Smuzhiyun AW_AUDIO_MIX_ENABLE, 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct aw_spin_ch { 58*4882a593Smuzhiyun uint16_t rx_val; 59*4882a593Smuzhiyun uint16_t tx_val; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct aw_spin_desc { 63*4882a593Smuzhiyun struct aw_spin_ch spin_table[AW_SPIN_MAX]; 64*4882a593Smuzhiyun uint32_t spin_mode; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun int aw_check_spin_mode(struct aw_spin_desc *spin_desc); 68*4882a593Smuzhiyun int aw_hold_dsp_spin_st(struct aw_spin_desc *spin_desc); 69*4882a593Smuzhiyun int aw_hold_reg_spin_st(struct aw_spin_desc *spin_desc); 70*4882a593Smuzhiyun void aw_add_spin_controls(void *aw_dev); 71*4882a593Smuzhiyun void aw_spin_init(struct aw_spin_desc *spin_desc); 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif 74