1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __AWINIC_DEVICE_FILE_H__ 4*4882a593Smuzhiyun #define __AWINIC_DEVICE_FILE_H__ 5*4882a593Smuzhiyun #include "aw_spin.h" 6*4882a593Smuzhiyun #include "aw_monitor.h" 7*4882a593Smuzhiyun #include "aw_data_type.h" 8*4882a593Smuzhiyun #include "aw_calib.h" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define AW_DEV_DEFAULT_CH (0) 11*4882a593Smuzhiyun #define AW_DEV_I2S_CHECK_MAX (5) 12*4882a593Smuzhiyun #define AW_DEV_DSP_CHECK_MAX (5) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /******************************************** 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * DSP I2C WRITES 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun *******************************************/ 20*4882a593Smuzhiyun #define AW_DSP_I2C_WRITES 21*4882a593Smuzhiyun #define AW_MAX_RAM_WRITE_BYTE_SIZE (128) 22*4882a593Smuzhiyun #define AW_DSP_ODD_NUM_BIT_TEST (0x5555) 23*4882a593Smuzhiyun #define AW_DSP_EVEN_NUM_BIT_TEST (0xAAAA) 24*4882a593Smuzhiyun #define AW_DSP_ST_CHECK_MAX (2) 25*4882a593Smuzhiyun #define AW_FADE_IN_OUT_DEFAULT (0) 26*4882a593Smuzhiyun #define AW_CALI_DELAY_CACL(value) ((value * 32) / 48) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct aw_device; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun enum { 31*4882a593Smuzhiyun AW_DEV_VDSEL_DAC = 0, 32*4882a593Smuzhiyun AW_DEV_VDSEL_VSENSE = 1, 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun enum { 36*4882a593Smuzhiyun AW_DSP_CRC_NA = 0, 37*4882a593Smuzhiyun AW_DSP_CRC_OK = 1, 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun enum { 41*4882a593Smuzhiyun AW_DSP_CRC_DISABLE = 0, 42*4882a593Smuzhiyun AW_DSP_CRC_ENABLE = 1, 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun enum { 46*4882a593Smuzhiyun AW_DSP_FW_UPDATE_OFF = 0, 47*4882a593Smuzhiyun AW_DSP_FW_UPDATE_ON = 1, 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun enum { 51*4882a593Smuzhiyun AW_FORCE_UPDATE_OFF = 0, 52*4882a593Smuzhiyun AW_FORCE_UPDATE_ON = 1, 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun enum { 56*4882a593Smuzhiyun AW_1000_US = 1000, 57*4882a593Smuzhiyun AW_2000_US = 2000, 58*4882a593Smuzhiyun AW_3000_US = 3000, 59*4882a593Smuzhiyun AW_4000_US = 4000, 60*4882a593Smuzhiyun AW_5000_US = 5000, 61*4882a593Smuzhiyun AW_10000_US = 10000, 62*4882a593Smuzhiyun AW_100000_US = 100000, 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun enum { 66*4882a593Smuzhiyun AW_DEV_TYPE_OK = 0, 67*4882a593Smuzhiyun AW_DEV_TYPE_NONE = 1, 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun enum AW_DEV_STATUS { 72*4882a593Smuzhiyun AW_DEV_PW_OFF = 0, 73*4882a593Smuzhiyun AW_DEV_PW_ON, 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun enum AW_DEV_FW_STATUS { 77*4882a593Smuzhiyun AW_DEV_FW_FAILED = 0, 78*4882a593Smuzhiyun AW_DEV_FW_OK, 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun enum AW_DEV_MEMCLK { 82*4882a593Smuzhiyun AW_DEV_MEMCLK_OSC = 0, 83*4882a593Smuzhiyun AW_DEV_MEMCLK_PLL = 1, 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun enum AW_DEV_DSP_CFG { 87*4882a593Smuzhiyun AW_DEV_DSP_WORK = 0, 88*4882a593Smuzhiyun AW_DEV_DSP_BYPASS = 1, 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun enum { 92*4882a593Smuzhiyun AW_DSP_16_DATA = 0, 93*4882a593Smuzhiyun AW_DSP_32_DATA = 1, 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun enum aw_platform { 97*4882a593Smuzhiyun AW_QCOM = 0, 98*4882a593Smuzhiyun AW_MTK = 1, 99*4882a593Smuzhiyun AW_SPRD = 2, 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun enum { 103*4882a593Smuzhiyun AW_NOT_RCV_MODE = 0, 104*4882a593Smuzhiyun AW_RCV_MODE = 1, 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun struct aw_device_ops { 108*4882a593Smuzhiyun int (*aw_i2c_writes)(struct aw_device *aw_dev, uint8_t reg_addr, uint8_t *buf, uint16_t len); 109*4882a593Smuzhiyun int (*aw_i2c_write)(struct aw_device *aw_dev, uint8_t reg_addr, uint16_t reg_data); 110*4882a593Smuzhiyun int (*aw_i2c_read)(struct aw_device *aw_dev, uint8_t reg_addr, uint16_t *reg_data); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun int (*aw_reg_write)(struct aw_device *aw_dev, uint8_t reg_addr, uint16_t reg_data); 113*4882a593Smuzhiyun int (*aw_reg_read)(struct aw_device *aw_dev, uint8_t reg_addr, uint16_t *reg_data); 114*4882a593Smuzhiyun int (*aw_reg_write_bits)(struct aw_device *aw_dev, uint8_t reg_addr, uint16_t mask, uint16_t reg_data); 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun int (*aw_dsp_write)(struct aw_device *aw_dev, uint16_t dsp_addr, uint32_t reg_data, uint8_t data_type); 117*4882a593Smuzhiyun int (*aw_dsp_read)(struct aw_device *aw_dev, uint16_t dsp_addr, uint32_t *dsp_data, uint8_t data_type); 118*4882a593Smuzhiyun int (*aw_dsp_write_bits)(struct aw_device *aw_dev, uint16_t dsp_addr, uint16_t mask, uint16_t dsp_data); 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun int (*aw_set_volume)(struct aw_device *aw_dev, uint16_t value); 121*4882a593Smuzhiyun int (*aw_get_volume)(struct aw_device *aw_dev, uint16_t *value); 122*4882a593Smuzhiyun unsigned int (*aw_reg_val_to_db)(unsigned int value); 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun void (*aw_i2s_tx_enable)(struct aw_device *aw_dev, bool flag); 125*4882a593Smuzhiyun int (*aw_get_dev_num)(void); 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun bool (*aw_check_wr_access)(int reg); 128*4882a593Smuzhiyun bool (*aw_check_rd_access)(int reg); 129*4882a593Smuzhiyun int (*aw_get_reg_num)(void); 130*4882a593Smuzhiyun int (*aw_get_version)(char *buf, int size); 131*4882a593Smuzhiyun int (*aw_read_dsp_pid)(struct aw_device *aw_dev); 132*4882a593Smuzhiyun int (*aw_get_hw_mon_st)(struct aw_device *aw_dev, bool *is_enable, uint8_t *temp_flag); 133*4882a593Smuzhiyun int (*aw_cali_svc_get_iv_st)(struct aw_device *aw_dev); 134*4882a593Smuzhiyun void (*aw_set_cfg_f0_fs)(struct aw_device *aw_dev, uint32_t *f0_fs); 135*4882a593Smuzhiyun int (*aw_dsp_fw_check)(struct aw_device *aw_dev); 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun struct aw_int_desc { 139*4882a593Smuzhiyun unsigned int mask_reg; /*interrupt mask reg*/ 140*4882a593Smuzhiyun unsigned int st_reg; /*interrupt status reg*/ 141*4882a593Smuzhiyun unsigned int mask_default; /*default mask close all*/ 142*4882a593Smuzhiyun unsigned int int_mask; /*set mask*/ 143*4882a593Smuzhiyun unsigned int intst_mask; /*interrupt check mask*/ 144*4882a593Smuzhiyun uint16_t sysint_st; /*interrupt reg status*/ 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun struct aw_pwd_desc { 148*4882a593Smuzhiyun unsigned int reg; 149*4882a593Smuzhiyun unsigned int mask; 150*4882a593Smuzhiyun unsigned int enable; 151*4882a593Smuzhiyun unsigned int disable; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun struct aw_vcalb_desc { 155*4882a593Smuzhiyun unsigned int icalk_reg; 156*4882a593Smuzhiyun unsigned int icalk_reg_mask; 157*4882a593Smuzhiyun unsigned int icalk_sign_mask; 158*4882a593Smuzhiyun unsigned int icalk_neg_mask; 159*4882a593Smuzhiyun int icalk_value_factor; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun unsigned int vcalk_reg; 162*4882a593Smuzhiyun unsigned int vcalk_reg_mask; 163*4882a593Smuzhiyun unsigned int vcalk_sign_mask; 164*4882a593Smuzhiyun unsigned int vcalk_neg_mask; 165*4882a593Smuzhiyun unsigned int vcalk_shift; 166*4882a593Smuzhiyun int vcalk_value_factor; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun unsigned int vcalb_dsp_reg; 169*4882a593Smuzhiyun unsigned char data_type; 170*4882a593Smuzhiyun int cabl_base_value; 171*4882a593Smuzhiyun int vcal_factor; 172*4882a593Smuzhiyun int vscal_factor; 173*4882a593Smuzhiyun int iscal_factor; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun unsigned int vcalb_adj_shift; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun unsigned int vcalb_vsense_reg; 178*4882a593Smuzhiyun int vscal_factor_vsense_in; 179*4882a593Smuzhiyun int vcalk_value_factor_vsense_in; 180*4882a593Smuzhiyun unsigned int vcalk_dac_shift; 181*4882a593Smuzhiyun unsigned int vcalk_dac_mask; 182*4882a593Smuzhiyun unsigned int vcalk_dac_neg_mask; 183*4882a593Smuzhiyun unsigned int vcalk_vdsel_mask; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun struct aw_mute_desc { 187*4882a593Smuzhiyun unsigned int reg; 188*4882a593Smuzhiyun unsigned int mask; 189*4882a593Smuzhiyun unsigned int enable; 190*4882a593Smuzhiyun unsigned int disable; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun struct aw_sysst_desc { 194*4882a593Smuzhiyun unsigned int reg; 195*4882a593Smuzhiyun unsigned int st_check; 196*4882a593Smuzhiyun unsigned int st_mask; 197*4882a593Smuzhiyun unsigned int pll_check; 198*4882a593Smuzhiyun unsigned int dsp_check; 199*4882a593Smuzhiyun unsigned int dsp_mask; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun struct aw_profctrl_desc { 203*4882a593Smuzhiyun unsigned int reg; 204*4882a593Smuzhiyun unsigned int mask; 205*4882a593Smuzhiyun unsigned int rcv_mode_val; 206*4882a593Smuzhiyun unsigned int cur_mode; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun struct aw_volume_desc { 210*4882a593Smuzhiyun unsigned int reg; 211*4882a593Smuzhiyun unsigned int mask; 212*4882a593Smuzhiyun unsigned int shift; 213*4882a593Smuzhiyun int init_volume; 214*4882a593Smuzhiyun int mute_volume; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun struct aw_dsp_en_desc { 218*4882a593Smuzhiyun unsigned int reg; 219*4882a593Smuzhiyun unsigned int mask; 220*4882a593Smuzhiyun unsigned int enable; 221*4882a593Smuzhiyun unsigned int disable; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun struct aw_memclk_desc { 225*4882a593Smuzhiyun unsigned int reg; 226*4882a593Smuzhiyun unsigned int mask; 227*4882a593Smuzhiyun unsigned int mcu_hclk; 228*4882a593Smuzhiyun unsigned int osc_clk; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun struct aw_watch_dog_desc { 232*4882a593Smuzhiyun unsigned int reg; 233*4882a593Smuzhiyun unsigned int mask; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun struct aw_dsp_mem_desc { 237*4882a593Smuzhiyun unsigned int dsp_madd_reg; 238*4882a593Smuzhiyun unsigned int dsp_mdat_reg; 239*4882a593Smuzhiyun unsigned int dsp_fw_base_addr; 240*4882a593Smuzhiyun unsigned int dsp_cfg_base_addr; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun struct aw_voltage_desc { 244*4882a593Smuzhiyun unsigned int reg; 245*4882a593Smuzhiyun unsigned int vbat_range; 246*4882a593Smuzhiyun unsigned int int_bit; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun struct aw_temperature_desc { 250*4882a593Smuzhiyun unsigned int reg; 251*4882a593Smuzhiyun unsigned int sign_mask; 252*4882a593Smuzhiyun unsigned int neg_mask; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun struct aw_ipeak_desc { 256*4882a593Smuzhiyun unsigned int reg; 257*4882a593Smuzhiyun unsigned int mask; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun struct aw_vmax_desc { 261*4882a593Smuzhiyun unsigned int dsp_reg; 262*4882a593Smuzhiyun unsigned char data_type; 263*4882a593Smuzhiyun unsigned int init_vmax; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun struct aw_soft_rst { 267*4882a593Smuzhiyun uint8_t reg; 268*4882a593Smuzhiyun uint16_t reg_value; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun struct aw_cali_cfg_desc { 272*4882a593Smuzhiyun unsigned int actampth_reg; 273*4882a593Smuzhiyun unsigned char actampth_data_type; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun unsigned int noiseampth_reg; 276*4882a593Smuzhiyun unsigned char noiseampth_data_type; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun unsigned int ustepn_reg; 279*4882a593Smuzhiyun unsigned char ustepn_data_type; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun unsigned int alphan_reg; 282*4882a593Smuzhiyun unsigned int alphan_data_type; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun struct aw_dsp_vol_desc { 286*4882a593Smuzhiyun unsigned int reg; 287*4882a593Smuzhiyun unsigned int mute_st; 288*4882a593Smuzhiyun unsigned int noise_st; 289*4882a593Smuzhiyun unsigned int mask; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun struct aw_amppd_desc { 293*4882a593Smuzhiyun unsigned int reg; 294*4882a593Smuzhiyun unsigned int mask; 295*4882a593Smuzhiyun unsigned int enable; 296*4882a593Smuzhiyun unsigned int disable; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun struct aw_f0_desc { 300*4882a593Smuzhiyun unsigned int dsp_reg; 301*4882a593Smuzhiyun unsigned char data_type; 302*4882a593Smuzhiyun unsigned int shift; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun struct aw_cfgf0_fs_desc { 306*4882a593Smuzhiyun unsigned int dsp_reg; 307*4882a593Smuzhiyun unsigned char data_type; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun struct aw_q_desc { 311*4882a593Smuzhiyun unsigned int dsp_reg; 312*4882a593Smuzhiyun unsigned char data_type; 313*4882a593Smuzhiyun unsigned int shift; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun struct aw_ra_desc { 317*4882a593Smuzhiyun unsigned int dsp_reg; 318*4882a593Smuzhiyun unsigned char data_type; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun struct aw_noise_desc { 322*4882a593Smuzhiyun unsigned int dsp_reg; 323*4882a593Smuzhiyun unsigned char data_type; 324*4882a593Smuzhiyun unsigned int mask; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun struct aw_hw_mon_desc { 328*4882a593Smuzhiyun unsigned int dsp_reg; 329*4882a593Smuzhiyun unsigned char data_type; 330*4882a593Smuzhiyun unsigned int mask; 331*4882a593Smuzhiyun unsigned int enable; 332*4882a593Smuzhiyun unsigned int disable; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun struct aw_ste_re_desc { 336*4882a593Smuzhiyun unsigned int dsp_reg; 337*4882a593Smuzhiyun unsigned char data_type; 338*4882a593Smuzhiyun unsigned int shift; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun struct aw_adpz_re_desc { 342*4882a593Smuzhiyun unsigned int dsp_reg; 343*4882a593Smuzhiyun unsigned char data_type; 344*4882a593Smuzhiyun unsigned int shift; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun struct aw_adpz_t0_desc { 348*4882a593Smuzhiyun unsigned int dsp_reg; 349*4882a593Smuzhiyun unsigned char data_type; 350*4882a593Smuzhiyun uint16_t coilalpha_reg; 351*4882a593Smuzhiyun unsigned char coil_type; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun struct aw_spkr_temp_desc { 355*4882a593Smuzhiyun unsigned int reg; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun struct aw_dsp_crc_desc { 359*4882a593Smuzhiyun unsigned int ctl_reg; 360*4882a593Smuzhiyun unsigned int ctl_mask; 361*4882a593Smuzhiyun unsigned int ctl_enable; 362*4882a593Smuzhiyun unsigned int ctl_disable; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun unsigned int dsp_reg; 365*4882a593Smuzhiyun unsigned char data_type; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun struct aw_cco_mux_desc { 369*4882a593Smuzhiyun unsigned int reg; 370*4882a593Smuzhiyun unsigned int mask; 371*4882a593Smuzhiyun unsigned int divider; 372*4882a593Smuzhiyun unsigned int bypass; 373*4882a593Smuzhiyun }; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun struct aw_hw_temp_desc { 376*4882a593Smuzhiyun unsigned int dsp_reg; 377*4882a593Smuzhiyun unsigned char data_type; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun struct aw_re_range_desc { 381*4882a593Smuzhiyun uint32_t re_min; 382*4882a593Smuzhiyun uint32_t re_max; 383*4882a593Smuzhiyun uint32_t re_min_default; 384*4882a593Smuzhiyun uint32_t re_max_default; 385*4882a593Smuzhiyun }; 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun struct aw_cali_delay_desc { 388*4882a593Smuzhiyun unsigned int dsp_reg; 389*4882a593Smuzhiyun unsigned char data_type; 390*4882a593Smuzhiyun unsigned int delay; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun struct aw_chansel_desc { 394*4882a593Smuzhiyun unsigned int rxchan_reg; 395*4882a593Smuzhiyun unsigned int rxchan_mask; 396*4882a593Smuzhiyun unsigned int txchan_reg; 397*4882a593Smuzhiyun unsigned int txchan_mask; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun unsigned int rx_left; 400*4882a593Smuzhiyun unsigned int rx_right; 401*4882a593Smuzhiyun unsigned int tx_left; 402*4882a593Smuzhiyun unsigned int tx_right; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun struct aw_tx_en_desc { 406*4882a593Smuzhiyun unsigned int tx_en_mask; 407*4882a593Smuzhiyun unsigned int tx_disable; 408*4882a593Smuzhiyun }; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun struct aw_dsp_st { 411*4882a593Smuzhiyun unsigned int dsp_reg_s1; 412*4882a593Smuzhiyun unsigned int dsp_reg_e1; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun unsigned int dsp_reg_s2; 415*4882a593Smuzhiyun unsigned int dsp_reg_e2; 416*4882a593Smuzhiyun }; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun struct aw_container { 419*4882a593Smuzhiyun int len; 420*4882a593Smuzhiyun uint8_t data[]; 421*4882a593Smuzhiyun }; 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun struct aw_device { 424*4882a593Smuzhiyun int status; 425*4882a593Smuzhiyun struct mutex *i2c_lock; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun unsigned char cur_prof; /*current profile index*/ 428*4882a593Smuzhiyun unsigned char set_prof; /*set profile index*/ 429*4882a593Smuzhiyun unsigned char dsp_crc_st; 430*4882a593Smuzhiyun uint16_t chip_id; 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun unsigned int channel; /*pa channel select*/ 433*4882a593Smuzhiyun unsigned int fade_step; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun struct i2c_client *i2c; 436*4882a593Smuzhiyun struct device *dev; 437*4882a593Smuzhiyun char *acf; 438*4882a593Smuzhiyun void *private_data; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun uint32_t fade_en; 441*4882a593Smuzhiyun unsigned char dsp_cfg; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun uint32_t dsp_fw_len; 444*4882a593Smuzhiyun uint32_t dsp_cfg_len; 445*4882a593Smuzhiyun uint8_t platform; 446*4882a593Smuzhiyun uint8_t fw_status; /*load cfg status*/ 447*4882a593Smuzhiyun struct aw_prof_info prof_info; 448*4882a593Smuzhiyun struct aw_sec_data_desc crc_dsp_cfg; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun struct aw_int_desc int_desc; 451*4882a593Smuzhiyun struct aw_pwd_desc pwd_desc; 452*4882a593Smuzhiyun struct aw_mute_desc mute_desc; 453*4882a593Smuzhiyun struct aw_vcalb_desc vcalb_desc; 454*4882a593Smuzhiyun struct aw_sysst_desc sysst_desc; 455*4882a593Smuzhiyun struct aw_profctrl_desc profctrl_desc; 456*4882a593Smuzhiyun struct aw_volume_desc volume_desc; 457*4882a593Smuzhiyun struct aw_dsp_en_desc dsp_en_desc; 458*4882a593Smuzhiyun struct aw_memclk_desc memclk_desc; 459*4882a593Smuzhiyun struct aw_watch_dog_desc watch_dog_desc; 460*4882a593Smuzhiyun struct aw_dsp_mem_desc dsp_mem_desc; 461*4882a593Smuzhiyun struct aw_voltage_desc voltage_desc; 462*4882a593Smuzhiyun struct aw_temperature_desc temp_desc; 463*4882a593Smuzhiyun struct aw_vmax_desc vmax_desc; 464*4882a593Smuzhiyun struct aw_ipeak_desc ipeak_desc; 465*4882a593Smuzhiyun struct aw_soft_rst soft_rst; 466*4882a593Smuzhiyun struct aw_cali_cfg_desc cali_cfg_desc; 467*4882a593Smuzhiyun struct aw_ra_desc ra_desc; 468*4882a593Smuzhiyun struct aw_dsp_vol_desc dsp_vol_desc; 469*4882a593Smuzhiyun struct aw_noise_desc noise_desc; 470*4882a593Smuzhiyun struct aw_f0_desc f0_desc; 471*4882a593Smuzhiyun struct aw_cfgf0_fs_desc cfgf0_fs_desc; 472*4882a593Smuzhiyun struct aw_q_desc q_desc; 473*4882a593Smuzhiyun struct aw_hw_mon_desc hw_mon_desc; 474*4882a593Smuzhiyun struct aw_ste_re_desc ste_re_desc; 475*4882a593Smuzhiyun struct aw_adpz_re_desc adpz_re_desc; 476*4882a593Smuzhiyun struct aw_adpz_t0_desc t0_desc; 477*4882a593Smuzhiyun struct aw_amppd_desc amppd_desc; 478*4882a593Smuzhiyun struct aw_spkr_temp_desc spkr_temp_desc; 479*4882a593Smuzhiyun struct aw_dsp_crc_desc dsp_crc_desc; 480*4882a593Smuzhiyun struct aw_cco_mux_desc cco_mux_desc; 481*4882a593Smuzhiyun struct aw_hw_temp_desc hw_temp_desc; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun struct aw_cali_desc cali_desc; 484*4882a593Smuzhiyun struct aw_monitor_desc monitor_desc; 485*4882a593Smuzhiyun struct aw_re_range_desc re_range; 486*4882a593Smuzhiyun struct aw_spin_desc spin_desc; 487*4882a593Smuzhiyun struct aw_chansel_desc chansel_desc; 488*4882a593Smuzhiyun struct aw_tx_en_desc tx_en_desc; 489*4882a593Smuzhiyun struct aw_cali_delay_desc cali_delay_desc; 490*4882a593Smuzhiyun struct aw_dsp_st dsp_st_desc; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun struct aw_device_ops ops; 493*4882a593Smuzhiyun struct list_head list_node; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun void aw_dev_deinit(struct aw_device *aw_dev); 498*4882a593Smuzhiyun int aw_device_init(struct aw_device *aw_dev, struct aw_container *aw_prof); 499*4882a593Smuzhiyun int aw_device_start(struct aw_device *aw_dev); 500*4882a593Smuzhiyun int aw_device_stop(struct aw_device *aw_dev); 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun int aw_dev_fw_update(struct aw_device *aw_dev, bool up_dsp_fw_en, bool force_up_en); 503*4882a593Smuzhiyun int aw_dev_get_int_status(struct aw_device *aw_dev, uint16_t *int_status); 504*4882a593Smuzhiyun void aw_dev_set_volume_step(struct aw_device *aw_dev, unsigned int step); 505*4882a593Smuzhiyun int aw_dev_set_intmask(struct aw_device *aw_dev, bool flag); 506*4882a593Smuzhiyun void aw_dev_clear_int_status(struct aw_device *aw_dev); 507*4882a593Smuzhiyun int aw_dev_get_volume_step(struct aw_device *aw_dev); 508*4882a593Smuzhiyun int aw_device_probe(struct aw_device *aw_dev); 509*4882a593Smuzhiyun int aw_device_remove(struct aw_device *aw_dev); 510*4882a593Smuzhiyun int aw_dev_syspll_check(struct aw_device *aw_dev); 511*4882a593Smuzhiyun int aw_dev_get_dsp_status(struct aw_device *aw_dev); 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun void aw_dev_set_fade_vol_step(struct aw_device *aw_dev, unsigned int step); 514*4882a593Smuzhiyun int aw_dev_get_fade_vol_step(struct aw_device *aw_dev); 515*4882a593Smuzhiyun void aw_dev_get_fade_time(unsigned int *time, bool fade_in); 516*4882a593Smuzhiyun void aw_dev_set_fade_time(unsigned int time, bool fade_in); 517*4882a593Smuzhiyun int aw_dev_get_hmute(struct aw_device *aw_dev); 518*4882a593Smuzhiyun int aw_dev_sysst_check(struct aw_device *aw_dev); 519*4882a593Smuzhiyun int aw_dev_get_list_head(struct list_head **head); 520*4882a593Smuzhiyun int aw_dev_dsp_check(struct aw_device *aw_dev); 521*4882a593Smuzhiyun void aw_dev_memclk_select(struct aw_device *aw_dev, unsigned char flag); 522*4882a593Smuzhiyun void aw_dev_dsp_enable(struct aw_device *aw_dev, bool dsp); 523*4882a593Smuzhiyun void aw_dev_mute(struct aw_device *aw_dev, bool mute); 524*4882a593Smuzhiyun int aw_dev_dsp_fw_update(struct aw_device *aw_dev, 525*4882a593Smuzhiyun uint8_t *data, uint32_t len); 526*4882a593Smuzhiyun int aw_dev_dsp_cfg_update(struct aw_device *aw_dev, 527*4882a593Smuzhiyun uint8_t *data, uint32_t len); 528*4882a593Smuzhiyun int aw_dev_modify_dsp_cfg(struct aw_device *aw_dev, 529*4882a593Smuzhiyun unsigned int addr, uint32_t dsp_data, unsigned char data_type); 530*4882a593Smuzhiyun int aw_dev_get_iis_status(struct aw_device *aw_dev); 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun #endif 533*4882a593Smuzhiyun 534