xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/aw883xx/aw883xx.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun 
3*4882a593Smuzhiyun #ifndef __AW883XX_H__
4*4882a593Smuzhiyun #define __AW883XX_H__
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/version.h>
7*4882a593Smuzhiyun #include <sound/control.h>
8*4882a593Smuzhiyun #include <sound/soc.h>
9*4882a593Smuzhiyun #include "aw_device.h"
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun /*#define AW_QCOM_PLATFORM*/
12*4882a593Smuzhiyun #define AW_MTK_PLATFORM
13*4882a593Smuzhiyun /*#define AW_SPRD_PLATFORM*/
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define AW883XX_CHIP_ID_REG	(0x00)
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 1)
18*4882a593Smuzhiyun #define AW_KERNEL_VER_OVER_4_19_1
19*4882a593Smuzhiyun #endif
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)
22*4882a593Smuzhiyun #define AW_KERNEL_VER_OVER_5_4_0
23*4882a593Smuzhiyun MODULE_IMPORT_NS(VFS_internal_I_am_really_a_filesystem_and_am_NOT_a_driver);
24*4882a593Smuzhiyun #endif
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /* i2c transaction on Linux limited to 64k
27*4882a593Smuzhiyun  * (See Linux kernel documentation: Documentation/i2c/writing-clients)
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun #define MAX_I2C_BUFFER_SIZE		(65536)
30*4882a593Smuzhiyun #define AW883XX_READ_MSG_NUM		(2)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define AW_I2C_RETRIES			(5)
33*4882a593Smuzhiyun #define AW_I2C_RETRY_DELAY		(5)/* 5ms */
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define AW_READ_CHIPID_RETRY_DELAY	(5)/* 5ms */
36*4882a593Smuzhiyun #define AW_START_RETRIES		(5)
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define AW883XX_FLAG_START_ON_MUTE	(1 << 0)
39*4882a593Smuzhiyun #define AW883XX_FLAG_SKIP_INTERRUPTS	(1 << 1)
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define AW883XX_I2S_CHECK_MAX		(5)
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define AW883XX_SYSST_CHECK_MAX		(10)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define AW883XX_BIN_TYPE_NUM		(3)
46*4882a593Smuzhiyun #define AW883XX_LOAD_FW_DELAY_TIME	(3000)
47*4882a593Smuzhiyun #define AW883XX_START_WORK_DELAY_MS	(0)
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define AW883XX_DSP_16_DATA_MASK	(0x0000ffff)
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define AW_GET_IV_CNT_MAX		(6)
53*4882a593Smuzhiyun #define AW_KCONTROL_NUM			(3)
54*4882a593Smuzhiyun #define AW_HW_MONITOR_DELAY		(1000)
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun enum {
57*4882a593Smuzhiyun 	AWRW_I2C_ST_NONE = 0,
58*4882a593Smuzhiyun 	AWRW_I2C_ST_READ,
59*4882a593Smuzhiyun 	AWRW_I2C_ST_WRITE,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun enum {
63*4882a593Smuzhiyun 	AWRW_DSP_ST_NONE = 0,
64*4882a593Smuzhiyun 	AWRW_DSP_READY,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun enum {
68*4882a593Smuzhiyun 	AW_SYNC_START = 0,
69*4882a593Smuzhiyun 	AW_ASYNC_START,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define AWRW_ADDR_BYTES (1)
74*4882a593Smuzhiyun #define AWRW_DATA_BYTES (2)
75*4882a593Smuzhiyun #define AWRW_HDR_LEN (24)
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun enum {
78*4882a593Smuzhiyun 	AWRW_FLAG_WRITE = 0,
79*4882a593Smuzhiyun 	AWRW_FLAG_READ,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun enum {
83*4882a593Smuzhiyun 	AWRW_HDR_WR_FLAG = 0,
84*4882a593Smuzhiyun 	AWRW_HDR_ADDR_BYTES,
85*4882a593Smuzhiyun 	AWRW_HDR_DATA_BYTES,
86*4882a593Smuzhiyun 	AWRW_HDR_REG_NUM,
87*4882a593Smuzhiyun 	AWRW_HDR_REG_ADDR,
88*4882a593Smuzhiyun 	AWRW_HDR_MAX,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun struct aw883xx_i2c_packet{
92*4882a593Smuzhiyun 	unsigned char i2c_status;
93*4882a593Smuzhiyun 	unsigned char dsp_status;
94*4882a593Smuzhiyun 	unsigned int reg_num;
95*4882a593Smuzhiyun 	unsigned int reg_addr;
96*4882a593Smuzhiyun 	unsigned int dsp_addr;
97*4882a593Smuzhiyun 	char *reg_data;
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun enum {
103*4882a593Smuzhiyun 	AW883XX_STREAM_CLOSE = 0,
104*4882a593Smuzhiyun 	AW883XX_STREAM_OPEN,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun enum aw883xx_init {
108*4882a593Smuzhiyun 	AW883XX_INIT_ST = 0,
109*4882a593Smuzhiyun 	AW883XX_INIT_OK = 1,
110*4882a593Smuzhiyun 	AW883XX_INIT_NG = 2,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun enum aw_re_range {
114*4882a593Smuzhiyun 	AW_RE_MIN = 1000,
115*4882a593Smuzhiyun 	AW_RE_MAX = 40000,
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun /********************************************
120*4882a593Smuzhiyun  *
121*4882a593Smuzhiyun  * Compatible with codec and component
122*4882a593Smuzhiyun  *
123*4882a593Smuzhiyun  *******************************************/
124*4882a593Smuzhiyun #ifdef AW_KERNEL_VER_OVER_4_19_1
125*4882a593Smuzhiyun typedef struct snd_soc_component aw_snd_soc_codec_t;
126*4882a593Smuzhiyun typedef struct snd_soc_component_driver aw_snd_soc_codec_driver_t;
127*4882a593Smuzhiyun #else
128*4882a593Smuzhiyun typedef struct snd_soc_codec aw_snd_soc_codec_t;
129*4882a593Smuzhiyun typedef struct snd_soc_codec_driver aw_snd_soc_codec_driver_t;
130*4882a593Smuzhiyun #endif
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun struct aw_componet_codec_ops {
133*4882a593Smuzhiyun 	aw_snd_soc_codec_t *(*kcontrol_codec)(struct snd_kcontrol *kcontrol);
134*4882a593Smuzhiyun 	void *(*codec_get_drvdata)(aw_snd_soc_codec_t *codec);
135*4882a593Smuzhiyun 	int (*add_codec_controls)(aw_snd_soc_codec_t *codec,
136*4882a593Smuzhiyun 		const struct snd_kcontrol_new *controls, unsigned int num_controls);
137*4882a593Smuzhiyun 	void (*unregister_codec)(struct device *dev);
138*4882a593Smuzhiyun 	int (*register_codec)(struct device *dev,
139*4882a593Smuzhiyun 			const aw_snd_soc_codec_driver_t *codec_drv,
140*4882a593Smuzhiyun 			struct snd_soc_dai_driver *dai_drv,
141*4882a593Smuzhiyun 			int num_dai);
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun struct aw883xx {
145*4882a593Smuzhiyun 	struct i2c_client *i2c;
146*4882a593Smuzhiyun 	struct device *dev;
147*4882a593Smuzhiyun 	struct clk *mclk;
148*4882a593Smuzhiyun 	struct mutex lock;
149*4882a593Smuzhiyun 	struct mutex i2c_lock;
150*4882a593Smuzhiyun 	aw_snd_soc_codec_t *codec;
151*4882a593Smuzhiyun 	struct aw_componet_codec_ops *codec_ops;
152*4882a593Smuzhiyun 	struct aw_device *aw_pa;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	int sysclk;
155*4882a593Smuzhiyun 	int reset_gpio;
156*4882a593Smuzhiyun 	int irq_gpio;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	unsigned char phase_sync;	/*phase sync*/
159*4882a593Smuzhiyun 	uint32_t allow_pw;
160*4882a593Smuzhiyun 	uint8_t pstream;
161*4882a593Smuzhiyun 	unsigned char fw_retry_cnt;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	uint8_t dbg_en_prof;
164*4882a593Smuzhiyun 	uint8_t i2c_log_en;
165*4882a593Smuzhiyun 	uint8_t spin_flag;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	struct list_head list;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	struct workqueue_struct *work_queue;
170*4882a593Smuzhiyun 	struct delayed_work start_work;
171*4882a593Smuzhiyun 	struct delayed_work monitor_work;
172*4882a593Smuzhiyun 	struct delayed_work interrupt_work;
173*4882a593Smuzhiyun 	struct delayed_work acf_work;
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	uint8_t reg_addr;
176*4882a593Smuzhiyun 	uint16_t dsp_addr;
177*4882a593Smuzhiyun 	uint16_t chip_id;
178*4882a593Smuzhiyun 	struct aw883xx_i2c_packet i2c_packet;
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun int aw883xx_init(struct aw883xx *aw883xx);
182*4882a593Smuzhiyun int aw883xx_i2c_writes(struct aw883xx *aw883xx,
183*4882a593Smuzhiyun 		uint8_t reg_addr, uint8_t *buf, uint16_t len);
184*4882a593Smuzhiyun int aw883xx_i2c_write(struct aw883xx *aw883xx,
185*4882a593Smuzhiyun 		uint8_t reg_addr, uint16_t reg_data);
186*4882a593Smuzhiyun int aw883xx_reg_write(struct aw883xx *aw883xx,
187*4882a593Smuzhiyun 		uint8_t reg_addr, uint16_t reg_data);
188*4882a593Smuzhiyun int aw883xx_i2c_read(struct aw883xx *aw883xx,
189*4882a593Smuzhiyun 			uint8_t reg_addr, uint16_t *reg_data);
190*4882a593Smuzhiyun int aw883xx_reg_read(struct aw883xx *aw883xx,
191*4882a593Smuzhiyun 		uint8_t reg_addr, uint16_t *reg_data);
192*4882a593Smuzhiyun int aw883xx_reg_write_bits(struct aw883xx *aw883xx,
193*4882a593Smuzhiyun 		uint8_t reg_addr, uint16_t mask, uint16_t reg_data);
194*4882a593Smuzhiyun int aw883xx_dsp_write(struct aw883xx *aw883xx,
195*4882a593Smuzhiyun 		uint16_t dsp_addr, uint32_t dsp_data, uint8_t data_type);
196*4882a593Smuzhiyun int aw883xx_dsp_read(struct aw883xx *aw883xx,
197*4882a593Smuzhiyun 		uint16_t dsp_addr, uint32_t *dsp_data, uint8_t data_type);
198*4882a593Smuzhiyun int aw883xx_get_dev_num(void);
199*4882a593Smuzhiyun int aw883xx_get_version(char *buf, int size);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun #endif
202