1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __AW_MONITOR_H__ 4*4882a593Smuzhiyun #define __AW_MONITOR_H__ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define AW_WAIT_DSP_OPEN_TIME (3000) 7*4882a593Smuzhiyun #define AW_VBAT_CAPACITY_MIN (0) 8*4882a593Smuzhiyun #define AW_VBAT_CAPACITY_MAX (100) 9*4882a593Smuzhiyun #define AW_VMAX_INIT_VAL (0xFFFFFFFF) 10*4882a593Smuzhiyun #define AW_VBAT_MAX (100) 11*4882a593Smuzhiyun #define AW_VMAX_MAX (0) 12*4882a593Smuzhiyun #define AW_DEFAULT_MONITOR_TIME (3000) 13*4882a593Smuzhiyun #define AW_WAIT_TIME (3000) 14*4882a593Smuzhiyun #define REG_STATUS_CHECK_MAX (10) 15*4882a593Smuzhiyun #define AW_ESD_CHECK_DELAY (1) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define AW_ESD_ENABLE (true) 18*4882a593Smuzhiyun #define AW_ESD_DISABLE (false) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum aw_monitor_init { 21*4882a593Smuzhiyun AW_MONITOR_CFG_WAIT = 0, 22*4882a593Smuzhiyun AW_MONITOR_CFG_OK = 1, 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum aw_monitor_hdr_info { 26*4882a593Smuzhiyun AW_MONITOR_HDR_DATA_SIZE = 0x00000004, 27*4882a593Smuzhiyun AW_MONITOR_HDR_DATA_BYTE_LEN = 0x00000004, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun enum aw_monitor_data_ver { 31*4882a593Smuzhiyun AW_MONITOR_DATA_VER = 0x00000001, 32*4882a593Smuzhiyun AW_MONITOR_DATA_VER_MAX, 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun enum aw_monitor_first_enter { 36*4882a593Smuzhiyun AW_FIRST_ENTRY = 0, 37*4882a593Smuzhiyun AW_NOT_FIRST_ENTRY = 1, 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct aw_bin_header { 41*4882a593Smuzhiyun uint32_t check_sum; 42*4882a593Smuzhiyun uint32_t header_ver; 43*4882a593Smuzhiyun uint32_t bin_data_type; 44*4882a593Smuzhiyun uint32_t bin_data_ver; 45*4882a593Smuzhiyun uint32_t bin_data_size; 46*4882a593Smuzhiyun uint32_t ui_ver; 47*4882a593Smuzhiyun char product[8]; 48*4882a593Smuzhiyun uint32_t addr_byte_len; 49*4882a593Smuzhiyun uint32_t data_byte_len; 50*4882a593Smuzhiyun uint32_t device_addr; 51*4882a593Smuzhiyun uint32_t reserve[4]; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct aw_monitor_header { 55*4882a593Smuzhiyun uint32_t monitor_switch; 56*4882a593Smuzhiyun uint32_t monitor_time; 57*4882a593Smuzhiyun uint32_t monitor_count; 58*4882a593Smuzhiyun uint32_t step_count; 59*4882a593Smuzhiyun uint32_t reserve[4]; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct vmax_step_config { 63*4882a593Smuzhiyun uint32_t vbat_min; 64*4882a593Smuzhiyun uint32_t vbat_max; 65*4882a593Smuzhiyun int vmax_vol; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct aw_monitor { 69*4882a593Smuzhiyun bool open_dsp_en; 70*4882a593Smuzhiyun bool esd_enable; 71*4882a593Smuzhiyun int32_t dev_index; 72*4882a593Smuzhiyun uint8_t first_entry; 73*4882a593Smuzhiyun uint8_t timer_cnt; 74*4882a593Smuzhiyun uint32_t vbat_sum; 75*4882a593Smuzhiyun uint32_t custom_capacity; 76*4882a593Smuzhiyun uint32_t pre_vmax; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun int bin_status; 79*4882a593Smuzhiyun struct aw_monitor_header monitor_hdr; 80*4882a593Smuzhiyun struct vmax_step_config *vmax_cfg; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct delayed_work with_dsp_work; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun void aw_monitor_cfg_free(struct aw_monitor *monitor); 86*4882a593Smuzhiyun int aw_monitor_bin_parse(struct device *dev, 87*4882a593Smuzhiyun char *monitor_data, uint32_t data_len); 88*4882a593Smuzhiyun void aw_monitor_stop(struct aw_monitor *monitor); 89*4882a593Smuzhiyun void aw_monitor_start(struct aw_monitor *monitor); 90*4882a593Smuzhiyun int aw_monitor_no_dsp_get_vmax(struct aw_monitor *monitor, 91*4882a593Smuzhiyun int32_t *vmax); 92*4882a593Smuzhiyun void aw_monitor_init(struct device *dev, struct aw_monitor *monitor, 93*4882a593Smuzhiyun struct device_node *dev_node); 94*4882a593Smuzhiyun void aw_monitor_exit(struct aw_monitor *monitor); 95*4882a593Smuzhiyun #endif 96