1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __AW_DSP_H__ 4*4882a593Smuzhiyun #define __AW_DSP_H__ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /*#define AW_MTK_OPEN_DSP_PLATFORM*/ 7*4882a593Smuzhiyun /*#define AW_QCOM_OPEN_DSP_PLATFORM*/ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /*Note: The pord_ID is configured according to different platforms*/ 10*4882a593Smuzhiyun #define AFE_PORT_ID_AWDSP_RX (0x4000) 11*4882a593Smuzhiyun #define AW_DSP_TRY_TIME (3) 12*4882a593Smuzhiyun #define AW_DSP_SLEEP_TIME (10) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define AW_DSP_MSG_HDR_VER (1) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define AWDSP_RX_SET_ENABLE (0x10013D11) 17*4882a593Smuzhiyun #define AWDSP_RX_PARAMS (0x10013D12) 18*4882a593Smuzhiyun #define AWDSP_RX_VMAX_0 (0X10013D17) 19*4882a593Smuzhiyun #define AWDSP_RX_VMAX_1 (0X10013D18) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun typedef struct mtk_dsp_msg_header { 22*4882a593Smuzhiyun int32_t type; 23*4882a593Smuzhiyun int32_t opcode_id; 24*4882a593Smuzhiyun int32_t version; 25*4882a593Smuzhiyun int32_t reserver[3]; 26*4882a593Smuzhiyun } mtk_dsp_hdr_t; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun enum aw_rx_module_enable { 29*4882a593Smuzhiyun AW_RX_MODULE_DISENABLE = 0, 30*4882a593Smuzhiyun AW_RX_MODULE_ENABLE, 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun enum aw_dsp_msg_type { 34*4882a593Smuzhiyun DSP_MSG_TYPE_DATA = 0, 35*4882a593Smuzhiyun DSP_MSG_TYPE_CMD = 1, 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun enum aw_dsp_channel { 39*4882a593Smuzhiyun AW_DSP_CHANNEL_0 = 0, 40*4882a593Smuzhiyun AW_DSP_CHANNEL_1, 41*4882a593Smuzhiyun AW_DSP_CHANNEL_MAX, 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun uint8_t aw_dsp_isEnable(void); 45*4882a593Smuzhiyun int aw_dsp_get_rx_module_enable(int *enable); 46*4882a593Smuzhiyun int aw_dsp_set_rx_module_enable(int enable); 47*4882a593Smuzhiyun int aw_dsp_get_vmax(uint32_t *vmax, int channel); 48*4882a593Smuzhiyun int aw_dsp_set_vmax(uint32_t vmax, int channel); 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif 51