1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * aw87xxx_dsp.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (c) 2021 AWINIC Technology CO., LTD
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author: Barry <zhaozhongbo@awinic.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
9*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the
10*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your
11*4882a593Smuzhiyun * option) any later version.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/uaccess.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/device.h>
17*4882a593Smuzhiyun #include <linux/kernel.h>
18*4882a593Smuzhiyun #include <linux/of.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/hrtimer.h>
21*4882a593Smuzhiyun #include <linux/proc_fs.h>
22*4882a593Smuzhiyun #include <linux/init.h>
23*4882a593Smuzhiyun #include "aw_log.h"
24*4882a593Smuzhiyun #include "aw_dsp.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static DEFINE_MUTEX(g_dsp_lock);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #ifdef AW_MTK_OPEN_DSP_PLATFORM
29*4882a593Smuzhiyun extern int mtk_spk_send_ipi_buf_to_dsp(void *data_buffer,
30*4882a593Smuzhiyun uint32_t data_size);
31*4882a593Smuzhiyun extern int mtk_spk_recv_ipi_buf_from_dsp(int8_t *buffer,
32*4882a593Smuzhiyun int16_t size, uint32_t *buf_len);
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun static int mtk_spk_send_ipi_buf_to_dsp(void *data_buffer,
35*4882a593Smuzhiyun uint32_t data_size)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun AW_LOGI("enter");
38*4882a593Smuzhiyun return 0;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static int mtk_spk_recv_ipi_buf_from_dsp(int8_t *buffer,
42*4882a593Smuzhiyun int16_t size, uint32_t *buf_len)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun AW_LOGI("enter");
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun #elif defined AW_QCOM_OPEN_DSP_PLATFORM
49*4882a593Smuzhiyun extern int afe_get_topology(int port_id);
50*4882a593Smuzhiyun extern int aw_send_afe_cal_apr(uint32_t param_id,
51*4882a593Smuzhiyun void *buf, int cmd_size, bool write);
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun static int afe_get_topology(int port_id)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun return -EPERM;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static int aw_send_afe_cal_apr(uint32_t param_id,
59*4882a593Smuzhiyun void *buf, int cmd_size, bool write)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun AW_LOGI("enter, no define AWINIC_ADSP_ENABLE", __func__);
62*4882a593Smuzhiyun return 0;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun */
65*4882a593Smuzhiyun #endif
66*4882a593Smuzhiyun
aw_dsp_isEnable(void)67*4882a593Smuzhiyun uint8_t aw_dsp_isEnable(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun #if (defined AW_QCOM_OPEN_DSP_PLATFORM) || (defined AW_MTK_OPEN_DSP_PLATFORM)
70*4882a593Smuzhiyun return true;
71*4882a593Smuzhiyun #else
72*4882a593Smuzhiyun return false;
73*4882a593Smuzhiyun #endif
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*****************mtk dsp communication function start**********************/
77*4882a593Smuzhiyun #ifdef AW_MTK_OPEN_DSP_PLATFORM
aw_mtk_write_data_to_dsp(int32_t param_id,void * data,int size)78*4882a593Smuzhiyun static int aw_mtk_write_data_to_dsp(int32_t param_id,
79*4882a593Smuzhiyun void *data, int size)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun int32_t *dsp_data = NULL;
82*4882a593Smuzhiyun mtk_dsp_hdr_t *hdr = NULL;
83*4882a593Smuzhiyun int ret;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun dsp_data = kzalloc(sizeof(mtk_dsp_hdr_t) + size, GFP_KERNEL);
86*4882a593Smuzhiyun if (!dsp_data) {
87*4882a593Smuzhiyun AW_LOGE("kzalloc dsp_msg error");
88*4882a593Smuzhiyun return -ENOMEM;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun hdr = (mtk_dsp_hdr_t *)dsp_data;
92*4882a593Smuzhiyun hdr->type = DSP_MSG_TYPE_DATA;
93*4882a593Smuzhiyun hdr->opcode_id = param_id;
94*4882a593Smuzhiyun hdr->version = AW_DSP_MSG_HDR_VER;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun memcpy(((char *)dsp_data) + sizeof(mtk_dsp_hdr_t),
97*4882a593Smuzhiyun data, size);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun ret = mtk_spk_send_ipi_buf_to_dsp(dsp_data,
100*4882a593Smuzhiyun sizeof(mtk_dsp_hdr_t) + size);
101*4882a593Smuzhiyun if (ret < 0) {
102*4882a593Smuzhiyun AW_LOGE("write data failed");
103*4882a593Smuzhiyun kfree(dsp_data);
104*4882a593Smuzhiyun dsp_data = NULL;
105*4882a593Smuzhiyun return ret;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun kfree(dsp_data);
109*4882a593Smuzhiyun dsp_data = NULL;
110*4882a593Smuzhiyun return 0;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
aw_mtk_read_data_from_dsp(int32_t param_id,void * data,int data_size)113*4882a593Smuzhiyun static int aw_mtk_read_data_from_dsp(int32_t param_id, void *data,
114*4882a593Smuzhiyun int data_size)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun int ret;
117*4882a593Smuzhiyun mtk_dsp_hdr_t hdr;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun mutex_lock(&g_dsp_lock);
120*4882a593Smuzhiyun hdr.type = DSP_MSG_TYPE_CMD;
121*4882a593Smuzhiyun hdr.opcode_id = param_id;
122*4882a593Smuzhiyun hdr.version = AW_DSP_MSG_HDR_VER;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun ret = mtk_spk_send_ipi_buf_to_dsp(&hdr, sizeof(mtk_dsp_hdr_t));
125*4882a593Smuzhiyun if (ret < 0)
126*4882a593Smuzhiyun goto failed;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun ret = mtk_spk_recv_ipi_buf_from_dsp(data, data_size, &data_size);
129*4882a593Smuzhiyun if (ret < 0)
130*4882a593Smuzhiyun goto failed;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun mutex_unlock(&g_dsp_lock);
133*4882a593Smuzhiyun return 0;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun failed:
136*4882a593Smuzhiyun mutex_unlock(&g_dsp_lock);
137*4882a593Smuzhiyun return ret;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #endif
141*4882a593Smuzhiyun /********************mtk dsp communication function end***********************/
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /******************qcom dsp communication function start**********************/
144*4882a593Smuzhiyun #ifdef AW_QCOM_OPEN_DSP_PLATFORM
aw_check_dsp_ready(void)145*4882a593Smuzhiyun static int aw_check_dsp_ready(void)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun int ret;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun ret = afe_get_topology(AFE_PORT_ID_AWDSP_RX);
150*4882a593Smuzhiyun AW_LOGD("topo_id 0x%x", ret);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun if (ret <= 0)
153*4882a593Smuzhiyun return 0;
154*4882a593Smuzhiyun else
155*4882a593Smuzhiyun return 1;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
aw_qcom_write_data_to_dsp(int32_t param_id,void * data,int data_size)158*4882a593Smuzhiyun static int aw_qcom_write_data_to_dsp(int32_t param_id,
159*4882a593Smuzhiyun void *data, int data_size)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun int ret = 0;
162*4882a593Smuzhiyun int try = 0;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun AW_LOGI("enter");
165*4882a593Smuzhiyun mutex_lock(&g_dsp_lock);
166*4882a593Smuzhiyun while (try < AW_DSP_TRY_TIME) {
167*4882a593Smuzhiyun if (aw_check_dsp_ready()) {
168*4882a593Smuzhiyun ret = aw_send_afe_cal_apr(param_id, data,
169*4882a593Smuzhiyun data_size, true);
170*4882a593Smuzhiyun mutex_unlock(&g_dsp_lock);
171*4882a593Smuzhiyun return ret;
172*4882a593Smuzhiyun } else {
173*4882a593Smuzhiyun try++;
174*4882a593Smuzhiyun msleep(AW_DSP_SLEEP_TIME);
175*4882a593Smuzhiyun AW_LOGD("afe not ready try again");
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun mutex_unlock(&g_dsp_lock);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun return -EINVAL;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
aw_qcom_read_data_from_dsp(int32_t param_id,void * data,int data_size)183*4882a593Smuzhiyun static int aw_qcom_read_data_from_dsp(int32_t param_id,
184*4882a593Smuzhiyun void *data, int data_size)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun int ret = 0;
187*4882a593Smuzhiyun int try = 0;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun AW_LOGI("enter");
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun mutex_lock(&g_dsp_lock);
192*4882a593Smuzhiyun while (try < AW_DSP_TRY_TIME) {
193*4882a593Smuzhiyun if (aw_check_dsp_ready()) {
194*4882a593Smuzhiyun ret = aw_send_afe_cal_apr(param_id, data,
195*4882a593Smuzhiyun data_size, false);
196*4882a593Smuzhiyun mutex_unlock(&g_dsp_lock);
197*4882a593Smuzhiyun return ret;
198*4882a593Smuzhiyun } else {
199*4882a593Smuzhiyun try++;
200*4882a593Smuzhiyun msleep(AW_DSP_SLEEP_TIME);
201*4882a593Smuzhiyun AW_LOGD("afe not ready try again");
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun mutex_unlock(&g_dsp_lock);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun return -EINVAL;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun #endif
210*4882a593Smuzhiyun /*****************qcom dsp communication function end*********************/
211*4882a593Smuzhiyun
aw_dsp_get_rx_module_enable(int * enable)212*4882a593Smuzhiyun int aw_dsp_get_rx_module_enable(int *enable)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun int ret = 0;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun if (!enable) {
217*4882a593Smuzhiyun AW_LOGE("enable is NULL");
218*4882a593Smuzhiyun return -EINVAL;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun #ifdef AW_QCOM_OPEN_DSP_PLATFORM
222*4882a593Smuzhiyun ret = aw_qcom_read_data_from_dsp(AWDSP_RX_SET_ENABLE,
223*4882a593Smuzhiyun (void *)enable, sizeof(uint32_t));
224*4882a593Smuzhiyun #elif defined AW_MTK_OPEN_DSP_PLATFORM
225*4882a593Smuzhiyun ret = aw_mtk_read_data_from_dsp(AWDSP_RX_SET_ENABLE,
226*4882a593Smuzhiyun (void *)enable, sizeof(uint32_t));
227*4882a593Smuzhiyun #endif
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun return ret;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
aw_dsp_set_rx_module_enable(int enable)232*4882a593Smuzhiyun int aw_dsp_set_rx_module_enable(int enable)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun int ret = 0;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun switch (enable) {
237*4882a593Smuzhiyun case AW_RX_MODULE_DISENABLE:
238*4882a593Smuzhiyun AW_LOGD("set enable=%d", enable);
239*4882a593Smuzhiyun break;
240*4882a593Smuzhiyun case AW_RX_MODULE_ENABLE:
241*4882a593Smuzhiyun AW_LOGD("set enable=%d", enable);
242*4882a593Smuzhiyun break;
243*4882a593Smuzhiyun default:
244*4882a593Smuzhiyun AW_LOGE("unsupport enable=%d", enable);
245*4882a593Smuzhiyun return -EINVAL;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun #ifdef AW_QCOM_OPEN_DSP_PLATFORM
249*4882a593Smuzhiyun ret = aw_qcom_write_data_to_dsp(AWDSP_RX_SET_ENABLE,
250*4882a593Smuzhiyun &enable, sizeof(uint32_t));
251*4882a593Smuzhiyun #elif defined AW_MTK_OPEN_DSP_PLATFORM
252*4882a593Smuzhiyun ret = aw_mtk_write_data_to_dsp(AWDSP_RX_SET_ENABLE,
253*4882a593Smuzhiyun &enable, sizeof(uint32_t));
254*4882a593Smuzhiyun #endif
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun return ret;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun
aw_dsp_get_vmax(uint32_t * vmax,int dev_index)260*4882a593Smuzhiyun int aw_dsp_get_vmax(uint32_t *vmax, int dev_index)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun int ret = 0;
263*4882a593Smuzhiyun int32_t param_id = 0;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun switch (dev_index % AW_DSP_CHANNEL_MAX) {
266*4882a593Smuzhiyun case AW_DSP_CHANNEL_0:
267*4882a593Smuzhiyun param_id = AWDSP_RX_VMAX_0;
268*4882a593Smuzhiyun break;
269*4882a593Smuzhiyun case AW_DSP_CHANNEL_1:
270*4882a593Smuzhiyun param_id = AWDSP_RX_VMAX_1;
271*4882a593Smuzhiyun break;
272*4882a593Smuzhiyun default:
273*4882a593Smuzhiyun AW_LOGE("algo only support double PA channel:%d unsupport",
274*4882a593Smuzhiyun dev_index);
275*4882a593Smuzhiyun return -EINVAL;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun #ifdef AW_QCOM_OPEN_DSP_PLATFORM
278*4882a593Smuzhiyun ret = aw_qcom_read_data_from_dsp(param_id,
279*4882a593Smuzhiyun (void *)vmax, sizeof(uint32_t));
280*4882a593Smuzhiyun #elif defined AW_MTK_OPEN_DSP_PLATFORM
281*4882a593Smuzhiyun ret = aw_mtk_read_data_from_dsp(param_id,
282*4882a593Smuzhiyun (void *)vmax, sizeof(uint32_t));
283*4882a593Smuzhiyun #endif
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun return ret;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
aw_dsp_set_vmax(uint32_t vmax,int dev_index)288*4882a593Smuzhiyun int aw_dsp_set_vmax(uint32_t vmax, int dev_index)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun int ret = 0;
291*4882a593Smuzhiyun int32_t param_id = 0;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun switch (dev_index % AW_DSP_CHANNEL_MAX) {
294*4882a593Smuzhiyun case AW_DSP_CHANNEL_0:
295*4882a593Smuzhiyun param_id = AWDSP_RX_VMAX_0;
296*4882a593Smuzhiyun break;
297*4882a593Smuzhiyun case AW_DSP_CHANNEL_1:
298*4882a593Smuzhiyun param_id = AWDSP_RX_VMAX_1;
299*4882a593Smuzhiyun break;
300*4882a593Smuzhiyun default:
301*4882a593Smuzhiyun AW_LOGE("algo only support double PA channel:%d unsupport",
302*4882a593Smuzhiyun dev_index);
303*4882a593Smuzhiyun return -EINVAL;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun #ifdef AW_QCOM_OPEN_DSP_PLATFORM
306*4882a593Smuzhiyun ret = aw_qcom_write_data_to_dsp(param_id, &vmax, sizeof(uint32_t));
307*4882a593Smuzhiyun #elif defined AW_MTK_OPEN_DSP_PLATFORM
308*4882a593Smuzhiyun ret = aw_mtk_write_data_to_dsp(param_id, &vmax, sizeof(uint32_t));
309*4882a593Smuzhiyun #endif
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun return ret;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
314