xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/alc5632.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * alc5632.h  --  ALC5632 ALSA SoC Audio Codec
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Authors:  Leon Romanovsky <leon@leon.nu>
8*4882a593Smuzhiyun *           Andrey Danin <danindrey@mail.ru>
9*4882a593Smuzhiyun *           Ilya Petrov <ilya.muromec@gmail.com>
10*4882a593Smuzhiyun *           Marc Dietrich <marvin24@gmx.de>
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Based on alc5623.h by Arnaud Patard
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #ifndef _ALC5632_H
16*4882a593Smuzhiyun #define _ALC5632_H
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define ALC5632_RESET				0x00
19*4882a593Smuzhiyun /* speaker output vol		   2    2           */
20*4882a593Smuzhiyun /* line output vol                      4    2      */
21*4882a593Smuzhiyun /* HP output vol		   4    0    4      */
22*4882a593Smuzhiyun #define ALC5632_SPK_OUT_VOL			0x02 /* spe out vol */
23*4882a593Smuzhiyun #define ALC5632_SPK_OUT_VOL_STEP		1.5
24*4882a593Smuzhiyun #define ALC5632_HP_OUT_VOL			0x04 /* hp out vol */
25*4882a593Smuzhiyun #define ALC5632_AUX_OUT_VOL			0x06 /* aux out vol */
26*4882a593Smuzhiyun #define ALC5632_PHONE_IN_VOL			0x08 /* phone in vol */
27*4882a593Smuzhiyun #define ALC5632_LINE_IN_VOL			0x0A /* line in vol */
28*4882a593Smuzhiyun #define ALC5632_STEREO_DAC_IN_VOL		0x0C /* stereo dac in vol */
29*4882a593Smuzhiyun #define ALC5632_MIC_VOL				0x0E /* mic in vol */
30*4882a593Smuzhiyun /* stero dac/mic routing */
31*4882a593Smuzhiyun #define ALC5632_MIC_ROUTING_CTRL		0x10
32*4882a593Smuzhiyun #define ALC5632_MIC_ROUTE_MONOMIX		(1 << 0)
33*4882a593Smuzhiyun #define ALC5632_MIC_ROUTE_SPK			(1 << 1)
34*4882a593Smuzhiyun #define ALC5632_MIC_ROUTE_HP			(1 << 2)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define ALC5632_ADC_REC_GAIN			0x12 /* rec gain */
37*4882a593Smuzhiyun #define ALC5632_ADC_REC_GAIN_RANGE		0x1F1F
38*4882a593Smuzhiyun #define ALC5632_ADC_REC_GAIN_BASE		(-16.5)
39*4882a593Smuzhiyun #define ALC5632_ADC_REC_GAIN_STEP		1.5
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define ALC5632_ADC_REC_MIXER			0x14 /* mixer control */
42*4882a593Smuzhiyun #define ALC5632_ADC_REC_MIC1			(1 << 6)
43*4882a593Smuzhiyun #define ALC5632_ADC_REC_MIC2			(1 << 5)
44*4882a593Smuzhiyun #define ALC5632_ADC_REC_LINE_IN			(1 << 4)
45*4882a593Smuzhiyun #define ALC5632_ADC_REC_AUX			(1 << 3)
46*4882a593Smuzhiyun #define ALC5632_ADC_REC_HP			(1 << 2)
47*4882a593Smuzhiyun #define ALC5632_ADC_REC_SPK			(1 << 1)
48*4882a593Smuzhiyun #define ALC5632_ADC_REC_MONOMIX			(1 << 0)
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define ALC5632_VOICE_DAC_VOL			0x18 /* voice dac vol */
51*4882a593Smuzhiyun #define ALC5632_I2S_OUT_CTL				0x1A /* undocumented reg. found in path scheme */
52*4882a593Smuzhiyun /* ALC5632_OUTPUT_MIXER_CTRL :			*/
53*4882a593Smuzhiyun /* same remark as for reg 2 line vs speaker	*/
54*4882a593Smuzhiyun #define ALC5632_OUTPUT_MIXER_CTRL		0x1C /* out mix ctrl */
55*4882a593Smuzhiyun #define ALC5632_OUTPUT_MIXER_RP			(1 << 14)
56*4882a593Smuzhiyun #define ALC5632_OUTPUT_MIXER_WEEK		(1 << 12)
57*4882a593Smuzhiyun #define ALC5632_OUTPUT_MIXER_HP			(1 << 10)
58*4882a593Smuzhiyun #define ALC5632_OUTPUT_MIXER_AUX_SPK		(2 <<  6)
59*4882a593Smuzhiyun #define ALC5632_OUTPUT_MIXER_AUX_HP_LR          (1 << 6)
60*4882a593Smuzhiyun #define ALC5632_OUTPUT_MIXER_HP_R               (1 << 8)
61*4882a593Smuzhiyun #define ALC5632_OUTPUT_MIXER_HP_L               (1 << 9)
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define ALC5632_MIC_CTRL			0x22 /* mic phone ctrl */
64*4882a593Smuzhiyun #define ALC5632_MIC_BOOST_BYPASS		0
65*4882a593Smuzhiyun #define ALC5632_MIC_BOOST_20DB			1
66*4882a593Smuzhiyun #define ALC5632_MIC_BOOST_30DB			2
67*4882a593Smuzhiyun #define ALC5632_MIC_BOOST_40DB			3
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define ALC5632_DIGI_BOOST_CTRL			0x24 /* digi mic / bost ctl */
70*4882a593Smuzhiyun #define ALC5632_MIC_BOOST_RANGE			7
71*4882a593Smuzhiyun #define ALC5632_MIC_BOOST_STEP			6
72*4882a593Smuzhiyun #define ALC5632_PWR_DOWN_CTRL_STATUS		0x26
73*4882a593Smuzhiyun #define ALC5632_PWR_DOWN_CTRL_STATUS_MASK	0xEF00
74*4882a593Smuzhiyun #define ALC5632_PWR_VREF_PR3			(1 << 11)
75*4882a593Smuzhiyun #define ALC5632_PWR_VREF_PR2			(1 << 10)
76*4882a593Smuzhiyun #define ALC5632_PWR_VREF_STATUS			(1 << 3)
77*4882a593Smuzhiyun #define ALC5632_PWR_AMIX_STATUS			(1 << 2)
78*4882a593Smuzhiyun #define ALC5632_PWR_DAC_STATUS			(1 << 1)
79*4882a593Smuzhiyun #define ALC5632_PWR_ADC_STATUS			(1 << 0)
80*4882a593Smuzhiyun /* stereo/voice DAC / stereo adc func ctrl */
81*4882a593Smuzhiyun #define ALC5632_DAC_FUNC_SELECT			0x2E
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /* Main serial data port ctrl (i2s) */
84*4882a593Smuzhiyun #define ALC5632_DAI_CONTROL			0x34
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define ALC5632_DAI_SDP_MASTER_MODE		(0 << 15)
87*4882a593Smuzhiyun #define ALC5632_DAI_SDP_SLAVE_MODE		(1 << 15)
88*4882a593Smuzhiyun #define ALC5632_DAI_SADLRCK_MODE		(1 << 14)
89*4882a593Smuzhiyun /* 0:voice, 1:main */
90*4882a593Smuzhiyun #define ALC5632_DAI_MAIN_I2S_SYSCLK_SEL		(1 <<  8)
91*4882a593Smuzhiyun #define ALC5632_DAI_MAIN_I2S_BCLK_POL_CTRL	(1 <<  7)
92*4882a593Smuzhiyun /* 0:normal, 1:invert */
93*4882a593Smuzhiyun #define ALC5632_DAI_MAIN_I2S_LRCK_INV		(1 <<  6)
94*4882a593Smuzhiyun #define ALC5632_DAI_I2S_DL_MASK			(3 <<  2)
95*4882a593Smuzhiyun #define ALC5632_DAI_I2S_DL_8			(3 <<  2)
96*4882a593Smuzhiyun #define	ALC5632_DAI_I2S_DL_24			(2 <<  2)
97*4882a593Smuzhiyun #define	ALC5632_DAI_I2S_DL_20			(1 <<  2)
98*4882a593Smuzhiyun #define ALC5632_DAI_I2S_DL_16			(0 <<  2)
99*4882a593Smuzhiyun #define ALC5632_DAI_I2S_DF_MASK			(3 <<  0)
100*4882a593Smuzhiyun #define ALC5632_DAI_I2S_DF_PCM_B		(3 <<  0)
101*4882a593Smuzhiyun #define	ALC5632_DAI_I2S_DF_PCM_A		(2 <<  0)
102*4882a593Smuzhiyun #define ALC5632_DAI_I2S_DF_LEFT			(1 <<  0)
103*4882a593Smuzhiyun #define ALC5632_DAI_I2S_DF_I2S			(0 <<  0)
104*4882a593Smuzhiyun /* extend serial data port control (VoDAC_i2c/pcm) */
105*4882a593Smuzhiyun #define ALC5632_DAI_CONTROL2			0x36
106*4882a593Smuzhiyun /* 0:gpio func, 1:voice pcm */
107*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_PCM_ENABLE		(1 << 15)
108*4882a593Smuzhiyun /* 0:master, 1:slave */
109*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_MODE_SEL		(1 << 14)
110*4882a593Smuzhiyun /* 0:disable, 1:enable */
111*4882a593Smuzhiyun #define ALC5632_DAI_HPF_CLK_CTRL		(1 << 13)
112*4882a593Smuzhiyun /* 0:main, 1:voice */
113*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_I2S_SYSCLK_SEL	(1 <<  8)
114*4882a593Smuzhiyun /* 0:normal, 1:invert */
115*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_VBCLK_SYSCLK_SEL	(1 <<  7)
116*4882a593Smuzhiyun /* 0:normal, 1:invert */
117*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_I2S_LR_INV		(1 <<  6)
118*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_DL_MASK		(3 <<  2)
119*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_DL_16			(0 <<  2)
120*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_DL_20			(1 <<  2)
121*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_DL_24			(2 <<  2)
122*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_DL_8			(3 <<  2)
123*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_DF_MASK		(3 <<  0)
124*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_DF_I2S		(0 <<  0)
125*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_DF_LEFT		(1 <<  0)
126*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_DF_PCM_A		(2 <<  0)
127*4882a593Smuzhiyun #define ALC5632_DAI_VOICE_DF_PCM_B		(3 <<  0)
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #define	ALC5632_PWR_MANAG_ADD1			0x3A
130*4882a593Smuzhiyun #define	ALC5632_PWR_MANAG_ADD1_MASK		0xEFFF
131*4882a593Smuzhiyun #define ALC5632_PWR_ADD1_DAC_L_EN		(1 << 15)
132*4882a593Smuzhiyun #define ALC5632_PWR_ADD1_DAC_R_EN		(1 << 14)
133*4882a593Smuzhiyun #define ALC5632_PWR_ADD1_ZERO_CROSS		(1 << 13)
134*4882a593Smuzhiyun #define ALC5632_PWR_ADD1_MAIN_I2S_EN		(1 << 11)
135*4882a593Smuzhiyun #define ALC5632_PWR_ADD1_SPK_AMP_EN		(1 << 10)
136*4882a593Smuzhiyun #define ALC5632_PWR_ADD1_HP_OUT_AMP		(1 <<  9)
137*4882a593Smuzhiyun #define ALC5632_PWR_ADD1_HP_OUT_ENH_AMP		(1 <<  8)
138*4882a593Smuzhiyun #define ALC5632_PWR_ADD1_VOICE_DAC_MIX		(1 <<  7)
139*4882a593Smuzhiyun #define	ALC5632_PWR_ADD1_SOFTGEN_EN		(1 <<  6)
140*4882a593Smuzhiyun #define	ALC5632_PWR_ADD1_MIC1_SHORT_CURR	(1 <<  5)
141*4882a593Smuzhiyun #define	ALC5632_PWR_ADD1_MIC2_SHORT_CURR	(1 <<  4)
142*4882a593Smuzhiyun #define	ALC5632_PWR_ADD1_MIC1_EN		(1 <<  3)
143*4882a593Smuzhiyun #define	ALC5632_PWR_ADD1_MIC2_EN		(1 <<  2)
144*4882a593Smuzhiyun #define ALC5632_PWR_ADD1_MAIN_BIAS		(1 <<  1)
145*4882a593Smuzhiyun #define ALC5632_PWR_ADD1_DAC_REF		(1 <<  0)
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun #define ALC5632_PWR_MANAG_ADD2			0x3C
148*4882a593Smuzhiyun #define ALC5632_PWR_MANAG_ADD2_MASK		0x7FFF
149*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_PLL1			(1 << 15)
150*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_PLL2			(1 << 14)
151*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_VREF			(1 << 13)
152*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_OVT_DET		(1 << 12)
153*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_VOICE_DAC		(1 << 10)
154*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_L_DAC_CLK		(1 <<  9)
155*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_R_DAC_CLK		(1 <<  8)
156*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_L_ADC_CLK_GAIN		(1 <<  7)
157*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_R_ADC_CLK_GAIN		(1 <<  6)
158*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_L_HP_MIXER		(1 <<  5)
159*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_R_HP_MIXER		(1 <<  4)
160*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_SPK_MIXER		(1 <<  3)
161*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_MONO_MIXER		(1 <<  2)
162*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_L_ADC_REC_MIXER	(1 <<  1)
163*4882a593Smuzhiyun #define ALC5632_PWR_ADD2_R_ADC_REC_MIXER	(1 <<  0)
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun #define ALC5632_PWR_MANAG_ADD3			0x3E
166*4882a593Smuzhiyun #define ALC5632_PWR_MANAG_ADD3_MASK		0x7CFF
167*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_AUXOUT_VOL		(1 << 14)
168*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_SPK_L_OUT		(1 << 13)
169*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_SPK_R_OUT		(1 << 12)
170*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_HP_L_OUT_VOL		(1 << 11)
171*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_HP_R_OUT_VOL		(1 << 10)
172*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_LINEIN_L_VOL		(1 <<  7)
173*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_LINEIN_R_VOL		(1 <<  6)
174*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_AUXIN_VOL		(1 <<  5)
175*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_AUXIN_MIX		(1 <<  4)
176*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_MIC1_VOL		(1 <<  3)
177*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_MIC2_VOL		(1 <<  2)
178*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_MIC1_BOOST_AD		(1 <<  1)
179*4882a593Smuzhiyun #define ALC5632_PWR_ADD3_MIC2_BOOST_AD		(1 <<  0)
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun #define ALC5632_GPCR1				0x40
182*4882a593Smuzhiyun #define ALC5632_GPCR1_CLK_SYS_SRC_SEL_PLL1	(1 << 15)
183*4882a593Smuzhiyun #define ALC5632_GPCR1_CLK_SYS_SRC_SEL_MCLK	(0 << 15)
184*4882a593Smuzhiyun #define ALC5632_GPCR1_DAC_HI_FLT_EN		(1 << 10)
185*4882a593Smuzhiyun #define ALC5632_GPCR1_SPK_AMP_CTRL		(7 <<  1)
186*4882a593Smuzhiyun #define ALC5632_GPCR1_VDD_100			(5 <<  1)
187*4882a593Smuzhiyun #define ALC5632_GPCR1_VDD_125			(4 <<  1)
188*4882a593Smuzhiyun #define ALC5632_GPCR1_VDD_150			(3 <<  1)
189*4882a593Smuzhiyun #define ALC5632_GPCR1_VDD_175			(2 <<  1)
190*4882a593Smuzhiyun #define ALC5632_GPCR1_VDD_200			(1 <<  1)
191*4882a593Smuzhiyun #define ALC5632_GPCR1_VDD_225			(0 <<  1)
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun #define	ALC5632_GPCR2				0x42
194*4882a593Smuzhiyun #define ALC5632_GPCR2_PLL1_SOUR_SEL		(3 << 12)
195*4882a593Smuzhiyun #define ALC5632_PLL_FR_MCLK			(0 << 12)
196*4882a593Smuzhiyun #define ALC5632_PLL_FR_BCLK			(2 << 12)
197*4882a593Smuzhiyun #define ALC5632_PLL_FR_VBCLK			(3 << 12)
198*4882a593Smuzhiyun #define ALC5632_GPCR2_CLK_PLL_PRE_DIV1		(0 <<  0)
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun #define ALC5632_PLL1_CTRL			0x44
201*4882a593Smuzhiyun #define ALC5632_PLL1_CTRL_N_VAL(n)		(((n) & 0x0f) << 8)
202*4882a593Smuzhiyun #define ALC5632_PLL1_M_BYPASS			(1 <<  7)
203*4882a593Smuzhiyun #define ALC5632_PLL1_CTRL_K_VAL(k)		(((k) & 0x07) << 4)
204*4882a593Smuzhiyun #define ALC5632_PLL1_CTRL_M_VAL(m)		(((m) & 0x0f) << 0)
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun #define ALC5632_PLL2_CTRL			0x46
207*4882a593Smuzhiyun #define ALC5632_PLL2_EN				(1 << 15)
208*4882a593Smuzhiyun #define ALC5632_PLL2_RATIO			(0 << 15)
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun #define ALC5632_GPIO_PIN_CONFIG			0x4C
211*4882a593Smuzhiyun #define ALC5632_GPIO_PIN_POLARITY		0x4E
212*4882a593Smuzhiyun #define ALC5632_GPIO_PIN_STICKY			0x50
213*4882a593Smuzhiyun #define ALC5632_GPIO_PIN_WAKEUP			0x52
214*4882a593Smuzhiyun #define ALC5632_GPIO_PIN_STATUS			0x54
215*4882a593Smuzhiyun #define ALC5632_GPIO_PIN_SHARING		0x56
216*4882a593Smuzhiyun #define	ALC5632_OVER_CURR_STATUS		0x58
217*4882a593Smuzhiyun #define ALC5632_SOFTVOL_CTRL			0x5A
218*4882a593Smuzhiyun #define ALC5632_GPIO_OUPUT_PIN_CTRL		0x5C
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun #define ALC5632_MISC_CTRL			0x5E
221*4882a593Smuzhiyun #define ALC5632_MISC_DISABLE_FAST_VREG		(1 << 15)
222*4882a593Smuzhiyun #define ALC5632_MISC_AVC_TRGT_SEL		(3 << 12)
223*4882a593Smuzhiyun #define ALC5632_MISC_AVC_TRGT_RIGHT		(1 << 12)
224*4882a593Smuzhiyun #define ALC5632_MISC_AVC_TRGT_LEFT		(2 << 12)
225*4882a593Smuzhiyun #define ALC5632_MISC_AVC_TRGT_BOTH		(3 << 12)
226*4882a593Smuzhiyun #define ALC5632_MISC_HP_DEPOP_MODE1_EN		(1 <<  9)
227*4882a593Smuzhiyun #define ALC5632_MISC_HP_DEPOP_MODE2_EN		(1 <<  8)
228*4882a593Smuzhiyun #define ALC5632_MISC_HP_DEPOP_MUTE_L		(1 <<  7)
229*4882a593Smuzhiyun #define ALC5632_MISC_HP_DEPOP_MUTE_R		(1 <<  6)
230*4882a593Smuzhiyun #define ALC5632_MISC_HP_DEPOP_MUTE		(1 <<  5)
231*4882a593Smuzhiyun #define ALC5632_MISC_GPIO_WAKEUP_CTRL		(1 <<  1)
232*4882a593Smuzhiyun #define ALC5632_MISC_IRQOUT_INV_CTRL		(1 <<  0)
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun #define ALC5632_DAC_CLK_CTRL1			0x60
235*4882a593Smuzhiyun #define ALC5632_DAC_CLK_CTRL2			0x62
236*4882a593Smuzhiyun #define ALC5632_DAC_CLK_CTRL2_DIV1_2		(1 << 0)
237*4882a593Smuzhiyun #define ALC5632_VOICE_DAC_PCM_CLK_CTRL1		0x64
238*4882a593Smuzhiyun #define ALC5632_PSEUDO_SPATIAL_CTRL		0x68
239*4882a593Smuzhiyun #define ALC5632_HID_CTRL_INDEX			0x6A
240*4882a593Smuzhiyun #define ALC5632_HID_CTRL_DATA			0x6C
241*4882a593Smuzhiyun #define ALC5632_EQ_CTRL				0x6E
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun /* undocumented */
244*4882a593Smuzhiyun #define ALC5632_VENDOR_ID1			0x7C
245*4882a593Smuzhiyun #define ALC5632_VENDOR_ID2			0x7E
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun #define ALC5632_MAX_REGISTER        0x7E
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun #endif
250