1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * alc5623.h -- alc562[123] ALSA Soc Audio driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2008 Realtek Microelectronics 6*4882a593Smuzhiyun * Copyright 2010 Arnaud Patard <arnaud.patard@rtp-net.org> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: flove <flove@realtek.com> 9*4882a593Smuzhiyun * Arnaud Patard <arnaud.patard@rtp-net.org> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _ALC5623_H 13*4882a593Smuzhiyun #define _ALC5623_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define ALC5623_RESET 0x00 16*4882a593Smuzhiyun /* 5621 5622 5623 */ 17*4882a593Smuzhiyun /* speaker output vol 2 2 */ 18*4882a593Smuzhiyun /* line output vol 4 2 */ 19*4882a593Smuzhiyun /* HP output vol 4 0 4 */ 20*4882a593Smuzhiyun #define ALC5623_SPK_OUT_VOL 0x02 21*4882a593Smuzhiyun #define ALC5623_HP_OUT_VOL 0x04 22*4882a593Smuzhiyun #define ALC5623_MONO_AUX_OUT_VOL 0x06 23*4882a593Smuzhiyun #define ALC5623_AUXIN_VOL 0x08 24*4882a593Smuzhiyun #define ALC5623_LINE_IN_VOL 0x0A 25*4882a593Smuzhiyun #define ALC5623_STEREO_DAC_VOL 0x0C 26*4882a593Smuzhiyun #define ALC5623_MIC_VOL 0x0E 27*4882a593Smuzhiyun #define ALC5623_MIC_ROUTING_CTRL 0x10 28*4882a593Smuzhiyun #define ALC5623_ADC_REC_GAIN 0x12 29*4882a593Smuzhiyun #define ALC5623_ADC_REC_MIXER 0x14 30*4882a593Smuzhiyun #define ALC5623_SOFT_VOL_CTRL_TIME 0x16 31*4882a593Smuzhiyun /* ALC5623_OUTPUT_MIXER_CTRL : */ 32*4882a593Smuzhiyun /* same remark as for reg 2 line vs speaker */ 33*4882a593Smuzhiyun #define ALC5623_OUTPUT_MIXER_CTRL 0x1C 34*4882a593Smuzhiyun #define ALC5623_MIC_CTRL 0x22 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define ALC5623_DAI_CONTROL 0x34 37*4882a593Smuzhiyun #define ALC5623_DAI_SDP_MASTER_MODE (0 << 15) 38*4882a593Smuzhiyun #define ALC5623_DAI_SDP_SLAVE_MODE (1 << 15) 39*4882a593Smuzhiyun #define ALC5623_DAI_I2S_PCM_MODE (1 << 14) 40*4882a593Smuzhiyun #define ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL (1 << 7) 41*4882a593Smuzhiyun #define ALC5623_DAI_ADC_DATA_L_R_SWAP (1 << 5) 42*4882a593Smuzhiyun #define ALC5623_DAI_DAC_DATA_L_R_SWAP (1 << 4) 43*4882a593Smuzhiyun #define ALC5623_DAI_I2S_DL_MASK (3 << 2) 44*4882a593Smuzhiyun #define ALC5623_DAI_I2S_DL_32 (3 << 2) 45*4882a593Smuzhiyun #define ALC5623_DAI_I2S_DL_24 (2 << 2) 46*4882a593Smuzhiyun #define ALC5623_DAI_I2S_DL_20 (1 << 2) 47*4882a593Smuzhiyun #define ALC5623_DAI_I2S_DL_16 (0 << 2) 48*4882a593Smuzhiyun #define ALC5623_DAI_I2S_DF_PCM (3 << 0) 49*4882a593Smuzhiyun #define ALC5623_DAI_I2S_DF_LEFT (2 << 0) 50*4882a593Smuzhiyun #define ALC5623_DAI_I2S_DF_RIGHT (1 << 0) 51*4882a593Smuzhiyun #define ALC5623_DAI_I2S_DF_I2S (0 << 0) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define ALC5623_STEREO_AD_DA_CLK_CTRL 0x36 54*4882a593Smuzhiyun #define ALC5623_COMPANDING_CTRL 0x38 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define ALC5623_PWR_MANAG_ADD1 0x3A 57*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_MAIN_I2S_EN (1 << 15) 58*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_ZC_DET_PD_EN (1 << 14) 59*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_MIC1_BIAS_EN (1 << 11) 60*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_SHORT_CURR_DET_EN (1 << 10) 61*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_SOFTGEN_EN (1 << 8) /* rsvd on 5622 */ 62*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_DEPOP_BUF_HP (1 << 6) /* rsvd on 5622 */ 63*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_HP_OUT_AMP (1 << 5) 64*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_HP_OUT_ENH_AMP (1 << 4) /* rsvd on 5622 */ 65*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_DEPOP_BUF_AUX (1 << 2) 66*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_AUX_OUT_AMP (1 << 1) 67*4882a593Smuzhiyun #define ALC5623_PWR_ADD1_AUX_OUT_ENH_AMP (1 << 0) /* rsvd on 5622 */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define ALC5623_PWR_MANAG_ADD2 0x3C 70*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_LINEOUT (1 << 15) /* rt5623 */ 71*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_CLASS_AB (1 << 15) /* rt5621 */ 72*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_CLASS_D (1 << 14) /* rt5621 */ 73*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_VREF (1 << 13) 74*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_PLL (1 << 12) 75*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_DAC_REF_CIR (1 << 10) 76*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_L_DAC_CLK (1 << 9) 77*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_R_DAC_CLK (1 << 8) 78*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_L_ADC_CLK_GAIN (1 << 7) 79*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_R_ADC_CLK_GAIN (1 << 6) 80*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_L_HP_MIXER (1 << 5) 81*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_R_HP_MIXER (1 << 4) 82*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_SPK_MIXER (1 << 3) 83*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_MONO_MIXER (1 << 2) 84*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_L_ADC_REC_MIXER (1 << 1) 85*4882a593Smuzhiyun #define ALC5623_PWR_ADD2_R_ADC_REC_MIXER (1 << 0) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define ALC5623_PWR_MANAG_ADD3 0x3E 88*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_MAIN_BIAS (1 << 15) 89*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_AUXOUT_L_VOL_AMP (1 << 14) 90*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_AUXOUT_R_VOL_AMP (1 << 13) 91*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_SPK_OUT (1 << 12) 92*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_HP_L_OUT_VOL (1 << 10) 93*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_HP_R_OUT_VOL (1 << 9) 94*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_LINEIN_L_VOL (1 << 7) 95*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_LINEIN_R_VOL (1 << 6) 96*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_AUXIN_L_VOL (1 << 5) 97*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_AUXIN_R_VOL (1 << 4) 98*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_MIC1_FUN_CTRL (1 << 3) 99*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_MIC2_FUN_CTRL (1 << 2) 100*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_MIC1_BOOST_AD (1 << 1) 101*4882a593Smuzhiyun #define ALC5623_PWR_ADD3_MIC2_BOOST_AD (1 << 0) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define ALC5623_ADD_CTRL_REG 0x40 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define ALC5623_GLOBAL_CLK_CTRL_REG 0x42 106*4882a593Smuzhiyun #define ALC5623_GBL_CLK_SYS_SOUR_SEL_PLL (1 << 15) 107*4882a593Smuzhiyun #define ALC5623_GBL_CLK_SYS_SOUR_SEL_MCLK (0 << 15) 108*4882a593Smuzhiyun #define ALC5623_GBL_CLK_PLL_SOUR_SEL_BITCLK (1 << 14) 109*4882a593Smuzhiyun #define ALC5623_GBL_CLK_PLL_SOUR_SEL_MCLK (0 << 14) 110*4882a593Smuzhiyun #define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV8 (3 << 1) 111*4882a593Smuzhiyun #define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV4 (2 << 1) 112*4882a593Smuzhiyun #define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV2 (1 << 1) 113*4882a593Smuzhiyun #define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV1 (0 << 1) 114*4882a593Smuzhiyun #define ALC5623_GBL_CLK_PLL_PRE_DIV2 (1 << 0) 115*4882a593Smuzhiyun #define ALC5623_GBL_CLK_PLL_PRE_DIV1 (0 << 0) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define ALC5623_PLL_CTRL 0x44 118*4882a593Smuzhiyun #define ALC5623_PLL_CTRL_N_VAL(n) (((n)&0xff) << 8) 119*4882a593Smuzhiyun #define ALC5623_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4) 120*4882a593Smuzhiyun #define ALC5623_PLL_CTRL_M_VAL(m) ((m)&0xf) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define ALC5623_GPIO_OUTPUT_PIN_CTRL 0x4A 123*4882a593Smuzhiyun #define ALC5623_GPIO_PIN_CONFIG 0x4C 124*4882a593Smuzhiyun #define ALC5623_GPIO_PIN_POLARITY 0x4E 125*4882a593Smuzhiyun #define ALC5623_GPIO_PIN_STICKY 0x50 126*4882a593Smuzhiyun #define ALC5623_GPIO_PIN_WAKEUP 0x52 127*4882a593Smuzhiyun #define ALC5623_GPIO_PIN_STATUS 0x54 128*4882a593Smuzhiyun #define ALC5623_GPIO_PIN_SHARING 0x56 129*4882a593Smuzhiyun #define ALC5623_OVER_CURR_STATUS 0x58 130*4882a593Smuzhiyun #define ALC5623_JACK_DET_CTRL 0x5A 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define ALC5623_MISC_CTRL 0x5E 133*4882a593Smuzhiyun #define ALC5623_MISC_DISABLE_FAST_VREG (1 << 15) 134*4882a593Smuzhiyun #define ALC5623_MISC_SPK_CLASS_AB_OC_PD (1 << 13) /* 5621 */ 135*4882a593Smuzhiyun #define ALC5623_MISC_SPK_CLASS_AB_OC_DET (1 << 12) /* 5621 */ 136*4882a593Smuzhiyun #define ALC5623_MISC_HP_DEPOP_MODE3_EN (1 << 10) 137*4882a593Smuzhiyun #define ALC5623_MISC_HP_DEPOP_MODE2_EN (1 << 9) 138*4882a593Smuzhiyun #define ALC5623_MISC_HP_DEPOP_MODE1_EN (1 << 8) 139*4882a593Smuzhiyun #define ALC5623_MISC_AUXOUT_DEPOP_MODE3_EN (1 << 6) 140*4882a593Smuzhiyun #define ALC5623_MISC_AUXOUT_DEPOP_MODE2_EN (1 << 5) 141*4882a593Smuzhiyun #define ALC5623_MISC_AUXOUT_DEPOP_MODE1_EN (1 << 4) 142*4882a593Smuzhiyun #define ALC5623_MISC_M_DAC_L_INPUT (1 << 3) 143*4882a593Smuzhiyun #define ALC5623_MISC_M_DAC_R_INPUT (1 << 2) 144*4882a593Smuzhiyun #define ALC5623_MISC_IRQOUT_INV_CTRL (1 << 0) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define ALC5623_PSEDUEO_SPATIAL_CTRL 0x60 147*4882a593Smuzhiyun #define ALC5623_EQ_CTRL 0x62 148*4882a593Smuzhiyun #define ALC5623_EQ_MODE_ENABLE 0x66 149*4882a593Smuzhiyun #define ALC5623_AVC_CTRL 0x68 150*4882a593Smuzhiyun #define ALC5623_HID_CTRL_INDEX 0x6A 151*4882a593Smuzhiyun #define ALC5623_HID_CTRL_DATA 0x6C 152*4882a593Smuzhiyun #define ALC5623_VENDOR_ID1 0x7C 153*4882a593Smuzhiyun #define ALC5623_VENDOR_ID2 0x7E 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #define ALC5623_PLL_FR_MCLK 0 156*4882a593Smuzhiyun #define ALC5623_PLL_FR_BCK 1 157*4882a593Smuzhiyun #endif 158