1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Audio driver header for AK5558 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Asahi Kasei Microdevices Corporation 6*4882a593Smuzhiyun * Copyright 2018 NXP 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _AK5558_H 10*4882a593Smuzhiyun #define _AK5558_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define AK5558_00_POWER_MANAGEMENT1 0x00 13*4882a593Smuzhiyun #define AK5558_01_POWER_MANAGEMENT2 0x01 14*4882a593Smuzhiyun #define AK5558_02_CONTROL1 0x02 15*4882a593Smuzhiyun #define AK5558_03_CONTROL2 0x03 16*4882a593Smuzhiyun #define AK5558_04_CONTROL3 0x04 17*4882a593Smuzhiyun #define AK5558_05_DSD 0x05 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* AK5558_02_CONTROL1 fields */ 20*4882a593Smuzhiyun #define AK5558_DIF GENMASK(1, 1) 21*4882a593Smuzhiyun #define AK5558_DIF_MSB_MODE (0 << 1) 22*4882a593Smuzhiyun #define AK5558_DIF_I2S_MODE (1 << 1) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define AK5558_BITS GENMASK(2, 2) 25*4882a593Smuzhiyun #define AK5558_DIF_24BIT_MODE (0 << 2) 26*4882a593Smuzhiyun #define AK5558_DIF_32BIT_MODE (1 << 2) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define AK5558_CKS GENMASK(6, 3) 29*4882a593Smuzhiyun #define AK5558_CKS_128FS_192KHZ (0 << 3) 30*4882a593Smuzhiyun #define AK5558_CKS_192FS_192KHZ (1 << 3) 31*4882a593Smuzhiyun #define AK5558_CKS_256FS_48KHZ (2 << 3) 32*4882a593Smuzhiyun #define AK5558_CKS_256FS_96KHZ (3 << 3) 33*4882a593Smuzhiyun #define AK5558_CKS_384FS_96KHZ (4 << 3) 34*4882a593Smuzhiyun #define AK5558_CKS_384FS_48KHZ (5 << 3) 35*4882a593Smuzhiyun #define AK5558_CKS_512FS_48KHZ (6 << 3) 36*4882a593Smuzhiyun #define AK5558_CKS_768FS_48KHZ (7 << 3) 37*4882a593Smuzhiyun #define AK5558_CKS_64FS_384KHZ (8 << 3) 38*4882a593Smuzhiyun #define AK5558_CKS_32FS_768KHZ (9 << 3) 39*4882a593Smuzhiyun #define AK5558_CKS_96FS_384KHZ (10 << 3) 40*4882a593Smuzhiyun #define AK5558_CKS_48FS_768KHZ (11 << 3) 41*4882a593Smuzhiyun #define AK5558_CKS_64FS_768KHZ (12 << 3) 42*4882a593Smuzhiyun #define AK5558_CKS_1024FS_16KHZ (13 << 3) 43*4882a593Smuzhiyun #define AK5558_CKS_AUTO (15 << 3) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* AK5558_03_CONTROL2 fields */ 46*4882a593Smuzhiyun #define AK5558_MODE_BITS GENMASK(6, 5) 47*4882a593Smuzhiyun #define AK5558_MODE_NORMAL (0 << 5) 48*4882a593Smuzhiyun #define AK5558_MODE_TDM128 (1 << 5) 49*4882a593Smuzhiyun #define AK5558_MODE_TDM256 (2 << 5) 50*4882a593Smuzhiyun #define AK5558_MODE_TDM512 (3 << 5) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif 53