xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/ak4458.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Audio driver for AK4458
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2016 Asahi Kasei Microdevices Corporation
6*4882a593Smuzhiyun  * Copyright 2018 NXP
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #ifndef _AK4458_H
10*4882a593Smuzhiyun #define _AK4458_H
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun /* Settings */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define AK4458_00_CONTROL1			0x00
17*4882a593Smuzhiyun #define AK4458_01_CONTROL2			0x01
18*4882a593Smuzhiyun #define AK4458_02_CONTROL3			0x02
19*4882a593Smuzhiyun #define AK4458_03_LCHATT			0x03
20*4882a593Smuzhiyun #define AK4458_04_RCHATT			0x04
21*4882a593Smuzhiyun #define AK4458_05_CONTROL4			0x05
22*4882a593Smuzhiyun #define AK4458_06_DSD1				0x06
23*4882a593Smuzhiyun #define AK4458_07_CONTROL5			0x07
24*4882a593Smuzhiyun #define AK4458_08_SOUND_CONTROL			0x08
25*4882a593Smuzhiyun #define AK4458_09_DSD2				0x09
26*4882a593Smuzhiyun #define AK4458_0A_CONTROL6			0x0A
27*4882a593Smuzhiyun #define AK4458_0B_CONTROL7			0x0B
28*4882a593Smuzhiyun #define AK4458_0C_CONTROL8			0x0C
29*4882a593Smuzhiyun #define AK4458_0D_CONTROL9			0x0D
30*4882a593Smuzhiyun #define AK4458_0E_CONTROL10			0x0E
31*4882a593Smuzhiyun #define AK4458_0F_L2CHATT			0x0F
32*4882a593Smuzhiyun #define AK4458_10_R2CHATT			0x10
33*4882a593Smuzhiyun #define AK4458_11_L3CHATT			0x11
34*4882a593Smuzhiyun #define AK4458_12_R3CHATT			0x12
35*4882a593Smuzhiyun #define AK4458_13_L4CHATT			0x13
36*4882a593Smuzhiyun #define AK4458_14_R4CHATT			0x14
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Bitfield Definitions */
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /* AK4458_00_CONTROL1 (0x00) Fields
41*4882a593Smuzhiyun  * Addr Register Name  D7     D6    D5    D4    D3    D2    D1    D0
42*4882a593Smuzhiyun  * 00H  Control 1      ACKS   0     0     0     DIF2  DIF1  DIF0  RSTN
43*4882a593Smuzhiyun  */
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* Digital Filter (SD, SLOW, SSLOW) */
46*4882a593Smuzhiyun #define AK4458_SD_MASK		GENMASK(5, 5)
47*4882a593Smuzhiyun #define AK4458_SLOW_MASK	GENMASK(0, 0)
48*4882a593Smuzhiyun #define AK4458_SSLOW_MASK	GENMASK(0, 0)
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /* DIF2	1 0
51*4882a593Smuzhiyun  *  x	1 0 MSB justified  Figure 3 (default)
52*4882a593Smuzhiyun  *  x	1 1 I2S Compliment  Figure 4
53*4882a593Smuzhiyun  */
54*4882a593Smuzhiyun #define AK4458_DIF_SHIFT	1
55*4882a593Smuzhiyun #define AK4458_DIF_MASK		GENMASK(3, 1)
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define AK4458_DIF_16BIT_LSB	(0 << 1)
58*4882a593Smuzhiyun #define AK4458_DIF_24BIT_I2S	(3 << 1)
59*4882a593Smuzhiyun #define AK4458_DIF_32BIT_LSB	(5 << 1)
60*4882a593Smuzhiyun #define AK4458_DIF_32BIT_MSB	(6 << 1)
61*4882a593Smuzhiyun #define AK4458_DIF_32BIT_I2S	(7 << 1)
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /* AK4458_00_CONTROL1 (0x00) D0 bit */
64*4882a593Smuzhiyun #define AK4458_RSTN_MASK	GENMASK(0, 0)
65*4882a593Smuzhiyun #define AK4458_RSTN		(0x1 << 0)
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /* AK4458_0A_CONTROL6 Mode bits */
68*4882a593Smuzhiyun #define AK4458_MODE_SHIFT	6
69*4882a593Smuzhiyun #define AK4458_MODE_MASK	GENMASK(7, 6)
70*4882a593Smuzhiyun #define AK4458_MODE_NORMAL	(0 << AK4458_MODE_SHIFT)
71*4882a593Smuzhiyun #define AK4458_MODE_TDM128	(1 << AK4458_MODE_SHIFT)
72*4882a593Smuzhiyun #define AK4458_MODE_TDM256	(2 << AK4458_MODE_SHIFT)
73*4882a593Smuzhiyun #define AK4458_MODE_TDM512	(3 << AK4458_MODE_SHIFT)
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* DAC Digital attenuator transition time setting
76*4882a593Smuzhiyun  * Table 19
77*4882a593Smuzhiyun  * Mode	ATS1	ATS2	ATT speed
78*4882a593Smuzhiyun  * 0	0	0	4080/fs
79*4882a593Smuzhiyun  * 1	0	1	2040/fs
80*4882a593Smuzhiyun  * 2	1	0	510/fs
81*4882a593Smuzhiyun  * 3	1	1	255/fs
82*4882a593Smuzhiyun  * */
83*4882a593Smuzhiyun #define AK4458_ATS_SHIFT	6
84*4882a593Smuzhiyun #define AK4458_ATS_MASK		GENMASK(7, 6)
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define AK4458_DSDSEL_MASK		(0x1 << 0)
87*4882a593Smuzhiyun #define AK4458_DP_MASK			(0x1 << 7)
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #endif
90