1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * AK4104 ALSA SoC (ASoC) driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include <linux/spi/spi.h>
11*4882a593Smuzhiyun #include <linux/of_device.h>
12*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
13*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
14*4882a593Smuzhiyun #include <sound/asoundef.h>
15*4882a593Smuzhiyun #include <sound/core.h>
16*4882a593Smuzhiyun #include <sound/soc.h>
17*4882a593Smuzhiyun #include <sound/initval.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* AK4104 registers addresses */
20*4882a593Smuzhiyun #define AK4104_REG_CONTROL1 0x00
21*4882a593Smuzhiyun #define AK4104_REG_RESERVED 0x01
22*4882a593Smuzhiyun #define AK4104_REG_CONTROL2 0x02
23*4882a593Smuzhiyun #define AK4104_REG_TX 0x03
24*4882a593Smuzhiyun #define AK4104_REG_CHN_STATUS(x) ((x) + 0x04)
25*4882a593Smuzhiyun #define AK4104_NUM_REGS 10
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define AK4104_REG_MASK 0x1f
28*4882a593Smuzhiyun #define AK4104_READ 0xc0
29*4882a593Smuzhiyun #define AK4104_WRITE 0xe0
30*4882a593Smuzhiyun #define AK4104_RESERVED_VAL 0x5b
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Bit masks for AK4104 registers */
33*4882a593Smuzhiyun #define AK4104_CONTROL1_RSTN (1 << 0)
34*4882a593Smuzhiyun #define AK4104_CONTROL1_PW (1 << 1)
35*4882a593Smuzhiyun #define AK4104_CONTROL1_DIF0 (1 << 2)
36*4882a593Smuzhiyun #define AK4104_CONTROL1_DIF1 (1 << 3)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define AK4104_CONTROL2_SEL0 (1 << 0)
39*4882a593Smuzhiyun #define AK4104_CONTROL2_SEL1 (1 << 1)
40*4882a593Smuzhiyun #define AK4104_CONTROL2_MODE (1 << 2)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define AK4104_TX_TXE (1 << 0)
43*4882a593Smuzhiyun #define AK4104_TX_V (1 << 1)
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun struct ak4104_private {
46*4882a593Smuzhiyun struct regmap *regmap;
47*4882a593Smuzhiyun struct regulator *regulator;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct snd_soc_dapm_widget ak4104_dapm_widgets[] = {
51*4882a593Smuzhiyun SND_SOC_DAPM_PGA("TXE", AK4104_REG_TX, AK4104_TX_TXE, 0, NULL, 0),
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("TX"),
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static const struct snd_soc_dapm_route ak4104_dapm_routes[] = {
57*4882a593Smuzhiyun { "TXE", NULL, "Playback" },
58*4882a593Smuzhiyun { "TX", NULL, "TXE" },
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
ak4104_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int format)61*4882a593Smuzhiyun static int ak4104_set_dai_fmt(struct snd_soc_dai *codec_dai,
62*4882a593Smuzhiyun unsigned int format)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
65*4882a593Smuzhiyun struct ak4104_private *ak4104 = snd_soc_component_get_drvdata(component);
66*4882a593Smuzhiyun int val = 0;
67*4882a593Smuzhiyun int ret;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* set DAI format */
70*4882a593Smuzhiyun switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
71*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
72*4882a593Smuzhiyun break;
73*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
74*4882a593Smuzhiyun val |= AK4104_CONTROL1_DIF0;
75*4882a593Smuzhiyun break;
76*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
77*4882a593Smuzhiyun val |= AK4104_CONTROL1_DIF0 | AK4104_CONTROL1_DIF1;
78*4882a593Smuzhiyun break;
79*4882a593Smuzhiyun default:
80*4882a593Smuzhiyun dev_err(component->dev, "invalid dai format\n");
81*4882a593Smuzhiyun return -EINVAL;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* This device can only be slave */
85*4882a593Smuzhiyun if ((format & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
86*4882a593Smuzhiyun return -EINVAL;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun ret = regmap_update_bits(ak4104->regmap, AK4104_REG_CONTROL1,
89*4882a593Smuzhiyun AK4104_CONTROL1_DIF0 | AK4104_CONTROL1_DIF1,
90*4882a593Smuzhiyun val);
91*4882a593Smuzhiyun if (ret < 0)
92*4882a593Smuzhiyun return ret;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun return 0;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
ak4104_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)97*4882a593Smuzhiyun static int ak4104_hw_params(struct snd_pcm_substream *substream,
98*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
99*4882a593Smuzhiyun struct snd_soc_dai *dai)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
102*4882a593Smuzhiyun struct ak4104_private *ak4104 = snd_soc_component_get_drvdata(component);
103*4882a593Smuzhiyun int ret, val = 0;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* set the IEC958 bits: consumer mode, no copyright bit */
106*4882a593Smuzhiyun val |= IEC958_AES0_CON_NOT_COPYRIGHT;
107*4882a593Smuzhiyun regmap_write(ak4104->regmap, AK4104_REG_CHN_STATUS(0), val);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun val = 0;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun switch (params_rate(params)) {
112*4882a593Smuzhiyun case 22050:
113*4882a593Smuzhiyun val |= IEC958_AES3_CON_FS_22050;
114*4882a593Smuzhiyun break;
115*4882a593Smuzhiyun case 24000:
116*4882a593Smuzhiyun val |= IEC958_AES3_CON_FS_24000;
117*4882a593Smuzhiyun break;
118*4882a593Smuzhiyun case 32000:
119*4882a593Smuzhiyun val |= IEC958_AES3_CON_FS_32000;
120*4882a593Smuzhiyun break;
121*4882a593Smuzhiyun case 44100:
122*4882a593Smuzhiyun val |= IEC958_AES3_CON_FS_44100;
123*4882a593Smuzhiyun break;
124*4882a593Smuzhiyun case 48000:
125*4882a593Smuzhiyun val |= IEC958_AES3_CON_FS_48000;
126*4882a593Smuzhiyun break;
127*4882a593Smuzhiyun case 88200:
128*4882a593Smuzhiyun val |= IEC958_AES3_CON_FS_88200;
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun case 96000:
131*4882a593Smuzhiyun val |= IEC958_AES3_CON_FS_96000;
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun case 176400:
134*4882a593Smuzhiyun val |= IEC958_AES3_CON_FS_176400;
135*4882a593Smuzhiyun break;
136*4882a593Smuzhiyun case 192000:
137*4882a593Smuzhiyun val |= IEC958_AES3_CON_FS_192000;
138*4882a593Smuzhiyun break;
139*4882a593Smuzhiyun default:
140*4882a593Smuzhiyun dev_err(component->dev, "unsupported sampling rate\n");
141*4882a593Smuzhiyun return -EINVAL;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun ret = regmap_write(ak4104->regmap, AK4104_REG_CHN_STATUS(3), val);
145*4882a593Smuzhiyun if (ret < 0)
146*4882a593Smuzhiyun return ret;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const struct snd_soc_dai_ops ak4101_dai_ops = {
152*4882a593Smuzhiyun .hw_params = ak4104_hw_params,
153*4882a593Smuzhiyun .set_fmt = ak4104_set_dai_fmt,
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun static struct snd_soc_dai_driver ak4104_dai = {
157*4882a593Smuzhiyun .name = "ak4104-hifi",
158*4882a593Smuzhiyun .playback = {
159*4882a593Smuzhiyun .stream_name = "Playback",
160*4882a593Smuzhiyun .channels_min = 2,
161*4882a593Smuzhiyun .channels_max = 2,
162*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
163*4882a593Smuzhiyun SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
164*4882a593Smuzhiyun SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
165*4882a593Smuzhiyun SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
166*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S16_LE |
167*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_3LE |
168*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE
169*4882a593Smuzhiyun },
170*4882a593Smuzhiyun .ops = &ak4101_dai_ops,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun
ak4104_probe(struct snd_soc_component * component)173*4882a593Smuzhiyun static int ak4104_probe(struct snd_soc_component *component)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun struct ak4104_private *ak4104 = snd_soc_component_get_drvdata(component);
176*4882a593Smuzhiyun int ret;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun ret = regulator_enable(ak4104->regulator);
179*4882a593Smuzhiyun if (ret < 0) {
180*4882a593Smuzhiyun dev_err(component->dev, "Unable to enable regulator: %d\n", ret);
181*4882a593Smuzhiyun return ret;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* set power-up and non-reset bits */
185*4882a593Smuzhiyun ret = regmap_update_bits(ak4104->regmap, AK4104_REG_CONTROL1,
186*4882a593Smuzhiyun AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN,
187*4882a593Smuzhiyun AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN);
188*4882a593Smuzhiyun if (ret < 0)
189*4882a593Smuzhiyun goto exit_disable_regulator;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /* enable transmitter */
192*4882a593Smuzhiyun ret = regmap_update_bits(ak4104->regmap, AK4104_REG_TX,
193*4882a593Smuzhiyun AK4104_TX_TXE, AK4104_TX_TXE);
194*4882a593Smuzhiyun if (ret < 0)
195*4882a593Smuzhiyun goto exit_disable_regulator;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun return 0;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun exit_disable_regulator:
200*4882a593Smuzhiyun regulator_disable(ak4104->regulator);
201*4882a593Smuzhiyun return ret;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
ak4104_remove(struct snd_soc_component * component)204*4882a593Smuzhiyun static void ak4104_remove(struct snd_soc_component *component)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun struct ak4104_private *ak4104 = snd_soc_component_get_drvdata(component);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun regmap_update_bits(ak4104->regmap, AK4104_REG_CONTROL1,
209*4882a593Smuzhiyun AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN, 0);
210*4882a593Smuzhiyun regulator_disable(ak4104->regulator);
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun #ifdef CONFIG_PM
ak4104_soc_suspend(struct snd_soc_component * component)214*4882a593Smuzhiyun static int ak4104_soc_suspend(struct snd_soc_component *component)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct ak4104_private *priv = snd_soc_component_get_drvdata(component);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun regulator_disable(priv->regulator);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun return 0;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
ak4104_soc_resume(struct snd_soc_component * component)223*4882a593Smuzhiyun static int ak4104_soc_resume(struct snd_soc_component *component)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun struct ak4104_private *priv = snd_soc_component_get_drvdata(component);
226*4882a593Smuzhiyun int ret;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun ret = regulator_enable(priv->regulator);
229*4882a593Smuzhiyun if (ret < 0)
230*4882a593Smuzhiyun return ret;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun return 0;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun #else
235*4882a593Smuzhiyun #define ak4104_soc_suspend NULL
236*4882a593Smuzhiyun #define ak4104_soc_resume NULL
237*4882a593Smuzhiyun #endif /* CONFIG_PM */
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_device_ak4104 = {
240*4882a593Smuzhiyun .probe = ak4104_probe,
241*4882a593Smuzhiyun .remove = ak4104_remove,
242*4882a593Smuzhiyun .suspend = ak4104_soc_suspend,
243*4882a593Smuzhiyun .resume = ak4104_soc_resume,
244*4882a593Smuzhiyun .dapm_widgets = ak4104_dapm_widgets,
245*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(ak4104_dapm_widgets),
246*4882a593Smuzhiyun .dapm_routes = ak4104_dapm_routes,
247*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(ak4104_dapm_routes),
248*4882a593Smuzhiyun .idle_bias_on = 1,
249*4882a593Smuzhiyun .use_pmdown_time = 1,
250*4882a593Smuzhiyun .endianness = 1,
251*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
252*4882a593Smuzhiyun };
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun static const struct regmap_config ak4104_regmap = {
255*4882a593Smuzhiyun .reg_bits = 8,
256*4882a593Smuzhiyun .val_bits = 8,
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun .max_register = AK4104_NUM_REGS - 1,
259*4882a593Smuzhiyun .read_flag_mask = AK4104_READ,
260*4882a593Smuzhiyun .write_flag_mask = AK4104_WRITE,
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
263*4882a593Smuzhiyun };
264*4882a593Smuzhiyun
ak4104_spi_probe(struct spi_device * spi)265*4882a593Smuzhiyun static int ak4104_spi_probe(struct spi_device *spi)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun struct ak4104_private *ak4104;
268*4882a593Smuzhiyun struct gpio_desc *reset_gpiod;
269*4882a593Smuzhiyun unsigned int val;
270*4882a593Smuzhiyun int ret;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun spi->bits_per_word = 8;
273*4882a593Smuzhiyun spi->mode = SPI_MODE_0;
274*4882a593Smuzhiyun ret = spi_setup(spi);
275*4882a593Smuzhiyun if (ret < 0)
276*4882a593Smuzhiyun return ret;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun ak4104 = devm_kzalloc(&spi->dev, sizeof(struct ak4104_private),
279*4882a593Smuzhiyun GFP_KERNEL);
280*4882a593Smuzhiyun if (ak4104 == NULL)
281*4882a593Smuzhiyun return -ENOMEM;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun ak4104->regulator = devm_regulator_get(&spi->dev, "vdd");
284*4882a593Smuzhiyun if (IS_ERR(ak4104->regulator)) {
285*4882a593Smuzhiyun ret = PTR_ERR(ak4104->regulator);
286*4882a593Smuzhiyun dev_err(&spi->dev, "Unable to get Vdd regulator: %d\n", ret);
287*4882a593Smuzhiyun return ret;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun ak4104->regmap = devm_regmap_init_spi(spi, &ak4104_regmap);
291*4882a593Smuzhiyun if (IS_ERR(ak4104->regmap)) {
292*4882a593Smuzhiyun ret = PTR_ERR(ak4104->regmap);
293*4882a593Smuzhiyun return ret;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun reset_gpiod = devm_gpiod_get_optional(&spi->dev, "reset",
297*4882a593Smuzhiyun GPIOD_OUT_HIGH);
298*4882a593Smuzhiyun if (PTR_ERR(reset_gpiod) == -EPROBE_DEFER)
299*4882a593Smuzhiyun return -EPROBE_DEFER;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun /* read the 'reserved' register - according to the datasheet, it
302*4882a593Smuzhiyun * should contain 0x5b. Not a good way to verify the presence of
303*4882a593Smuzhiyun * the device, but there is no hardware ID register. */
304*4882a593Smuzhiyun ret = regmap_read(ak4104->regmap, AK4104_REG_RESERVED, &val);
305*4882a593Smuzhiyun if (ret != 0)
306*4882a593Smuzhiyun return ret;
307*4882a593Smuzhiyun if (val != AK4104_RESERVED_VAL)
308*4882a593Smuzhiyun return -ENODEV;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun spi_set_drvdata(spi, ak4104);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&spi->dev,
313*4882a593Smuzhiyun &soc_component_device_ak4104, &ak4104_dai, 1);
314*4882a593Smuzhiyun return ret;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun static const struct of_device_id ak4104_of_match[] = {
318*4882a593Smuzhiyun { .compatible = "asahi-kasei,ak4104", },
319*4882a593Smuzhiyun { }
320*4882a593Smuzhiyun };
321*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ak4104_of_match);
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun static const struct spi_device_id ak4104_id_table[] = {
324*4882a593Smuzhiyun { "ak4104", 0 },
325*4882a593Smuzhiyun { }
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ak4104_id_table);
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun static struct spi_driver ak4104_spi_driver = {
330*4882a593Smuzhiyun .driver = {
331*4882a593Smuzhiyun .name = "ak4104",
332*4882a593Smuzhiyun .of_match_table = ak4104_of_match,
333*4882a593Smuzhiyun },
334*4882a593Smuzhiyun .id_table = ak4104_id_table,
335*4882a593Smuzhiyun .probe = ak4104_spi_probe,
336*4882a593Smuzhiyun };
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun module_spi_driver(ak4104_spi_driver);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
341*4882a593Smuzhiyun MODULE_DESCRIPTION("Asahi Kasei AK4104 ALSA SoC driver");
342*4882a593Smuzhiyun MODULE_LICENSE("GPL");
343*4882a593Smuzhiyun
344