1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ADAU1373_H__ 3*4882a593Smuzhiyun #define __ADAU1373_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun enum adau1373_pll_src { 6*4882a593Smuzhiyun ADAU1373_PLL_SRC_MCLK1 = 0, 7*4882a593Smuzhiyun ADAU1373_PLL_SRC_BCLK1 = 1, 8*4882a593Smuzhiyun ADAU1373_PLL_SRC_BCLK2 = 2, 9*4882a593Smuzhiyun ADAU1373_PLL_SRC_BCLK3 = 3, 10*4882a593Smuzhiyun ADAU1373_PLL_SRC_LRCLK1 = 4, 11*4882a593Smuzhiyun ADAU1373_PLL_SRC_LRCLK2 = 5, 12*4882a593Smuzhiyun ADAU1373_PLL_SRC_LRCLK3 = 6, 13*4882a593Smuzhiyun ADAU1373_PLL_SRC_GPIO1 = 7, 14*4882a593Smuzhiyun ADAU1373_PLL_SRC_GPIO2 = 8, 15*4882a593Smuzhiyun ADAU1373_PLL_SRC_GPIO3 = 9, 16*4882a593Smuzhiyun ADAU1373_PLL_SRC_GPIO4 = 10, 17*4882a593Smuzhiyun ADAU1373_PLL_SRC_MCLK2 = 11, 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum adau1373_pll { 21*4882a593Smuzhiyun ADAU1373_PLL1 = 0, 22*4882a593Smuzhiyun ADAU1373_PLL2 = 1, 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum adau1373_clk_src { 26*4882a593Smuzhiyun ADAU1373_CLK_SRC_PLL1 = 0, 27*4882a593Smuzhiyun ADAU1373_CLK_SRC_PLL2 = 1, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #endif 31