1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * File: sound/soc/codec/ad73311.h 4*4882a593Smuzhiyun * Based on: 5*4882a593Smuzhiyun * Author: Cliff Cai <cliff.cai@analog.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Created: Thur Sep 25, 2008 8*4882a593Smuzhiyun * Description: definitions for AD73311 registers 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Modified: 11*4882a593Smuzhiyun * Copyright 2006 Analog Devices Inc. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Bugs: Enter bugs at http://blackfin.uclinux.org/ 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __AD73311_H__ 17*4882a593Smuzhiyun #define __AD73311_H__ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define AD_CONTROL 0x8000 20*4882a593Smuzhiyun #define AD_DATA 0x0000 21*4882a593Smuzhiyun #define AD_READ 0x4000 22*4882a593Smuzhiyun #define AD_WRITE 0x0000 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Control register A */ 25*4882a593Smuzhiyun #define CTRL_REG_A (0 << 8) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define REGA_MODE_PRO 0x00 28*4882a593Smuzhiyun #define REGA_MODE_DATA 0x01 29*4882a593Smuzhiyun #define REGA_MODE_MIXED 0x03 30*4882a593Smuzhiyun #define REGA_DLB 0x04 31*4882a593Smuzhiyun #define REGA_SLB 0x08 32*4882a593Smuzhiyun #define REGA_DEVC(x) ((x & 0x7) << 4) 33*4882a593Smuzhiyun #define REGA_RESET 0x80 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Control register B */ 36*4882a593Smuzhiyun #define CTRL_REG_B (1 << 8) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define REGB_DIRATE(x) (x & 0x3) 39*4882a593Smuzhiyun #define REGB_SCDIV(x) ((x & 0x3) << 2) 40*4882a593Smuzhiyun #define REGB_MCDIV(x) ((x & 0x7) << 4) 41*4882a593Smuzhiyun #define REGB_CEE (1 << 7) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Control register C */ 44*4882a593Smuzhiyun #define CTRL_REG_C (2 << 8) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define REGC_PUDEV (1 << 0) 47*4882a593Smuzhiyun #define REGC_PUADC (1 << 3) 48*4882a593Smuzhiyun #define REGC_PUDAC (1 << 4) 49*4882a593Smuzhiyun #define REGC_PUREF (1 << 5) 50*4882a593Smuzhiyun #define REGC_REFUSE (1 << 6) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Control register D */ 53*4882a593Smuzhiyun #define CTRL_REG_D (3 << 8) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define REGD_IGS(x) (x & 0x7) 56*4882a593Smuzhiyun #define REGD_RMOD (1 << 3) 57*4882a593Smuzhiyun #define REGD_OGS(x) ((x & 0x7) << 4) 58*4882a593Smuzhiyun #define REGD_MUTE (1 << 7) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Control register E */ 61*4882a593Smuzhiyun #define CTRL_REG_E (4 << 8) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define REGE_DA(x) (x & 0x1f) 64*4882a593Smuzhiyun #define REGE_IBYP (1 << 5) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Control register F */ 67*4882a593Smuzhiyun #define CTRL_REG_F (5 << 8) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define REGF_SEEN (1 << 5) 70*4882a593Smuzhiyun #define REGF_INV (1 << 6) 71*4882a593Smuzhiyun #define REGF_ALB (1 << 7) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif 74