1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * AD193X Audio Codec driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2010 Analog Devices Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __AD193X_H__ 9*4882a593Smuzhiyun #define __AD193X_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/regmap.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct device; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum ad193x_type { 16*4882a593Smuzhiyun AD193X, 17*4882a593Smuzhiyun AD1933, 18*4882a593Smuzhiyun AD1934, 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun extern const struct regmap_config ad193x_regmap_config; 22*4882a593Smuzhiyun int ad193x_probe(struct device *dev, struct regmap *regmap, 23*4882a593Smuzhiyun enum ad193x_type type); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define AD193X_PLL_CLK_CTRL0 0x00 26*4882a593Smuzhiyun #define AD193X_PLL_POWERDOWN 0x01 27*4882a593Smuzhiyun #define AD193X_PLL_INPUT_MASK 0x6 28*4882a593Smuzhiyun #define AD193X_PLL_INPUT_256 (0 << 1) 29*4882a593Smuzhiyun #define AD193X_PLL_INPUT_384 (1 << 1) 30*4882a593Smuzhiyun #define AD193X_PLL_INPUT_512 (2 << 1) 31*4882a593Smuzhiyun #define AD193X_PLL_INPUT_768 (3 << 1) 32*4882a593Smuzhiyun #define AD193X_PLL_CLK_CTRL1 0x01 33*4882a593Smuzhiyun #define AD193X_PLL_SRC_MASK 0x03 34*4882a593Smuzhiyun #define AD193X_PLL_DAC_SRC_PLL 0 35*4882a593Smuzhiyun #define AD193X_PLL_DAC_SRC_MCLK 1 36*4882a593Smuzhiyun #define AD193X_PLL_CLK_SRC_PLL (0 << 1) 37*4882a593Smuzhiyun #define AD193X_PLL_CLK_SRC_MCLK (1 << 1) 38*4882a593Smuzhiyun #define AD193X_DAC_CTRL0 0x02 39*4882a593Smuzhiyun #define AD193X_DAC_POWERDOWN 0x01 40*4882a593Smuzhiyun #define AD193X_DAC_SERFMT_MASK 0xC0 41*4882a593Smuzhiyun #define AD193X_DAC_SERFMT_STEREO (0 << 6) 42*4882a593Smuzhiyun #define AD193X_DAC_SERFMT_TDM (1 << 6) 43*4882a593Smuzhiyun #define AD193X_DAC_CTRL1 0x03 44*4882a593Smuzhiyun #define AD193X_DAC_CHAN_SHFT 1 45*4882a593Smuzhiyun #define AD193X_DAC_CHAN_MASK (3 << AD193X_DAC_CHAN_SHFT) 46*4882a593Smuzhiyun #define AD193X_DAC_LCR_MASTER (1 << 4) 47*4882a593Smuzhiyun #define AD193X_DAC_BCLK_MASTER (1 << 5) 48*4882a593Smuzhiyun #define AD193X_DAC_LEFT_HIGH (1 << 3) 49*4882a593Smuzhiyun #define AD193X_DAC_BCLK_INV (1 << 7) 50*4882a593Smuzhiyun #define AD193X_DAC_FMT_MASK (AD193X_DAC_LCR_MASTER | \ 51*4882a593Smuzhiyun AD193X_DAC_BCLK_MASTER | AD193X_DAC_LEFT_HIGH | AD193X_DAC_BCLK_INV) 52*4882a593Smuzhiyun #define AD193X_DAC_CTRL2 0x04 53*4882a593Smuzhiyun #define AD193X_DAC_WORD_LEN_SHFT 3 54*4882a593Smuzhiyun #define AD193X_DAC_WORD_LEN_MASK 0x18 55*4882a593Smuzhiyun #define AD193X_DAC_MASTER_MUTE 1 56*4882a593Smuzhiyun #define AD193X_DAC_CHNL_MUTE 0x05 57*4882a593Smuzhiyun #define AD193X_DACL1_MUTE 0 58*4882a593Smuzhiyun #define AD193X_DACR1_MUTE 1 59*4882a593Smuzhiyun #define AD193X_DACL2_MUTE 2 60*4882a593Smuzhiyun #define AD193X_DACR2_MUTE 3 61*4882a593Smuzhiyun #define AD193X_DACL3_MUTE 4 62*4882a593Smuzhiyun #define AD193X_DACR3_MUTE 5 63*4882a593Smuzhiyun #define AD193X_DACL4_MUTE 6 64*4882a593Smuzhiyun #define AD193X_DACR4_MUTE 7 65*4882a593Smuzhiyun #define AD193X_DAC_L1_VOL 0x06 66*4882a593Smuzhiyun #define AD193X_DAC_R1_VOL 0x07 67*4882a593Smuzhiyun #define AD193X_DAC_L2_VOL 0x08 68*4882a593Smuzhiyun #define AD193X_DAC_R2_VOL 0x09 69*4882a593Smuzhiyun #define AD193X_DAC_L3_VOL 0x0a 70*4882a593Smuzhiyun #define AD193X_DAC_R3_VOL 0x0b 71*4882a593Smuzhiyun #define AD193X_DAC_L4_VOL 0x0c 72*4882a593Smuzhiyun #define AD193X_DAC_R4_VOL 0x0d 73*4882a593Smuzhiyun #define AD193X_ADC_CTRL0 0x0e 74*4882a593Smuzhiyun #define AD193X_ADC_POWERDOWN 0x01 75*4882a593Smuzhiyun #define AD193X_ADC_HIGHPASS_FILTER 1 76*4882a593Smuzhiyun #define AD193X_ADCL1_MUTE 2 77*4882a593Smuzhiyun #define AD193X_ADCR1_MUTE 3 78*4882a593Smuzhiyun #define AD193X_ADCL2_MUTE 4 79*4882a593Smuzhiyun #define AD193X_ADCR2_MUTE 5 80*4882a593Smuzhiyun #define AD193X_ADC_CTRL1 0x0f 81*4882a593Smuzhiyun #define AD193X_ADC_SERFMT_MASK 0x60 82*4882a593Smuzhiyun #define AD193X_ADC_SERFMT_STEREO (0 << 5) 83*4882a593Smuzhiyun #define AD193X_ADC_SERFMT_TDM (1 << 5) 84*4882a593Smuzhiyun #define AD193X_ADC_SERFMT_AUX (2 << 5) 85*4882a593Smuzhiyun #define AD193X_ADC_WORD_LEN_MASK 0x3 86*4882a593Smuzhiyun #define AD193X_ADC_CTRL2 0x10 87*4882a593Smuzhiyun #define AD193X_ADC_CHAN_SHFT 4 88*4882a593Smuzhiyun #define AD193X_ADC_CHAN_MASK (3 << AD193X_ADC_CHAN_SHFT) 89*4882a593Smuzhiyun #define AD193X_ADC_LCR_MASTER (1 << 3) 90*4882a593Smuzhiyun #define AD193X_ADC_BCLK_MASTER (1 << 6) 91*4882a593Smuzhiyun #define AD193X_ADC_LEFT_HIGH (1 << 2) 92*4882a593Smuzhiyun #define AD193X_ADC_BCLK_INV (1 << 1) 93*4882a593Smuzhiyun #define AD193X_ADC_FMT_MASK (AD193X_ADC_LCR_MASTER | \ 94*4882a593Smuzhiyun AD193X_ADC_BCLK_MASTER | AD193X_ADC_LEFT_HIGH | AD193X_ADC_BCLK_INV) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define AD193X_2_CHANNELS 0 97*4882a593Smuzhiyun #define AD193X_4_CHANNELS 1 98*4882a593Smuzhiyun #define AD193X_8_CHANNELS 2 99*4882a593Smuzhiyun #define AD193X_16_CHANNELS 3 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define AD193X_NUM_REGS 17 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define AD193X_SYSCLK_PLL 0 104*4882a593Smuzhiyun #define AD193X_SYSCLK_MCLK 1 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #endif 107