1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Audio Codec driver supporting: 4*4882a593Smuzhiyun * AD1835A, AD1836, AD1837A, AD1838A, AD1839A 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright 2009-2011 Analog Devices Inc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __AD1836_H__ 10*4882a593Smuzhiyun #define __AD1836_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define AD1836_DAC_CTRL1 0 13*4882a593Smuzhiyun #define AD1836_DAC_POWERDOWN 2 14*4882a593Smuzhiyun #define AD1836_DAC_SERFMT_MASK 0xE0 15*4882a593Smuzhiyun #define AD1836_DAC_SERFMT_PCK256 (0x4 << 5) 16*4882a593Smuzhiyun #define AD1836_DAC_SERFMT_PCK128 (0x5 << 5) 17*4882a593Smuzhiyun #define AD1836_DAC_WORD_LEN_MASK 0x18 18*4882a593Smuzhiyun #define AD1836_DAC_WORD_LEN_OFFSET 3 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AD1836_DAC_CTRL2 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* These macros are one-based. So AD183X_MUTE_LEFT(1) will return the mute bit 23*4882a593Smuzhiyun * for the first ADC/DAC */ 24*4882a593Smuzhiyun #define AD1836_MUTE_LEFT(x) (((x) * 2) - 2) 25*4882a593Smuzhiyun #define AD1836_MUTE_RIGHT(x) (((x) * 2) - 1) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define AD1836_DAC_L_VOL(x) ((x) * 2) 28*4882a593Smuzhiyun #define AD1836_DAC_R_VOL(x) (1 + ((x) * 2)) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define AD1836_ADC_CTRL1 12 31*4882a593Smuzhiyun #define AD1836_ADC_POWERDOWN 7 32*4882a593Smuzhiyun #define AD1836_ADC_HIGHPASS_FILTER 8 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AD1836_ADC_CTRL2 13 35*4882a593Smuzhiyun #define AD1836_ADC_WORD_LEN_MASK 0x30 36*4882a593Smuzhiyun #define AD1836_ADC_WORD_OFFSET 4 37*4882a593Smuzhiyun #define AD1836_ADC_SERFMT_MASK (7 << 6) 38*4882a593Smuzhiyun #define AD1836_ADC_SERFMT_PCK256 (0x4 << 6) 39*4882a593Smuzhiyun #define AD1836_ADC_SERFMT_PCK128 (0x5 << 6) 40*4882a593Smuzhiyun #define AD1836_ADC_AUX (0x6 << 6) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define AD1836_ADC_CTRL3 14 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define AD1836_NUM_REGS 16 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define AD1836_WORD_LEN_24 0x0 47*4882a593Smuzhiyun #define AD1836_WORD_LEN_20 0x1 48*4882a593Smuzhiyun #define AD1836_WORD_LEN_16 0x2 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif 51