1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) ST-Ericsson SA 2012 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 6*4882a593Smuzhiyun * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>, 7*4882a593Smuzhiyun * Roger Nilsson <roger.xr.nilsson@stericsson.com>, 8*4882a593Smuzhiyun * for ST-Ericsson. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Based on the early work done by: 11*4882a593Smuzhiyun * Mikko J. Lehto <mikko.lehto@symbio.com>, 12*4882a593Smuzhiyun * Mikko Sarmanne <mikko.sarmanne@symbio.com>, 13*4882a593Smuzhiyun * for ST-Ericsson. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * License terms: 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef AB8500_CODEC_REGISTERS_H 19*4882a593Smuzhiyun #define AB8500_CODEC_REGISTERS_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define AB8500_SUPPORTED_RATE (SNDRV_PCM_RATE_48000) 22*4882a593Smuzhiyun #define AB8500_SUPPORTED_FMT (SNDRV_PCM_FMTBIT_S16_LE) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* AB8500 interface slot offset definitions */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define AB8500_AD_DATA0_OFFSET 0 27*4882a593Smuzhiyun #define AB8500_DA_DATA0_OFFSET 8 28*4882a593Smuzhiyun #define AB8500_AD_DATA1_OFFSET 16 29*4882a593Smuzhiyun #define AB8500_DA_DATA1_OFFSET 24 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* AB8500 audio bank (0x0d) register definitions */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define AB8500_POWERUP 0x00 34*4882a593Smuzhiyun #define AB8500_AUDSWRESET 0x01 35*4882a593Smuzhiyun #define AB8500_ADPATHENA 0x02 36*4882a593Smuzhiyun #define AB8500_DAPATHENA 0x03 37*4882a593Smuzhiyun #define AB8500_ANACONF1 0x04 38*4882a593Smuzhiyun #define AB8500_ANACONF2 0x05 39*4882a593Smuzhiyun #define AB8500_DIGMICCONF 0x06 40*4882a593Smuzhiyun #define AB8500_ANACONF3 0x07 41*4882a593Smuzhiyun #define AB8500_ANACONF4 0x08 42*4882a593Smuzhiyun #define AB8500_DAPATHCONF 0x09 43*4882a593Smuzhiyun #define AB8500_MUTECONF 0x0A 44*4882a593Smuzhiyun #define AB8500_SHORTCIRCONF 0x0B 45*4882a593Smuzhiyun #define AB8500_ANACONF5 0x0C 46*4882a593Smuzhiyun #define AB8500_ENVCPCONF 0x0D 47*4882a593Smuzhiyun #define AB8500_SIGENVCONF 0x0E 48*4882a593Smuzhiyun #define AB8500_PWMGENCONF1 0x0F 49*4882a593Smuzhiyun #define AB8500_PWMGENCONF2 0x10 50*4882a593Smuzhiyun #define AB8500_PWMGENCONF3 0x11 51*4882a593Smuzhiyun #define AB8500_PWMGENCONF4 0x12 52*4882a593Smuzhiyun #define AB8500_PWMGENCONF5 0x13 53*4882a593Smuzhiyun #define AB8500_ANAGAIN1 0x14 54*4882a593Smuzhiyun #define AB8500_ANAGAIN2 0x15 55*4882a593Smuzhiyun #define AB8500_ANAGAIN3 0x16 56*4882a593Smuzhiyun #define AB8500_ANAGAIN4 0x17 57*4882a593Smuzhiyun #define AB8500_DIGLINHSLGAIN 0x18 58*4882a593Smuzhiyun #define AB8500_DIGLINHSRGAIN 0x19 59*4882a593Smuzhiyun #define AB8500_ADFILTCONF 0x1A 60*4882a593Smuzhiyun #define AB8500_DIGIFCONF1 0x1B 61*4882a593Smuzhiyun #define AB8500_DIGIFCONF2 0x1C 62*4882a593Smuzhiyun #define AB8500_DIGIFCONF3 0x1D 63*4882a593Smuzhiyun #define AB8500_DIGIFCONF4 0x1E 64*4882a593Smuzhiyun #define AB8500_ADSLOTSEL1 0x1F 65*4882a593Smuzhiyun #define AB8500_ADSLOTSEL2 0x20 66*4882a593Smuzhiyun #define AB8500_ADSLOTSEL3 0x21 67*4882a593Smuzhiyun #define AB8500_ADSLOTSEL4 0x22 68*4882a593Smuzhiyun #define AB8500_ADSLOTSEL5 0x23 69*4882a593Smuzhiyun #define AB8500_ADSLOTSEL6 0x24 70*4882a593Smuzhiyun #define AB8500_ADSLOTSEL7 0x25 71*4882a593Smuzhiyun #define AB8500_ADSLOTSEL8 0x26 72*4882a593Smuzhiyun #define AB8500_ADSLOTSEL9 0x27 73*4882a593Smuzhiyun #define AB8500_ADSLOTSEL10 0x28 74*4882a593Smuzhiyun #define AB8500_ADSLOTSEL11 0x29 75*4882a593Smuzhiyun #define AB8500_ADSLOTSEL12 0x2A 76*4882a593Smuzhiyun #define AB8500_ADSLOTSEL13 0x2B 77*4882a593Smuzhiyun #define AB8500_ADSLOTSEL14 0x2C 78*4882a593Smuzhiyun #define AB8500_ADSLOTSEL15 0x2D 79*4882a593Smuzhiyun #define AB8500_ADSLOTSEL16 0x2E 80*4882a593Smuzhiyun #define AB8500_ADSLOTSEL(slot) (AB8500_ADSLOTSEL1 + (slot >> 1)) 81*4882a593Smuzhiyun #define AB8500_ADSLOTHIZCTRL1 0x2F 82*4882a593Smuzhiyun #define AB8500_ADSLOTHIZCTRL2 0x30 83*4882a593Smuzhiyun #define AB8500_ADSLOTHIZCTRL3 0x31 84*4882a593Smuzhiyun #define AB8500_ADSLOTHIZCTRL4 0x32 85*4882a593Smuzhiyun #define AB8500_DASLOTCONF1 0x33 86*4882a593Smuzhiyun #define AB8500_DASLOTCONF2 0x34 87*4882a593Smuzhiyun #define AB8500_DASLOTCONF3 0x35 88*4882a593Smuzhiyun #define AB8500_DASLOTCONF4 0x36 89*4882a593Smuzhiyun #define AB8500_DASLOTCONF5 0x37 90*4882a593Smuzhiyun #define AB8500_DASLOTCONF6 0x38 91*4882a593Smuzhiyun #define AB8500_DASLOTCONF7 0x39 92*4882a593Smuzhiyun #define AB8500_DASLOTCONF8 0x3A 93*4882a593Smuzhiyun #define AB8500_CLASSDCONF1 0x3B 94*4882a593Smuzhiyun #define AB8500_CLASSDCONF2 0x3C 95*4882a593Smuzhiyun #define AB8500_CLASSDCONF3 0x3D 96*4882a593Smuzhiyun #define AB8500_DMICFILTCONF 0x3E 97*4882a593Smuzhiyun #define AB8500_DIGMULTCONF1 0x3F 98*4882a593Smuzhiyun #define AB8500_DIGMULTCONF2 0x40 99*4882a593Smuzhiyun #define AB8500_ADDIGGAIN1 0x41 100*4882a593Smuzhiyun #define AB8500_ADDIGGAIN2 0x42 101*4882a593Smuzhiyun #define AB8500_ADDIGGAIN3 0x43 102*4882a593Smuzhiyun #define AB8500_ADDIGGAIN4 0x44 103*4882a593Smuzhiyun #define AB8500_ADDIGGAIN5 0x45 104*4882a593Smuzhiyun #define AB8500_ADDIGGAIN6 0x46 105*4882a593Smuzhiyun #define AB8500_DADIGGAIN1 0x47 106*4882a593Smuzhiyun #define AB8500_DADIGGAIN2 0x48 107*4882a593Smuzhiyun #define AB8500_DADIGGAIN3 0x49 108*4882a593Smuzhiyun #define AB8500_DADIGGAIN4 0x4A 109*4882a593Smuzhiyun #define AB8500_DADIGGAIN5 0x4B 110*4882a593Smuzhiyun #define AB8500_DADIGGAIN6 0x4C 111*4882a593Smuzhiyun #define AB8500_ADDIGLOOPGAIN1 0x4D 112*4882a593Smuzhiyun #define AB8500_ADDIGLOOPGAIN2 0x4E 113*4882a593Smuzhiyun #define AB8500_HSLEARDIGGAIN 0x4F 114*4882a593Smuzhiyun #define AB8500_HSRDIGGAIN 0x50 115*4882a593Smuzhiyun #define AB8500_SIDFIRGAIN1 0x51 116*4882a593Smuzhiyun #define AB8500_SIDFIRGAIN2 0x52 117*4882a593Smuzhiyun #define AB8500_ANCCONF1 0x53 118*4882a593Smuzhiyun #define AB8500_ANCCONF2 0x54 119*4882a593Smuzhiyun #define AB8500_ANCCONF3 0x55 120*4882a593Smuzhiyun #define AB8500_ANCCONF4 0x56 121*4882a593Smuzhiyun #define AB8500_ANCCONF5 0x57 122*4882a593Smuzhiyun #define AB8500_ANCCONF6 0x58 123*4882a593Smuzhiyun #define AB8500_ANCCONF7 0x59 124*4882a593Smuzhiyun #define AB8500_ANCCONF8 0x5A 125*4882a593Smuzhiyun #define AB8500_ANCCONF9 0x5B 126*4882a593Smuzhiyun #define AB8500_ANCCONF10 0x5C 127*4882a593Smuzhiyun #define AB8500_ANCCONF11 0x5D 128*4882a593Smuzhiyun #define AB8500_ANCCONF12 0x5E 129*4882a593Smuzhiyun #define AB8500_ANCCONF13 0x5F 130*4882a593Smuzhiyun #define AB8500_ANCCONF14 0x60 131*4882a593Smuzhiyun #define AB8500_SIDFIRADR 0x61 132*4882a593Smuzhiyun #define AB8500_SIDFIRCOEF1 0x62 133*4882a593Smuzhiyun #define AB8500_SIDFIRCOEF2 0x63 134*4882a593Smuzhiyun #define AB8500_SIDFIRCONF 0x64 135*4882a593Smuzhiyun #define AB8500_AUDINTMASK1 0x65 136*4882a593Smuzhiyun #define AB8500_AUDINTSOURCE1 0x66 137*4882a593Smuzhiyun #define AB8500_AUDINTMASK2 0x67 138*4882a593Smuzhiyun #define AB8500_AUDINTSOURCE2 0x68 139*4882a593Smuzhiyun #define AB8500_FIFOCONF1 0x69 140*4882a593Smuzhiyun #define AB8500_FIFOCONF2 0x6A 141*4882a593Smuzhiyun #define AB8500_FIFOCONF3 0x6B 142*4882a593Smuzhiyun #define AB8500_FIFOCONF4 0x6C 143*4882a593Smuzhiyun #define AB8500_FIFOCONF5 0x6D 144*4882a593Smuzhiyun #define AB8500_FIFOCONF6 0x6E 145*4882a593Smuzhiyun #define AB8500_AUDREV 0x6F 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define AB8500_FIRST_REG AB8500_POWERUP 148*4882a593Smuzhiyun #define AB8500_LAST_REG AB8500_AUDREV 149*4882a593Smuzhiyun #define AB8500_CACHEREGNUM (AB8500_LAST_REG + 1) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define AB8500_MASK_ALL 0xFF 152*4882a593Smuzhiyun #define AB8500_MASK_SLOT(slot) ((slot & 1) ? 0xF0 : 0x0F) 153*4882a593Smuzhiyun #define AB8500_MASK_NONE 0x00 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* AB8500_POWERUP */ 156*4882a593Smuzhiyun #define AB8500_POWERUP_POWERUP 7 157*4882a593Smuzhiyun #define AB8500_POWERUP_ENANA 3 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* AB8500_AUDSWRESET */ 160*4882a593Smuzhiyun #define AB8500_AUDSWRESET_SWRESET 7 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* AB8500_ADPATHENA */ 163*4882a593Smuzhiyun #define AB8500_ADPATHENA_ENAD12 7 164*4882a593Smuzhiyun #define AB8500_ADPATHENA_ENAD34 5 165*4882a593Smuzhiyun #define AB8500_ADPATHENA_ENAD5768 3 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* AB8500_DAPATHENA */ 168*4882a593Smuzhiyun #define AB8500_DAPATHENA_ENDA1 7 169*4882a593Smuzhiyun #define AB8500_DAPATHENA_ENDA2 6 170*4882a593Smuzhiyun #define AB8500_DAPATHENA_ENDA3 5 171*4882a593Smuzhiyun #define AB8500_DAPATHENA_ENDA4 4 172*4882a593Smuzhiyun #define AB8500_DAPATHENA_ENDA5 3 173*4882a593Smuzhiyun #define AB8500_DAPATHENA_ENDA6 2 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* AB8500_ANACONF1 */ 176*4882a593Smuzhiyun #define AB8500_ANACONF1_HSLOWPOW 7 177*4882a593Smuzhiyun #define AB8500_ANACONF1_DACLOWPOW1 6 178*4882a593Smuzhiyun #define AB8500_ANACONF1_DACLOWPOW0 5 179*4882a593Smuzhiyun #define AB8500_ANACONF1_EARDACLOWPOW 4 180*4882a593Smuzhiyun #define AB8500_ANACONF1_EARSELCM 2 181*4882a593Smuzhiyun #define AB8500_ANACONF1_HSHPEN 1 182*4882a593Smuzhiyun #define AB8500_ANACONF1_EARDRVLOWPOW 0 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* AB8500_ANACONF2 */ 185*4882a593Smuzhiyun #define AB8500_ANACONF2_ENMIC1 7 186*4882a593Smuzhiyun #define AB8500_ANACONF2_ENMIC2 6 187*4882a593Smuzhiyun #define AB8500_ANACONF2_ENLINL 5 188*4882a593Smuzhiyun #define AB8500_ANACONF2_ENLINR 4 189*4882a593Smuzhiyun #define AB8500_ANACONF2_MUTMIC1 3 190*4882a593Smuzhiyun #define AB8500_ANACONF2_MUTMIC2 2 191*4882a593Smuzhiyun #define AB8500_ANACONF2_MUTLINL 1 192*4882a593Smuzhiyun #define AB8500_ANACONF2_MUTLINR 0 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* AB8500_DIGMICCONF */ 195*4882a593Smuzhiyun #define AB8500_DIGMICCONF_ENDMIC1 7 196*4882a593Smuzhiyun #define AB8500_DIGMICCONF_ENDMIC2 6 197*4882a593Smuzhiyun #define AB8500_DIGMICCONF_ENDMIC3 5 198*4882a593Smuzhiyun #define AB8500_DIGMICCONF_ENDMIC4 4 199*4882a593Smuzhiyun #define AB8500_DIGMICCONF_ENDMIC5 3 200*4882a593Smuzhiyun #define AB8500_DIGMICCONF_ENDMIC6 2 201*4882a593Smuzhiyun #define AB8500_DIGMICCONF_HSFADSPEED 0 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* AB8500_ANACONF3 */ 204*4882a593Smuzhiyun #define AB8500_ANACONF3_MIC1SEL 7 205*4882a593Smuzhiyun #define AB8500_ANACONF3_LINRSEL 6 206*4882a593Smuzhiyun #define AB8500_ANACONF3_ENDRVHSL 5 207*4882a593Smuzhiyun #define AB8500_ANACONF3_ENDRVHSR 4 208*4882a593Smuzhiyun #define AB8500_ANACONF3_ENADCMIC 2 209*4882a593Smuzhiyun #define AB8500_ANACONF3_ENADCLINL 1 210*4882a593Smuzhiyun #define AB8500_ANACONF3_ENADCLINR 0 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun /* AB8500_ANACONF4 */ 213*4882a593Smuzhiyun #define AB8500_ANACONF4_DISPDVSS 7 214*4882a593Smuzhiyun #define AB8500_ANACONF4_ENEAR 6 215*4882a593Smuzhiyun #define AB8500_ANACONF4_ENHSL 5 216*4882a593Smuzhiyun #define AB8500_ANACONF4_ENHSR 4 217*4882a593Smuzhiyun #define AB8500_ANACONF4_ENHFL 3 218*4882a593Smuzhiyun #define AB8500_ANACONF4_ENHFR 2 219*4882a593Smuzhiyun #define AB8500_ANACONF4_ENVIB1 1 220*4882a593Smuzhiyun #define AB8500_ANACONF4_ENVIB2 0 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /* AB8500_DAPATHCONF */ 223*4882a593Smuzhiyun #define AB8500_DAPATHCONF_ENDACEAR 6 224*4882a593Smuzhiyun #define AB8500_DAPATHCONF_ENDACHSL 5 225*4882a593Smuzhiyun #define AB8500_DAPATHCONF_ENDACHSR 4 226*4882a593Smuzhiyun #define AB8500_DAPATHCONF_ENDACHFL 3 227*4882a593Smuzhiyun #define AB8500_DAPATHCONF_ENDACHFR 2 228*4882a593Smuzhiyun #define AB8500_DAPATHCONF_ENDACVIB1 1 229*4882a593Smuzhiyun #define AB8500_DAPATHCONF_ENDACVIB2 0 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* AB8500_MUTECONF */ 232*4882a593Smuzhiyun #define AB8500_MUTECONF_MUTEAR 6 233*4882a593Smuzhiyun #define AB8500_MUTECONF_MUTHSL 5 234*4882a593Smuzhiyun #define AB8500_MUTECONF_MUTHSR 4 235*4882a593Smuzhiyun #define AB8500_MUTECONF_MUTDACEAR 2 236*4882a593Smuzhiyun #define AB8500_MUTECONF_MUTDACHSL 1 237*4882a593Smuzhiyun #define AB8500_MUTECONF_MUTDACHSR 0 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun /* AB8500_SHORTCIRCONF */ 240*4882a593Smuzhiyun #define AB8500_SHORTCIRCONF_ENSHORTPWD 7 241*4882a593Smuzhiyun #define AB8500_SHORTCIRCONF_EARSHORTDIS 6 242*4882a593Smuzhiyun #define AB8500_SHORTCIRCONF_HSSHORTDIS 5 243*4882a593Smuzhiyun #define AB8500_SHORTCIRCONF_HSPULLDEN 4 244*4882a593Smuzhiyun #define AB8500_SHORTCIRCONF_HSOSCEN 2 245*4882a593Smuzhiyun #define AB8500_SHORTCIRCONF_HSFADDIS 1 246*4882a593Smuzhiyun #define AB8500_SHORTCIRCONF_HSZCDDIS 0 247*4882a593Smuzhiyun /* Zero cross should be disabled */ 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* AB8500_ANACONF5 */ 250*4882a593Smuzhiyun #define AB8500_ANACONF5_ENCPHS 7 251*4882a593Smuzhiyun #define AB8500_ANACONF5_HSLDACTOLOL 5 252*4882a593Smuzhiyun #define AB8500_ANACONF5_HSRDACTOLOR 4 253*4882a593Smuzhiyun #define AB8500_ANACONF5_ENLOL 3 254*4882a593Smuzhiyun #define AB8500_ANACONF5_ENLOR 2 255*4882a593Smuzhiyun #define AB8500_ANACONF5_HSAUTOEN 0 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun /* AB8500_ENVCPCONF */ 258*4882a593Smuzhiyun #define AB8500_ENVCPCONF_ENVDETHTHRE 4 259*4882a593Smuzhiyun #define AB8500_ENVCPCONF_ENVDETLTHRE 0 260*4882a593Smuzhiyun #define AB8500_ENVCPCONF_ENVDETHTHRE_MAX 0x0F 261*4882a593Smuzhiyun #define AB8500_ENVCPCONF_ENVDETLTHRE_MAX 0x0F 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* AB8500_SIGENVCONF */ 264*4882a593Smuzhiyun #define AB8500_SIGENVCONF_CPLVEN 5 265*4882a593Smuzhiyun #define AB8500_SIGENVCONF_ENVDETCPEN 4 266*4882a593Smuzhiyun #define AB8500_SIGENVCONF_ENVDETTIME 0 267*4882a593Smuzhiyun #define AB8500_SIGENVCONF_ENVDETTIME_MAX 0x0F 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /* AB8500_PWMGENCONF1 */ 270*4882a593Smuzhiyun #define AB8500_PWMGENCONF1_PWMTOVIB1 7 271*4882a593Smuzhiyun #define AB8500_PWMGENCONF1_PWMTOVIB2 6 272*4882a593Smuzhiyun #define AB8500_PWMGENCONF1_PWM1CTRL 5 273*4882a593Smuzhiyun #define AB8500_PWMGENCONF1_PWM2CTRL 4 274*4882a593Smuzhiyun #define AB8500_PWMGENCONF1_PWM1NCTRL 3 275*4882a593Smuzhiyun #define AB8500_PWMGENCONF1_PWM1PCTRL 2 276*4882a593Smuzhiyun #define AB8500_PWMGENCONF1_PWM2NCTRL 1 277*4882a593Smuzhiyun #define AB8500_PWMGENCONF1_PWM2PCTRL 0 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun /* AB8500_PWMGENCONF2 */ 280*4882a593Smuzhiyun /* AB8500_PWMGENCONF3 */ 281*4882a593Smuzhiyun /* AB8500_PWMGENCONF4 */ 282*4882a593Smuzhiyun /* AB8500_PWMGENCONF5 */ 283*4882a593Smuzhiyun #define AB8500_PWMGENCONFX_PWMVIBXPOL 7 284*4882a593Smuzhiyun #define AB8500_PWMGENCONFX_PWMVIBXDUTCYC 0 285*4882a593Smuzhiyun #define AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX 0x64 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* AB8500_ANAGAIN1 */ 288*4882a593Smuzhiyun /* AB8500_ANAGAIN2 */ 289*4882a593Smuzhiyun #define AB8500_ANAGAINX_ENSEMICX 7 290*4882a593Smuzhiyun #define AB8500_ANAGAINX_LOWPOWMICX 6 291*4882a593Smuzhiyun #define AB8500_ANAGAINX_MICXGAIN 0 292*4882a593Smuzhiyun #define AB8500_ANAGAINX_MICXGAIN_MAX 0x1F 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /* AB8500_ANAGAIN3 */ 295*4882a593Smuzhiyun #define AB8500_ANAGAIN3_HSLGAIN 4 296*4882a593Smuzhiyun #define AB8500_ANAGAIN3_HSRGAIN 0 297*4882a593Smuzhiyun #define AB8500_ANAGAIN3_HSXGAIN_MAX 0x0F 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun /* AB8500_ANAGAIN4 */ 300*4882a593Smuzhiyun #define AB8500_ANAGAIN4_LINLGAIN 4 301*4882a593Smuzhiyun #define AB8500_ANAGAIN4_LINRGAIN 0 302*4882a593Smuzhiyun #define AB8500_ANAGAIN4_LINXGAIN_MAX 0x0F 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /* AB8500_DIGLINHSLGAIN */ 305*4882a593Smuzhiyun /* AB8500_DIGLINHSRGAIN */ 306*4882a593Smuzhiyun #define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN 0 307*4882a593Smuzhiyun #define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX 0x13 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun /* AB8500_ADFILTCONF */ 310*4882a593Smuzhiyun #define AB8500_ADFILTCONF_AD1NH 7 311*4882a593Smuzhiyun #define AB8500_ADFILTCONF_AD2NH 6 312*4882a593Smuzhiyun #define AB8500_ADFILTCONF_AD3NH 5 313*4882a593Smuzhiyun #define AB8500_ADFILTCONF_AD4NH 4 314*4882a593Smuzhiyun #define AB8500_ADFILTCONF_AD1VOICE 3 315*4882a593Smuzhiyun #define AB8500_ADFILTCONF_AD2VOICE 2 316*4882a593Smuzhiyun #define AB8500_ADFILTCONF_AD3VOICE 1 317*4882a593Smuzhiyun #define AB8500_ADFILTCONF_AD4VOICE 0 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /* AB8500_DIGIFCONF1 */ 320*4882a593Smuzhiyun #define AB8500_DIGIFCONF1_ENMASTGEN 7 321*4882a593Smuzhiyun #define AB8500_DIGIFCONF1_IF1BITCLKOS1 6 322*4882a593Smuzhiyun #define AB8500_DIGIFCONF1_IF1BITCLKOS0 5 323*4882a593Smuzhiyun #define AB8500_DIGIFCONF1_ENFSBITCLK1 4 324*4882a593Smuzhiyun #define AB8500_DIGIFCONF1_IF0BITCLKOS1 2 325*4882a593Smuzhiyun #define AB8500_DIGIFCONF1_IF0BITCLKOS0 1 326*4882a593Smuzhiyun #define AB8500_DIGIFCONF1_ENFSBITCLK0 0 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun /* AB8500_DIGIFCONF2 */ 329*4882a593Smuzhiyun #define AB8500_DIGIFCONF2_FSYNC0P 6 330*4882a593Smuzhiyun #define AB8500_DIGIFCONF2_BITCLK0P 5 331*4882a593Smuzhiyun #define AB8500_DIGIFCONF2_IF0DEL 4 332*4882a593Smuzhiyun #define AB8500_DIGIFCONF2_IF0FORMAT1 3 333*4882a593Smuzhiyun #define AB8500_DIGIFCONF2_IF0FORMAT0 2 334*4882a593Smuzhiyun #define AB8500_DIGIFCONF2_IF0WL1 1 335*4882a593Smuzhiyun #define AB8500_DIGIFCONF2_IF0WL0 0 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun /* AB8500_DIGIFCONF3 */ 338*4882a593Smuzhiyun #define AB8500_DIGIFCONF3_IF0DATOIF1AD 7 339*4882a593Smuzhiyun #define AB8500_DIGIFCONF3_IF0CLKTOIF1CLK 6 340*4882a593Smuzhiyun #define AB8500_DIGIFCONF3_IF1MASTER 5 341*4882a593Smuzhiyun #define AB8500_DIGIFCONF3_IF1DATOIF0AD 3 342*4882a593Smuzhiyun #define AB8500_DIGIFCONF3_IF1CLKTOIF0CLK 2 343*4882a593Smuzhiyun #define AB8500_DIGIFCONF3_IF0MASTER 1 344*4882a593Smuzhiyun #define AB8500_DIGIFCONF3_IF0BFIFOEN 0 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun /* AB8500_DIGIFCONF4 */ 347*4882a593Smuzhiyun #define AB8500_DIGIFCONF4_FSYNC1P 6 348*4882a593Smuzhiyun #define AB8500_DIGIFCONF4_BITCLK1P 5 349*4882a593Smuzhiyun #define AB8500_DIGIFCONF4_IF1DEL 4 350*4882a593Smuzhiyun #define AB8500_DIGIFCONF4_IF1FORMAT1 3 351*4882a593Smuzhiyun #define AB8500_DIGIFCONF4_IF1FORMAT0 2 352*4882a593Smuzhiyun #define AB8500_DIGIFCONF4_IF1WL1 1 353*4882a593Smuzhiyun #define AB8500_DIGIFCONF4_IF1WL0 0 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun /* AB8500_ADSLOTSELX */ 356*4882a593Smuzhiyun #define AB8500_AD_OUT1 0x0 357*4882a593Smuzhiyun #define AB8500_AD_OUT2 0x1 358*4882a593Smuzhiyun #define AB8500_AD_OUT3 0x2 359*4882a593Smuzhiyun #define AB8500_AD_OUT4 0x3 360*4882a593Smuzhiyun #define AB8500_AD_OUT5 0x4 361*4882a593Smuzhiyun #define AB8500_AD_OUT6 0x5 362*4882a593Smuzhiyun #define AB8500_AD_OUT7 0x6 363*4882a593Smuzhiyun #define AB8500_AD_OUT8 0x7 364*4882a593Smuzhiyun #define AB8500_ZEROES 0x8 365*4882a593Smuzhiyun #define AB8500_TRISTATE 0xF 366*4882a593Smuzhiyun #define AB8500_ADSLOTSELX_EVEN_SHIFT 0 367*4882a593Smuzhiyun #define AB8500_ADSLOTSELX_ODD_SHIFT 4 368*4882a593Smuzhiyun #define AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(out, slot) \ 369*4882a593Smuzhiyun ((out) << (((slot) & 1) ? \ 370*4882a593Smuzhiyun AB8500_ADSLOTSELX_ODD_SHIFT : AB8500_ADSLOTSELX_EVEN_SHIFT)) 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun /* AB8500_ADSLOTHIZCTRL1 */ 373*4882a593Smuzhiyun /* AB8500_ADSLOTHIZCTRL2 */ 374*4882a593Smuzhiyun /* AB8500_ADSLOTHIZCTRL3 */ 375*4882a593Smuzhiyun /* AB8500_ADSLOTHIZCTRL4 */ 376*4882a593Smuzhiyun /* AB8500_DASLOTCONF1 */ 377*4882a593Smuzhiyun #define AB8500_DASLOTCONF1_DA12VOICE 7 378*4882a593Smuzhiyun #define AB8500_DASLOTCONF1_SWAPDA12_34 6 379*4882a593Smuzhiyun #define AB8500_DASLOTCONF1_DAI7TOADO1 5 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun /* AB8500_DASLOTCONF2 */ 382*4882a593Smuzhiyun #define AB8500_DASLOTCONF2_DAI8TOADO2 5 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun /* AB8500_DASLOTCONF3 */ 385*4882a593Smuzhiyun #define AB8500_DASLOTCONF3_DA34VOICE 7 386*4882a593Smuzhiyun #define AB8500_DASLOTCONF3_DAI7TOADO3 5 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun /* AB8500_DASLOTCONF4 */ 389*4882a593Smuzhiyun #define AB8500_DASLOTCONF4_DAI8TOADO4 5 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun /* AB8500_DASLOTCONF5 */ 392*4882a593Smuzhiyun #define AB8500_DASLOTCONF5_DA56VOICE 7 393*4882a593Smuzhiyun #define AB8500_DASLOTCONF5_DAI7TOADO5 5 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun /* AB8500_DASLOTCONF6 */ 396*4882a593Smuzhiyun #define AB8500_DASLOTCONF6_DAI8TOADO6 5 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun /* AB8500_DASLOTCONF7 */ 399*4882a593Smuzhiyun #define AB8500_DASLOTCONF7_DAI8TOADO7 5 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun /* AB8500_DASLOTCONF8 */ 402*4882a593Smuzhiyun #define AB8500_DASLOTCONF8_DAI7TOADO8 5 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun #define AB8500_DASLOTCONFX_SLTODAX_SHIFT 0 405*4882a593Smuzhiyun #define AB8500_DASLOTCONFX_SLTODAX_MASK 0x1F 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun /* AB8500_CLASSDCONF1 */ 408*4882a593Smuzhiyun #define AB8500_CLASSDCONF1_PARLHF 7 409*4882a593Smuzhiyun #define AB8500_CLASSDCONF1_PARLVIB 6 410*4882a593Smuzhiyun #define AB8500_CLASSDCONF1_VIB1SWAPEN 3 411*4882a593Smuzhiyun #define AB8500_CLASSDCONF1_VIB2SWAPEN 2 412*4882a593Smuzhiyun #define AB8500_CLASSDCONF1_HFLSWAPEN 1 413*4882a593Smuzhiyun #define AB8500_CLASSDCONF1_HFRSWAPEN 0 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun /* AB8500_CLASSDCONF2 */ 416*4882a593Smuzhiyun #define AB8500_CLASSDCONF2_FIRBYP3 7 417*4882a593Smuzhiyun #define AB8500_CLASSDCONF2_FIRBYP2 6 418*4882a593Smuzhiyun #define AB8500_CLASSDCONF2_FIRBYP1 5 419*4882a593Smuzhiyun #define AB8500_CLASSDCONF2_FIRBYP0 4 420*4882a593Smuzhiyun #define AB8500_CLASSDCONF2_HIGHVOLEN3 3 421*4882a593Smuzhiyun #define AB8500_CLASSDCONF2_HIGHVOLEN2 2 422*4882a593Smuzhiyun #define AB8500_CLASSDCONF2_HIGHVOLEN1 1 423*4882a593Smuzhiyun #define AB8500_CLASSDCONF2_HIGHVOLEN0 0 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun /* AB8500_CLASSDCONF3 */ 426*4882a593Smuzhiyun #define AB8500_CLASSDCONF3_DITHHPGAIN 4 427*4882a593Smuzhiyun #define AB8500_CLASSDCONF3_DITHHPGAIN_MAX 0x0A 428*4882a593Smuzhiyun #define AB8500_CLASSDCONF3_DITHWGAIN 0 429*4882a593Smuzhiyun #define AB8500_CLASSDCONF3_DITHWGAIN_MAX 0x0A 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun /* AB8500_DMICFILTCONF */ 432*4882a593Smuzhiyun #define AB8500_DMICFILTCONF_ANCINSEL 7 433*4882a593Smuzhiyun #define AB8500_DMICFILTCONF_DA3TOEAR 6 434*4882a593Smuzhiyun #define AB8500_DMICFILTCONF_DMIC1SINC3 5 435*4882a593Smuzhiyun #define AB8500_DMICFILTCONF_DMIC2SINC3 4 436*4882a593Smuzhiyun #define AB8500_DMICFILTCONF_DMIC3SINC3 3 437*4882a593Smuzhiyun #define AB8500_DMICFILTCONF_DMIC4SINC3 2 438*4882a593Smuzhiyun #define AB8500_DMICFILTCONF_DMIC5SINC3 1 439*4882a593Smuzhiyun #define AB8500_DMICFILTCONF_DMIC6SINC3 0 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun /* AB8500_DIGMULTCONF1 */ 442*4882a593Smuzhiyun #define AB8500_DIGMULTCONF1_DATOHSLEN 7 443*4882a593Smuzhiyun #define AB8500_DIGMULTCONF1_DATOHSREN 6 444*4882a593Smuzhiyun #define AB8500_DIGMULTCONF1_AD1SEL 5 445*4882a593Smuzhiyun #define AB8500_DIGMULTCONF1_AD2SEL 4 446*4882a593Smuzhiyun #define AB8500_DIGMULTCONF1_AD3SEL 3 447*4882a593Smuzhiyun #define AB8500_DIGMULTCONF1_AD5SEL 2 448*4882a593Smuzhiyun #define AB8500_DIGMULTCONF1_AD6SEL 1 449*4882a593Smuzhiyun #define AB8500_DIGMULTCONF1_ANCSEL 0 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun /* AB8500_DIGMULTCONF2 */ 452*4882a593Smuzhiyun #define AB8500_DIGMULTCONF2_DATOHFREN 7 453*4882a593Smuzhiyun #define AB8500_DIGMULTCONF2_DATOHFLEN 6 454*4882a593Smuzhiyun #define AB8500_DIGMULTCONF2_HFRSEL 5 455*4882a593Smuzhiyun #define AB8500_DIGMULTCONF2_HFLSEL 4 456*4882a593Smuzhiyun #define AB8500_DIGMULTCONF2_FIRSID1SEL 2 457*4882a593Smuzhiyun #define AB8500_DIGMULTCONF2_FIRSID2SEL 0 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun /* AB8500_ADDIGGAIN1 */ 460*4882a593Smuzhiyun /* AB8500_ADDIGGAIN2 */ 461*4882a593Smuzhiyun /* AB8500_ADDIGGAIN3 */ 462*4882a593Smuzhiyun /* AB8500_ADDIGGAIN4 */ 463*4882a593Smuzhiyun /* AB8500_ADDIGGAIN5 */ 464*4882a593Smuzhiyun /* AB8500_ADDIGGAIN6 */ 465*4882a593Smuzhiyun #define AB8500_ADDIGGAINX_FADEDISADX 6 466*4882a593Smuzhiyun #define AB8500_ADDIGGAINX_ADXGAIN_MAX 0x3F 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun /* AB8500_DADIGGAIN1 */ 469*4882a593Smuzhiyun /* AB8500_DADIGGAIN2 */ 470*4882a593Smuzhiyun /* AB8500_DADIGGAIN3 */ 471*4882a593Smuzhiyun /* AB8500_DADIGGAIN4 */ 472*4882a593Smuzhiyun /* AB8500_DADIGGAIN5 */ 473*4882a593Smuzhiyun /* AB8500_DADIGGAIN6 */ 474*4882a593Smuzhiyun #define AB8500_DADIGGAINX_FADEDISDAX 6 475*4882a593Smuzhiyun #define AB8500_DADIGGAINX_DAXGAIN_MAX 0x3F 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun /* AB8500_ADDIGLOOPGAIN1 */ 478*4882a593Smuzhiyun /* AB8500_ADDIGLOOPGAIN2 */ 479*4882a593Smuzhiyun #define AB8500_ADDIGLOOPGAINX_FADEDISADXL 6 480*4882a593Smuzhiyun #define AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX 0x3F 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun /* AB8500_HSLEARDIGGAIN */ 483*4882a593Smuzhiyun #define AB8500_HSLEARDIGGAIN_HSSINC1 7 484*4882a593Smuzhiyun #define AB8500_HSLEARDIGGAIN_FADEDISHSL 4 485*4882a593Smuzhiyun #define AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX 0x09 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun /* AB8500_HSRDIGGAIN */ 488*4882a593Smuzhiyun #define AB8500_HSRDIGGAIN_FADESPEED 6 489*4882a593Smuzhiyun #define AB8500_HSRDIGGAIN_FADEDISHSR 4 490*4882a593Smuzhiyun #define AB8500_HSRDIGGAIN_HSRDGAIN_MAX 0x09 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun /* AB8500_SIDFIRGAIN1 */ 493*4882a593Smuzhiyun /* AB8500_SIDFIRGAIN2 */ 494*4882a593Smuzhiyun #define AB8500_SIDFIRGAINX_FIRSIDXGAIN_MAX 0x1F 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun /* AB8500_ANCCONF1 */ 497*4882a593Smuzhiyun #define AB8500_ANCCONF1_ANCIIRUPDATE 3 498*4882a593Smuzhiyun #define AB8500_ANCCONF1_ENANC 2 499*4882a593Smuzhiyun #define AB8500_ANCCONF1_ANCIIRINIT 1 500*4882a593Smuzhiyun #define AB8500_ANCCONF1_ANCFIRUPDATE 0 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun /* AB8500_ANCCONF2 */ 503*4882a593Smuzhiyun #define AB8500_ANCCONF2_SHIFT 5 504*4882a593Smuzhiyun #define AB8500_ANCCONF2_MIN -0x10 505*4882a593Smuzhiyun #define AB8500_ANCCONF2_MAX 0xF 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun /* AB8500_ANCCONF3 */ 508*4882a593Smuzhiyun #define AB8500_ANCCONF3_SHIFT 5 509*4882a593Smuzhiyun #define AB8500_ANCCONF3_MIN -0x10 510*4882a593Smuzhiyun #define AB8500_ANCCONF3_MAX 0xF 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun /* AB8500_ANCCONF4 */ 513*4882a593Smuzhiyun #define AB8500_ANCCONF4_SHIFT 5 514*4882a593Smuzhiyun #define AB8500_ANCCONF4_MIN -0x10 515*4882a593Smuzhiyun #define AB8500_ANCCONF4_MAX 0xF 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun /* AB8500_ANC_FIR_COEFFS */ 518*4882a593Smuzhiyun #define AB8500_ANC_FIR_COEFF_MIN -0x8000 519*4882a593Smuzhiyun #define AB8500_ANC_FIR_COEFF_MAX 0x7FFF 520*4882a593Smuzhiyun #define AB8500_ANC_FIR_COEFFS 15 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun /* AB8500_ANC_IIR_COEFFS */ 523*4882a593Smuzhiyun #define AB8500_ANC_IIR_COEFF_MIN -0x800000 524*4882a593Smuzhiyun #define AB8500_ANC_IIR_COEFF_MAX 0x7FFFFF 525*4882a593Smuzhiyun #define AB8500_ANC_IIR_COEFFS 24 526*4882a593Smuzhiyun /* AB8500_ANC_WARP_DELAY */ 527*4882a593Smuzhiyun #define AB8500_ANC_WARP_DELAY_SHIFT 16 528*4882a593Smuzhiyun #define AB8500_ANC_WARP_DELAY_MIN 0x0000 529*4882a593Smuzhiyun #define AB8500_ANC_WARP_DELAY_MAX 0xFFFF 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun /* AB8500_ANCCONF11 */ 532*4882a593Smuzhiyun /* AB8500_ANCCONF12 */ 533*4882a593Smuzhiyun /* AB8500_ANCCONF13 */ 534*4882a593Smuzhiyun /* AB8500_ANCCONF14 */ 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun /* AB8500_SIDFIRADR */ 537*4882a593Smuzhiyun #define AB8500_SIDFIRADR_FIRSIDSET 7 538*4882a593Smuzhiyun #define AB8500_SIDFIRADR_ADDRESS_SHIFT 0 539*4882a593Smuzhiyun #define AB8500_SIDFIRADR_ADDRESS_MAX 0x7F 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun /* AB8500_SIDFIRCOEF1 */ 542*4882a593Smuzhiyun /* AB8500_SIDFIRCOEF2 */ 543*4882a593Smuzhiyun #define AB8500_SID_FIR_COEFF_MIN 0 544*4882a593Smuzhiyun #define AB8500_SID_FIR_COEFF_MAX 0xFFFF 545*4882a593Smuzhiyun #define AB8500_SID_FIR_COEFFS 128 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun /* AB8500_SIDFIRCONF */ 548*4882a593Smuzhiyun #define AB8500_SIDFIRCONF_ENFIRSIDS 2 549*4882a593Smuzhiyun #define AB8500_SIDFIRCONF_FIRSIDSTOIF1 1 550*4882a593Smuzhiyun #define AB8500_SIDFIRCONF_FIRSIDBUSY 0 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun /* AB8500_AUDINTMASK1 */ 553*4882a593Smuzhiyun /* AB8500_AUDINTSOURCE1 */ 554*4882a593Smuzhiyun /* AB8500_AUDINTMASK2 */ 555*4882a593Smuzhiyun /* AB8500_AUDINTSOURCE2 */ 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun /* AB8500_FIFOCONF1 */ 558*4882a593Smuzhiyun #define AB8500_FIFOCONF1_BFIFOMASK 0x80 559*4882a593Smuzhiyun #define AB8500_FIFOCONF1_BFIFO19M2 0x40 560*4882a593Smuzhiyun #define AB8500_FIFOCONF1_BFIFOINT_SHIFT 0 561*4882a593Smuzhiyun #define AB8500_FIFOCONF1_BFIFOINT_MAX 0x3F 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun /* AB8500_FIFOCONF2 */ 564*4882a593Smuzhiyun #define AB8500_FIFOCONF2_BFIFOTX_SHIFT 0 565*4882a593Smuzhiyun #define AB8500_FIFOCONF2_BFIFOTX_MAX 0xFF 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun /* AB8500_FIFOCONF3 */ 568*4882a593Smuzhiyun #define AB8500_FIFOCONF3_BFIFOEXSL_SHIFT 5 569*4882a593Smuzhiyun #define AB8500_FIFOCONF3_BFIFOEXSL_MAX 0x5 570*4882a593Smuzhiyun #define AB8500_FIFOCONF3_PREBITCLK0_SHIFT 2 571*4882a593Smuzhiyun #define AB8500_FIFOCONF3_PREBITCLK0_MAX 0x7 572*4882a593Smuzhiyun #define AB8500_FIFOCONF3_BFIFOMAST_SHIFT 1 573*4882a593Smuzhiyun #define AB8500_FIFOCONF3_BFIFORUN_SHIFT 0 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun /* AB8500_FIFOCONF4 */ 576*4882a593Smuzhiyun #define AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT 0 577*4882a593Smuzhiyun #define AB8500_FIFOCONF4_BFIFOFRAMSW_MAX 0xFF 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun /* AB8500_FIFOCONF5 */ 580*4882a593Smuzhiyun #define AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT 0 581*4882a593Smuzhiyun #define AB8500_FIFOCONF5_BFIFOWAKEUP_MAX 0xFF 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun /* AB8500_FIFOCONF6 */ 584*4882a593Smuzhiyun #define AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT 0 585*4882a593Smuzhiyun #define AB8500_FIFOCONF6_BFIFOSAMPLE_MAX 0xFF 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun /* AB8500_AUDREV */ 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun #endif 590