1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun // linux/sound/soc/bcm/bcm63xx-i2s.h 3*4882a593Smuzhiyun // Copyright (c) 2020 Broadcom Corporation 4*4882a593Smuzhiyun // Author: Kevin-Ke Li <kevin-ke.li@broadcom.com> 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __BCM63XX_I2S_H 7*4882a593Smuzhiyun #define __BCM63XX_I2S_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define I2S_DESC_FIFO_DEPTH 8 10*4882a593Smuzhiyun #define I2S_MISC_CFG (0x003C) 11*4882a593Smuzhiyun #define I2S_PAD_LVL_LOOP_DIS_MASK (1 << 2) 12*4882a593Smuzhiyun #define I2S_PAD_LVL_LOOP_DIS_ENABLE I2S_PAD_LVL_LOOP_DIS_MASK 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define I2S_TX_ENABLE_MASK (1 << 31) 15*4882a593Smuzhiyun #define I2S_TX_ENABLE I2S_TX_ENABLE_MASK 16*4882a593Smuzhiyun #define I2S_TX_OUT_R (1 << 19) 17*4882a593Smuzhiyun #define I2S_TX_DATA_ALIGNMENT (1 << 2) 18*4882a593Smuzhiyun #define I2S_TX_DATA_ENABLE (1 << 1) 19*4882a593Smuzhiyun #define I2S_TX_CLOCK_ENABLE (1 << 0) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define I2S_TX_DESC_OFF_LEVEL_SHIFT 12 22*4882a593Smuzhiyun #define I2S_TX_DESC_OFF_LEVEL_MASK (0x0F << I2S_TX_DESC_OFF_LEVEL_SHIFT) 23*4882a593Smuzhiyun #define I2S_TX_DESC_IFF_LEVEL_SHIFT 8 24*4882a593Smuzhiyun #define I2S_TX_DESC_IFF_LEVEL_MASK (0x0F << I2S_TX_DESC_IFF_LEVEL_SHIFT) 25*4882a593Smuzhiyun #define I2S_TX_DESC_OFF_INTR_EN_MSK (1 << 1) 26*4882a593Smuzhiyun #define I2S_TX_DESC_OFF_INTR_EN I2S_TX_DESC_OFF_INTR_EN_MSK 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define I2S_TX_CFG (0x0000) 29*4882a593Smuzhiyun #define I2S_TX_IRQ_CTL (0x0004) 30*4882a593Smuzhiyun #define I2S_TX_IRQ_EN (0x0008) 31*4882a593Smuzhiyun #define I2S_TX_IRQ_IFF_THLD (0x000c) 32*4882a593Smuzhiyun #define I2S_TX_IRQ_OFF_THLD (0x0010) 33*4882a593Smuzhiyun #define I2S_TX_DESC_IFF_ADDR (0x0014) 34*4882a593Smuzhiyun #define I2S_TX_DESC_IFF_LEN (0x0018) 35*4882a593Smuzhiyun #define I2S_TX_DESC_OFF_ADDR (0x001C) 36*4882a593Smuzhiyun #define I2S_TX_DESC_OFF_LEN (0x0020) 37*4882a593Smuzhiyun #define I2S_TX_CFG_2 (0x0024) 38*4882a593Smuzhiyun #define I2S_TX_SLAVE_MODE_SHIFT 13 39*4882a593Smuzhiyun #define I2S_TX_SLAVE_MODE_MASK (1 << I2S_TX_SLAVE_MODE_SHIFT) 40*4882a593Smuzhiyun #define I2S_TX_SLAVE_MODE I2S_TX_SLAVE_MODE_MASK 41*4882a593Smuzhiyun #define I2S_TX_MASTER_MODE 0 42*4882a593Smuzhiyun #define I2S_TX_INTR_MASK 0x0F 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define I2S_RX_ENABLE_MASK (1 << 31) 45*4882a593Smuzhiyun #define I2S_RX_ENABLE I2S_RX_ENABLE_MASK 46*4882a593Smuzhiyun #define I2S_RX_IN_R (1 << 19) 47*4882a593Smuzhiyun #define I2S_RX_DATA_ALIGNMENT (1 << 2) 48*4882a593Smuzhiyun #define I2S_RX_CLOCK_ENABLE (1 << 0) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define I2S_RX_DESC_OFF_LEVEL_SHIFT 12 51*4882a593Smuzhiyun #define I2S_RX_DESC_OFF_LEVEL_MASK (0x0F << I2S_RX_DESC_OFF_LEVEL_SHIFT) 52*4882a593Smuzhiyun #define I2S_RX_DESC_IFF_LEVEL_SHIFT 8 53*4882a593Smuzhiyun #define I2S_RX_DESC_IFF_LEVEL_MASK (0x0F << I2S_RX_DESC_IFF_LEVEL_SHIFT) 54*4882a593Smuzhiyun #define I2S_RX_DESC_OFF_INTR_EN_MSK (1 << 1) 55*4882a593Smuzhiyun #define I2S_RX_DESC_OFF_INTR_EN I2S_RX_DESC_OFF_INTR_EN_MSK 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define I2S_RX_CFG (0x0040) /* 20c0 */ 58*4882a593Smuzhiyun #define I2S_RX_IRQ_CTL (0x0044) 59*4882a593Smuzhiyun #define I2S_RX_IRQ_EN (0x0048) 60*4882a593Smuzhiyun #define I2S_RX_IRQ_IFF_THLD (0x004C) 61*4882a593Smuzhiyun #define I2S_RX_IRQ_OFF_THLD (0x0050) 62*4882a593Smuzhiyun #define I2S_RX_DESC_IFF_ADDR (0x0054) 63*4882a593Smuzhiyun #define I2S_RX_DESC_IFF_LEN (0x0058) 64*4882a593Smuzhiyun #define I2S_RX_DESC_OFF_ADDR (0x005C) 65*4882a593Smuzhiyun #define I2S_RX_DESC_OFF_LEN (0x0060) 66*4882a593Smuzhiyun #define I2S_RX_CFG_2 (0x0064) 67*4882a593Smuzhiyun #define I2S_RX_SLAVE_MODE_SHIFT 13 68*4882a593Smuzhiyun #define I2S_RX_SLAVE_MODE_MASK (1 << I2S_RX_SLAVE_MODE_SHIFT) 69*4882a593Smuzhiyun #define I2S_RX_SLAVE_MODE I2S_RX_SLAVE_MODE_MASK 70*4882a593Smuzhiyun #define I2S_RX_MASTER_MODE 0 71*4882a593Smuzhiyun #define I2S_RX_INTR_MASK 0x0F 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define I2S_REG_MAX 0x007C 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct bcm_i2s_priv { 76*4882a593Smuzhiyun struct device *dev; 77*4882a593Smuzhiyun struct resource *r_irq; 78*4882a593Smuzhiyun struct regmap *regmap_i2s; 79*4882a593Smuzhiyun struct clk *i2s_clk; 80*4882a593Smuzhiyun struct snd_pcm_substream *play_substream; 81*4882a593Smuzhiyun struct snd_pcm_substream *capture_substream; 82*4882a593Smuzhiyun struct i2s_dma_desc *play_dma_desc; 83*4882a593Smuzhiyun struct i2s_dma_desc *capture_dma_desc; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun extern int bcm63xx_soc_platform_probe(struct platform_device *pdev, 87*4882a593Smuzhiyun struct bcm_i2s_priv *i2s_priv); 88*4882a593Smuzhiyun extern int bcm63xx_soc_platform_remove(struct platform_device *pdev); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif 91