xref: /OK3568_Linux_fs/kernel/sound/soc/atmel/atmel-pdmic.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __ATMEL_PDMIC_H_
3*4882a593Smuzhiyun #define __ATMEL_PDMIC_H_
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include <linux/bitops.h>
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #define PDMIC_CR	0x00000000
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #define PDMIC_CR_SWRST		0x1
10*4882a593Smuzhiyun #define PDMIC_CR_SWRST_MASK	BIT(0)
11*4882a593Smuzhiyun #define PDMIC_CR_SWRST_SHIFT	(0)
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define PDMIC_CR_ENPDM_DIS	0x0
14*4882a593Smuzhiyun #define PDMIC_CR_ENPDM_EN	0x1
15*4882a593Smuzhiyun #define PDMIC_CR_ENPDM_MASK	BIT(4)
16*4882a593Smuzhiyun #define PDMIC_CR_ENPDM_SHIFT	(4)
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define PDMIC_MR	0x00000004
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define PDMIC_MR_CLKS_PCK	0x0
21*4882a593Smuzhiyun #define PDMIC_MR_CLKS_GCK	0x1
22*4882a593Smuzhiyun #define PDMIC_MR_CLKS_MASK	BIT(4)
23*4882a593Smuzhiyun #define PDMIC_MR_CLKS_SHIFT	(4)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define PDMIC_MR_PRESCAL_MASK	GENMASK(14, 8)
26*4882a593Smuzhiyun #define PDMIC_MR_PRESCAL_SHIFT	(8)
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define PDMIC_CDR	0x00000014
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define PDMIC_IER	0x00000018
31*4882a593Smuzhiyun #define PDMIC_IER_OVRE			BIT(25)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define PDMIC_IDR	0x0000001c
34*4882a593Smuzhiyun #define PDMIC_IDR_OVRE			BIT(25)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define PDMIC_IMR	0x00000020
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define PDMIC_ISR	0x00000024
39*4882a593Smuzhiyun #define PDMIC_ISR_OVRE			BIT(25)
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define PDMIC_DSPR0	0x00000058
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define PDMIC_DSPR0_HPFBYP_DIS		0x1
44*4882a593Smuzhiyun #define PDMIC_DSPR0_HPFBYP_EN		0x0
45*4882a593Smuzhiyun #define PDMIC_DSPR0_HPFBYP_MASK		BIT(1)
46*4882a593Smuzhiyun #define PDMIC_DSPR0_HPFBYP_SHIFT	(1)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define PDMIC_DSPR0_SINBYP_DIS		0x1
49*4882a593Smuzhiyun #define PDMIC_DSPR0_SINBYP_EN		0x0
50*4882a593Smuzhiyun #define PDMIC_DSPR0_SINBYP_MASK		BIT(2)
51*4882a593Smuzhiyun #define PDMIC_DSPR0_SINBYP_SHIFT	(2)
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define PDMIC_DSPR0_SIZE_16_BITS	0x0
54*4882a593Smuzhiyun #define PDMIC_DSPR0_SIZE_32_BITS	0x1
55*4882a593Smuzhiyun #define PDMIC_DSPR0_SIZE_MASK		BIT(3)
56*4882a593Smuzhiyun #define PDMIC_DSPR0_SIZE_SHIFT		(3)
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define PDMIC_DSPR0_OSR_128		0x0
59*4882a593Smuzhiyun #define PDMIC_DSPR0_OSR_64		0x1
60*4882a593Smuzhiyun #define PDMIC_DSPR0_OSR_MASK		GENMASK(6, 4)
61*4882a593Smuzhiyun #define PDMIC_DSPR0_OSR_SHIFT		(4)
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define PDMIC_DSPR0_SCALE_MASK		GENMASK(11, 8)
64*4882a593Smuzhiyun #define PDMIC_DSPR0_SCALE_SHIFT		(8)
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define PDMIC_DSPR0_SHIFT_MASK		GENMASK(15, 12)
67*4882a593Smuzhiyun #define PDMIC_DSPR0_SHIFT_SHIFT		(12)
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define PDMIC_DSPR1	0x0000005c
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define PDMIC_DSPR1_DGAIN_MASK		GENMASK(14, 0)
72*4882a593Smuzhiyun #define PDMIC_DSPR1_DGAIN_SHIFT		(0)
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define PDMIC_DSPR1_OFFSET_MASK		GENMASK(31, 16)
75*4882a593Smuzhiyun #define PDMIC_DSPR1_OFFSET_SHIFT	(16)
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define PDMIC_WPMR	0x000000e4
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #define PDMIC_WPSR	0x000000e8
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #endif
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