1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ATMEL_CLASSD_H_ 3*4882a593Smuzhiyun #define __ATMEL_CLASSD_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define CLASSD_CR 0x00000000 6*4882a593Smuzhiyun #define CLASSD_CR_RESET 0x1 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define CLASSD_MR 0x00000004 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CLASSD_MR_LEN_DIS 0x0 11*4882a593Smuzhiyun #define CLASSD_MR_LEN_EN 0x1 12*4882a593Smuzhiyun #define CLASSD_MR_LEN_MASK (0x1 << 0) 13*4882a593Smuzhiyun #define CLASSD_MR_LEN_SHIFT (0) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CLASSD_MR_LMUTE_DIS 0x0 16*4882a593Smuzhiyun #define CLASSD_MR_LMUTE_EN 0x1 17*4882a593Smuzhiyun #define CLASSD_MR_LMUTE_SHIFT (0x1) 18*4882a593Smuzhiyun #define CLASSD_MR_LMUTE_MASK (0x1 << 1) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CLASSD_MR_REN_DIS 0x0 21*4882a593Smuzhiyun #define CLASSD_MR_REN_EN 0x1 22*4882a593Smuzhiyun #define CLASSD_MR_REN_MASK (0x1 << 4) 23*4882a593Smuzhiyun #define CLASSD_MR_REN_SHIFT (4) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CLASSD_MR_RMUTE_DIS 0x0 26*4882a593Smuzhiyun #define CLASSD_MR_RMUTE_EN 0x1 27*4882a593Smuzhiyun #define CLASSD_MR_RMUTE_SHIFT (0x5) 28*4882a593Smuzhiyun #define CLASSD_MR_RMUTE_MASK (0x1 << 5) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CLASSD_MR_PWMTYP_SINGLE 0x0 31*4882a593Smuzhiyun #define CLASSD_MR_PWMTYP_DIFF 0x1 32*4882a593Smuzhiyun #define CLASSD_MR_PWMTYP_MASK (0x1 << 8) 33*4882a593Smuzhiyun #define CLASSD_MR_PWMTYP_SHIFT (8) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CLASSD_MR_NON_OVERLAP_DIS 0x0 36*4882a593Smuzhiyun #define CLASSD_MR_NON_OVERLAP_EN 0x1 37*4882a593Smuzhiyun #define CLASSD_MR_NON_OVERLAP_MASK (0x1 << 16) 38*4882a593Smuzhiyun #define CLASSD_MR_NON_OVERLAP_SHIFT (16) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define CLASSD_MR_NOVR_VAL_5NS 0x0 41*4882a593Smuzhiyun #define CLASSD_MR_NOVR_VAL_10NS 0x1 42*4882a593Smuzhiyun #define CLASSD_MR_NOVR_VAL_15NS 0x2 43*4882a593Smuzhiyun #define CLASSD_MR_NOVR_VAL_20NS 0x3 44*4882a593Smuzhiyun #define CLASSD_MR_NOVR_VAL_MASK (0x3 << 20) 45*4882a593Smuzhiyun #define CLASSD_MR_NOVR_VAL_SHIFT (20) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define CLASSD_INTPMR 0x00000008 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CLASSD_INTPMR_ATTL_MASK (0x3f << 0) 50*4882a593Smuzhiyun #define CLASSD_INTPMR_ATTL_SHIFT (0) 51*4882a593Smuzhiyun #define CLASSD_INTPMR_ATTR_MASK (0x3f << 8) 52*4882a593Smuzhiyun #define CLASSD_INTPMR_ATTR_SHIFT (8) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define CLASSD_INTPMR_DSP_CLK_FREQ_12M288 0x0 55*4882a593Smuzhiyun #define CLASSD_INTPMR_DSP_CLK_FREQ_11M2896 0x1 56*4882a593Smuzhiyun #define CLASSD_INTPMR_DSP_CLK_FREQ_MASK (0x1 << 16) 57*4882a593Smuzhiyun #define CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT (16) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define CLASSD_INTPMR_DEEMP_DIS 0x0 60*4882a593Smuzhiyun #define CLASSD_INTPMR_DEEMP_EN 0x1 61*4882a593Smuzhiyun #define CLASSD_INTPMR_DEEMP_MASK (0x1 << 18) 62*4882a593Smuzhiyun #define CLASSD_INTPMR_DEEMP_SHIFT (18) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define CLASSD_INTPMR_SWAP_LEFT_ON_LSB 0x0 65*4882a593Smuzhiyun #define CLASSD_INTPMR_SWAP_RIGHT_ON_LSB 0x1 66*4882a593Smuzhiyun #define CLASSD_INTPMR_SWAP_MASK (0x1 << 19) 67*4882a593Smuzhiyun #define CLASSD_INTPMR_SWAP_SHIFT (19) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define CLASSD_INTPMR_FRAME_8K 0x0 70*4882a593Smuzhiyun #define CLASSD_INTPMR_FRAME_16K 0x1 71*4882a593Smuzhiyun #define CLASSD_INTPMR_FRAME_32K 0x2 72*4882a593Smuzhiyun #define CLASSD_INTPMR_FRAME_48K 0x3 73*4882a593Smuzhiyun #define CLASSD_INTPMR_FRAME_96K 0x4 74*4882a593Smuzhiyun #define CLASSD_INTPMR_FRAME_22K 0x5 75*4882a593Smuzhiyun #define CLASSD_INTPMR_FRAME_44K 0x6 76*4882a593Smuzhiyun #define CLASSD_INTPMR_FRAME_88K 0x7 77*4882a593Smuzhiyun #define CLASSD_INTPMR_FRAME_MASK (0x7 << 20) 78*4882a593Smuzhiyun #define CLASSD_INTPMR_FRAME_SHIFT (20) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_FLAT 0x0 81*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_B_BOOST_12 0x1 82*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_B_BOOST_6 0x2 83*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_B_CUT_12 0x3 84*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_B_CUT_6 0x4 85*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_M_BOOST_3 0x5 86*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_M_BOOST_8 0x6 87*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_M_CUT_3 0x7 88*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_M_CUT_8 0x8 89*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_T_BOOST_12 0x9 90*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_T_BOOST_6 0xa 91*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_T_CUT_12 0xb 92*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_T_CUT_6 0xc 93*4882a593Smuzhiyun #define CLASSD_INTPMR_EQCFG_SHIFT (24) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define CLASSD_INTPMR_MONO_DIS 0x0 96*4882a593Smuzhiyun #define CLASSD_INTPMR_MONO_EN 0x1 97*4882a593Smuzhiyun #define CLASSD_INTPMR_MONO_MASK (0x1 << 28) 98*4882a593Smuzhiyun #define CLASSD_INTPMR_MONO_SHIFT (28) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define CLASSD_INTPMR_MONO_MODE_MIX 0x0 101*4882a593Smuzhiyun #define CLASSD_INTPMR_MONO_MODE_SAT 0x1 102*4882a593Smuzhiyun #define CLASSD_INTPMR_MONO_MODE_LEFT 0x2 103*4882a593Smuzhiyun #define CLASSD_INTPMR_MONO_MODE_RIGHT 0x3 104*4882a593Smuzhiyun #define CLASSD_INTPMR_MONO_MODE_MASK (0x3 << 29) 105*4882a593Smuzhiyun #define CLASSD_INTPMR_MONO_MODE_SHIFT (29) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define CLASSD_INTSR 0x0000000c 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define CLASSD_THR 0x00000010 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define CLASSD_IER 0x00000014 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define CLASSD_IDR 0x00000018 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define CLASSD_IMR 0x0000001c 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define CLASSD_ISR 0x00000020 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define CLASSD_WPMR 0x000000e4 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #endif 122