1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * AMD ALSA SoC PDM Driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2020 Advanced Micro Devices, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include "rn_chip_offset_byte.h" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define ACP_DEVS 3 11*4882a593Smuzhiyun #define ACP_PHY_BASE_ADDRESS 0x1240000 12*4882a593Smuzhiyun #define ACP_REG_START 0x1240000 13*4882a593Smuzhiyun #define ACP_REG_END 0x1250200 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define ACP_DEVICE_ID 0x15E2 16*4882a593Smuzhiyun #define ACP_POWER_ON 0x00 17*4882a593Smuzhiyun #define ACP_POWER_ON_IN_PROGRESS 0x01 18*4882a593Smuzhiyun #define ACP_POWER_OFF 0x02 19*4882a593Smuzhiyun #define ACP_POWER_OFF_IN_PROGRESS 0x03 20*4882a593Smuzhiyun #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 23*4882a593Smuzhiyun #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00 24*4882a593Smuzhiyun #define ACP_PGFSM_STATUS_MASK 0x03 25*4882a593Smuzhiyun #define ACP_POWERED_ON 0x00 26*4882a593Smuzhiyun #define ACP_POWER_ON_IN_PROGRESS 0x01 27*4882a593Smuzhiyun #define ACP_POWERED_OFF 0x02 28*4882a593Smuzhiyun #define ACP_POWER_OFF_IN_PROGRESS 0x03 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define ACP_ERROR_MASK 0x20000000 31*4882a593Smuzhiyun #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF 32*4882a593Smuzhiyun #define PDM_DMA_STAT 0x10 33*4882a593Smuzhiyun #define PDM_DMA_INTR_MASK 0x10000 34*4882a593Smuzhiyun #define ACP_ERROR_STAT 29 35*4882a593Smuzhiyun #define PDM_DECIMATION_FACTOR 0x2 36*4882a593Smuzhiyun #define ACP_PDM_CLK_FREQ_MASK 0x07 37*4882a593Smuzhiyun #define ACP_WOV_MISC_CTRL_MASK 0x10 38*4882a593Smuzhiyun #define ACP_PDM_ENABLE 0x01 39*4882a593Smuzhiyun #define ACP_PDM_DISABLE 0x00 40*4882a593Smuzhiyun #define ACP_PDM_DMA_EN_STATUS 0x02 41*4882a593Smuzhiyun #define TWO_CH 0x02 42*4882a593Smuzhiyun #define DELAY_US 5 43*4882a593Smuzhiyun #define ACP_COUNTER 20000 44*4882a593Smuzhiyun /* time in ms for runtime suspend delay */ 45*4882a593Smuzhiyun #define ACP_SUSPEND_DELAY_MS 2000 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define ACP_SRAM_PTE_OFFSET 0x02050000 48*4882a593Smuzhiyun #define PAGE_SIZE_4K_ENABLE 0x2 49*4882a593Smuzhiyun #define MEM_WINDOW_START 0x4000000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CAPTURE_MIN_NUM_PERIODS 4 52*4882a593Smuzhiyun #define CAPTURE_MAX_NUM_PERIODS 4 53*4882a593Smuzhiyun #define CAPTURE_MAX_PERIOD_SIZE 8192 54*4882a593Smuzhiyun #define CAPTURE_MIN_PERIOD_SIZE 4096 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS) 57*4882a593Smuzhiyun #define MIN_BUFFER MAX_BUFFER 58*4882a593Smuzhiyun #define ACP_DMIC_AUTO -1 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct pdm_dev_data { 61*4882a593Smuzhiyun u32 pdm_irq; 62*4882a593Smuzhiyun void __iomem *acp_base; 63*4882a593Smuzhiyun struct snd_pcm_substream *capture_stream; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct pdm_stream_instance { 67*4882a593Smuzhiyun u16 num_pages; 68*4882a593Smuzhiyun u16 channels; 69*4882a593Smuzhiyun dma_addr_t dma_addr; 70*4882a593Smuzhiyun u64 bytescount; 71*4882a593Smuzhiyun void __iomem *acp_base; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun union acp_pdm_dma_count { 75*4882a593Smuzhiyun struct { 76*4882a593Smuzhiyun u32 low; 77*4882a593Smuzhiyun u32 high; 78*4882a593Smuzhiyun } bcount; 79*4882a593Smuzhiyun u64 bytescount; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun rn_readl(void __iomem * base_addr)82*4882a593Smuzhiyunstatic inline u32 rn_readl(void __iomem *base_addr) 83*4882a593Smuzhiyun { 84*4882a593Smuzhiyun return readl(base_addr - ACP_PHY_BASE_ADDRESS); 85*4882a593Smuzhiyun } 86*4882a593Smuzhiyun rn_writel(u32 val,void __iomem * base_addr)87*4882a593Smuzhiyunstatic inline void rn_writel(u32 val, void __iomem *base_addr) 88*4882a593Smuzhiyun { 89*4882a593Smuzhiyun writel(val, base_addr - ACP_PHY_BASE_ADDRESS); 90*4882a593Smuzhiyun } 91