1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * AMD ACP 3.0 Register Documentation 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2016 Advanced Micro Devices, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _acp_ip_OFFSET_HEADER 9*4882a593Smuzhiyun #define _acp_ip_OFFSET_HEADER 10*4882a593Smuzhiyun // Registers from ACP_DMA block 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define mmACP_DMA_CNTL_0 0x1240000 13*4882a593Smuzhiyun #define mmACP_DMA_CNTL_1 0x1240004 14*4882a593Smuzhiyun #define mmACP_DMA_CNTL_2 0x1240008 15*4882a593Smuzhiyun #define mmACP_DMA_CNTL_3 0x124000C 16*4882a593Smuzhiyun #define mmACP_DMA_CNTL_4 0x1240010 17*4882a593Smuzhiyun #define mmACP_DMA_CNTL_5 0x1240014 18*4882a593Smuzhiyun #define mmACP_DMA_CNTL_6 0x1240018 19*4882a593Smuzhiyun #define mmACP_DMA_CNTL_7 0x124001C 20*4882a593Smuzhiyun #define mmACP_DMA_DSCR_STRT_IDX_0 0x1240020 21*4882a593Smuzhiyun #define mmACP_DMA_DSCR_STRT_IDX_1 0x1240024 22*4882a593Smuzhiyun #define mmACP_DMA_DSCR_STRT_IDX_2 0x1240028 23*4882a593Smuzhiyun #define mmACP_DMA_DSCR_STRT_IDX_3 0x124002C 24*4882a593Smuzhiyun #define mmACP_DMA_DSCR_STRT_IDX_4 0x1240030 25*4882a593Smuzhiyun #define mmACP_DMA_DSCR_STRT_IDX_5 0x1240034 26*4882a593Smuzhiyun #define mmACP_DMA_DSCR_STRT_IDX_6 0x1240038 27*4882a593Smuzhiyun #define mmACP_DMA_DSCR_STRT_IDX_7 0x124003C 28*4882a593Smuzhiyun #define mmACP_DMA_DSCR_CNT_0 0x1240040 29*4882a593Smuzhiyun #define mmACP_DMA_DSCR_CNT_1 0x1240044 30*4882a593Smuzhiyun #define mmACP_DMA_DSCR_CNT_2 0x1240048 31*4882a593Smuzhiyun #define mmACP_DMA_DSCR_CNT_3 0x124004C 32*4882a593Smuzhiyun #define mmACP_DMA_DSCR_CNT_4 0x1240050 33*4882a593Smuzhiyun #define mmACP_DMA_DSCR_CNT_5 0x1240054 34*4882a593Smuzhiyun #define mmACP_DMA_DSCR_CNT_6 0x1240058 35*4882a593Smuzhiyun #define mmACP_DMA_DSCR_CNT_7 0x124005C 36*4882a593Smuzhiyun #define mmACP_DMA_PRIO_0 0x1240060 37*4882a593Smuzhiyun #define mmACP_DMA_PRIO_1 0x1240064 38*4882a593Smuzhiyun #define mmACP_DMA_PRIO_2 0x1240068 39*4882a593Smuzhiyun #define mmACP_DMA_PRIO_3 0x124006C 40*4882a593Smuzhiyun #define mmACP_DMA_PRIO_4 0x1240070 41*4882a593Smuzhiyun #define mmACP_DMA_PRIO_5 0x1240074 42*4882a593Smuzhiyun #define mmACP_DMA_PRIO_6 0x1240078 43*4882a593Smuzhiyun #define mmACP_DMA_PRIO_7 0x124007C 44*4882a593Smuzhiyun #define mmACP_DMA_CUR_DSCR_0 0x1240080 45*4882a593Smuzhiyun #define mmACP_DMA_CUR_DSCR_1 0x1240084 46*4882a593Smuzhiyun #define mmACP_DMA_CUR_DSCR_2 0x1240088 47*4882a593Smuzhiyun #define mmACP_DMA_CUR_DSCR_3 0x124008C 48*4882a593Smuzhiyun #define mmACP_DMA_CUR_DSCR_4 0x1240090 49*4882a593Smuzhiyun #define mmACP_DMA_CUR_DSCR_5 0x1240094 50*4882a593Smuzhiyun #define mmACP_DMA_CUR_DSCR_6 0x1240098 51*4882a593Smuzhiyun #define mmACP_DMA_CUR_DSCR_7 0x124009C 52*4882a593Smuzhiyun #define mmACP_DMA_CUR_TRANS_CNT_0 0x12400A0 53*4882a593Smuzhiyun #define mmACP_DMA_CUR_TRANS_CNT_1 0x12400A4 54*4882a593Smuzhiyun #define mmACP_DMA_CUR_TRANS_CNT_2 0x12400A8 55*4882a593Smuzhiyun #define mmACP_DMA_CUR_TRANS_CNT_3 0x12400AC 56*4882a593Smuzhiyun #define mmACP_DMA_CUR_TRANS_CNT_4 0x12400B0 57*4882a593Smuzhiyun #define mmACP_DMA_CUR_TRANS_CNT_5 0x12400B4 58*4882a593Smuzhiyun #define mmACP_DMA_CUR_TRANS_CNT_6 0x12400B8 59*4882a593Smuzhiyun #define mmACP_DMA_CUR_TRANS_CNT_7 0x12400BC 60*4882a593Smuzhiyun #define mmACP_DMA_ERR_STS_0 0x12400C0 61*4882a593Smuzhiyun #define mmACP_DMA_ERR_STS_1 0x12400C4 62*4882a593Smuzhiyun #define mmACP_DMA_ERR_STS_2 0x12400C8 63*4882a593Smuzhiyun #define mmACP_DMA_ERR_STS_3 0x12400CC 64*4882a593Smuzhiyun #define mmACP_DMA_ERR_STS_4 0x12400D0 65*4882a593Smuzhiyun #define mmACP_DMA_ERR_STS_5 0x12400D4 66*4882a593Smuzhiyun #define mmACP_DMA_ERR_STS_6 0x12400D8 67*4882a593Smuzhiyun #define mmACP_DMA_ERR_STS_7 0x12400DC 68*4882a593Smuzhiyun #define mmACP_DMA_DESC_BASE_ADDR 0x12400E0 69*4882a593Smuzhiyun #define mmACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4 70*4882a593Smuzhiyun #define mmACP_DMA_CH_STS 0x12400E8 71*4882a593Smuzhiyun #define mmACP_DMA_CH_GROUP 0x12400EC 72*4882a593Smuzhiyun #define mmACP_DMA_CH_RST_STS 0x12400F0 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun // Registers from ACP_AXI2AXIATU block 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C00 78*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C04 79*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C08 80*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C 81*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C10 82*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C14 83*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C18 84*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C 85*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C20 86*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C24 87*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C28 88*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C 89*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C30 90*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C34 91*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C38 92*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C 93*4882a593Smuzhiyun #define mmACPAXI2AXI_ATU_CTRL 0x1240C40 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun // Registers from ACP_CLKRST block 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define mmACP_SOFT_RESET 0x1241000 99*4882a593Smuzhiyun #define mmACP_CONTROL 0x1241004 100*4882a593Smuzhiyun #define mmACP_STATUS 0x1241008 101*4882a593Smuzhiyun #define mmACP_DSP0_OCD_HALT_ON_RST 0x124100C 102*4882a593Smuzhiyun #define mmACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun // Registers from ACP_MISC block 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define mmACP_EXTERNAL_INTR_ENB 0x1241800 108*4882a593Smuzhiyun #define mmACP_EXTERNAL_INTR_CNTL 0x1241804 109*4882a593Smuzhiyun #define mmACP_EXTERNAL_INTR_STAT 0x1241808 110*4882a593Smuzhiyun #define mmACP_DSP0_INTR_CNTL 0x124180C 111*4882a593Smuzhiyun #define mmACP_DSP0_INTR_STAT 0x1241810 112*4882a593Smuzhiyun #define mmACP_DSP_SW_INTR_CNTL 0x1241814 113*4882a593Smuzhiyun #define mmACP_DSP_SW_INTR_STAT 0x1241818 114*4882a593Smuzhiyun #define mmACP_SW_INTR_TRIG 0x124181C 115*4882a593Smuzhiyun #define mmACP_SMU_MAILBOX 0x1241820 116*4882a593Smuzhiyun #define mmDSP_INTERRUPT_ROUTING_CTRL 0x1241824 117*4882a593Smuzhiyun #define mmACP_DSP0_WATCHDOG_TIMER_CNTL 0x1241828 118*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER1_CNTL 0x124182C 119*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER2_CNTL 0x1241830 120*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER3_CNTL 0x1241834 121*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER4_CNTL 0x1241838 122*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER5_CNTL 0x124183C 123*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER6_CNTL 0x1241840 124*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER1_CURR_VALUE 0x1241844 125*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER2_CURR_VALUE 0x1241848 126*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER3_CURR_VALUE 0x124184C 127*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER4_CURR_VALUE 0x1241850 128*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER5_CURR_VALUE 0x1241854 129*4882a593Smuzhiyun #define mmACP_DSP0_EXT_TIMER6_CURR_VALUE 0x1241858 130*4882a593Smuzhiyun #define mmACP_FW_STATUS 0x124185C 131*4882a593Smuzhiyun #define mmACP_TIMER 0x1241874 132*4882a593Smuzhiyun #define mmACP_TIMER_CNTL 0x1241878 133*4882a593Smuzhiyun #define mmACP_PGMEM_CTRL 0x12418C0 134*4882a593Smuzhiyun #define mmACP_ERROR_STATUS 0x12418C4 135*4882a593Smuzhiyun #define mmACP_SW_I2S_ERROR_REASON 0x12418C8 136*4882a593Smuzhiyun #define mmACP_MEM_PG_STS 0x12418CC 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun // Registers from ACP_PGFSM block 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define mmACP_I2S_PIN_CONFIG 0x1241400 142*4882a593Smuzhiyun #define mmACP_PAD_PULLUP_PULLDOWN_CTRL 0x1241404 143*4882a593Smuzhiyun #define mmACP_PAD_DRIVE_STRENGTH_CTRL 0x1241408 144*4882a593Smuzhiyun #define mmACP_SW_PAD_KEEPER_EN 0x124140C 145*4882a593Smuzhiyun #define mmACP_SW_WAKE_EN 0x1241410 146*4882a593Smuzhiyun #define mmACP_I2S_WAKE_EN 0x1241414 147*4882a593Smuzhiyun #define mmACP_PME_EN 0x1241418 148*4882a593Smuzhiyun #define mmACP_PGFSM_CONTROL 0x124141C 149*4882a593Smuzhiyun #define mmACP_PGFSM_STATUS 0x1241420 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun // Registers from ACP_SCRATCH block 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_0 0x1250000 155*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_1 0x1250004 156*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_2 0x1250008 157*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_3 0x125000C 158*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_4 0x1250010 159*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_5 0x1250014 160*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_6 0x1250018 161*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_7 0x125001C 162*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_8 0x1250020 163*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_9 0x1250024 164*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_10 0x1250028 165*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_11 0x125002C 166*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_12 0x1250030 167*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_13 0x1250034 168*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_14 0x1250038 169*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_15 0x125003C 170*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_16 0x1250040 171*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_17 0x1250044 172*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_18 0x1250048 173*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_19 0x125004C 174*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_20 0x1250050 175*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_21 0x1250054 176*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_22 0x1250058 177*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_23 0x125005C 178*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_24 0x1250060 179*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_25 0x1250064 180*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_26 0x1250068 181*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_27 0x125006C 182*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_28 0x1250070 183*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_29 0x1250074 184*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_30 0x1250078 185*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_31 0x125007C 186*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_32 0x1250080 187*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_33 0x1250084 188*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_34 0x1250088 189*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_35 0x125008C 190*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_36 0x1250090 191*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_37 0x1250094 192*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_38 0x1250098 193*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_39 0x125009C 194*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_40 0x12500A0 195*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_41 0x12500A4 196*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_42 0x12500A8 197*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_43 0x12500AC 198*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_44 0x12500B0 199*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_45 0x12500B4 200*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_46 0x12500B8 201*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_47 0x12500BC 202*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_48 0x12500C0 203*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_49 0x12500C4 204*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_50 0x12500C8 205*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_51 0x12500CC 206*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_52 0x12500D0 207*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_53 0x12500D4 208*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_54 0x12500D8 209*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_55 0x12500DC 210*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_56 0x12500E0 211*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_57 0x12500E4 212*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_58 0x12500E8 213*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_59 0x12500EC 214*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_60 0x12500F0 215*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_61 0x12500F4 216*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_62 0x12500F8 217*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_63 0x12500FC 218*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_64 0x1250100 219*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_65 0x1250104 220*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_66 0x1250108 221*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_67 0x125010C 222*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_68 0x1250110 223*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_69 0x1250114 224*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_70 0x1250118 225*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_71 0x125011C 226*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_72 0x1250120 227*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_73 0x1250124 228*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_74 0x1250128 229*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_75 0x125012C 230*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_76 0x1250130 231*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_77 0x1250134 232*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_78 0x1250138 233*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_79 0x125013C 234*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_80 0x1250140 235*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_81 0x1250144 236*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_82 0x1250148 237*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_83 0x125014C 238*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_84 0x1250150 239*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_85 0x1250154 240*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_86 0x1250158 241*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_87 0x125015C 242*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_88 0x1250160 243*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_89 0x1250164 244*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_90 0x1250168 245*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_91 0x125016C 246*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_92 0x1250170 247*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_93 0x1250174 248*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_94 0x1250178 249*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_95 0x125017C 250*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_96 0x1250180 251*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_97 0x1250184 252*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_98 0x1250188 253*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_99 0x125018C 254*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_100 0x1250190 255*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_101 0x1250194 256*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_102 0x1250198 257*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_103 0x125019C 258*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_104 0x12501A0 259*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_105 0x12501A4 260*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_106 0x12501A8 261*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_107 0x12501AC 262*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_108 0x12501B0 263*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_109 0x12501B4 264*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_110 0x12501B8 265*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_111 0x12501BC 266*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_112 0x12501C0 267*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_113 0x12501C4 268*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_114 0x12501C8 269*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_115 0x12501CC 270*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_116 0x12501D0 271*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_117 0x12501D4 272*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_118 0x12501D8 273*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_119 0x12501DC 274*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_120 0x12501E0 275*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_121 0x12501E4 276*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_122 0x12501E8 277*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_123 0x12501EC 278*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_124 0x12501F0 279*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_125 0x12501F4 280*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_126 0x12501F8 281*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_127 0x12501FC 282*4882a593Smuzhiyun #define mmACP_SCRATCH_REG_128 0x1250200 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun // Registers from ACP_SW_ACLK block 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun #define mmSW_CORB_Base_Address 0x1243200 288*4882a593Smuzhiyun #define mmSW_CORB_Write_Pointer 0x1243204 289*4882a593Smuzhiyun #define mmSW_CORB_Read_Pointer 0x1243208 290*4882a593Smuzhiyun #define mmSW_CORB_Control 0x124320C 291*4882a593Smuzhiyun #define mmSW_CORB_Size 0x1243214 292*4882a593Smuzhiyun #define mmSW_RIRB_Base_Address 0x1243218 293*4882a593Smuzhiyun #define mmSW_RIRB_Write_Pointer 0x124321C 294*4882a593Smuzhiyun #define mmSW_RIRB_Response_Interrupt_Count 0x1243220 295*4882a593Smuzhiyun #define mmSW_RIRB_Control 0x1243224 296*4882a593Smuzhiyun #define mmSW_RIRB_Size 0x1243228 297*4882a593Smuzhiyun #define mmSW_RIRB_FIFO_MIN_THDL 0x124322C 298*4882a593Smuzhiyun #define mmSW_imm_cmd_UPPER_WORD 0x1243230 299*4882a593Smuzhiyun #define mmSW_imm_cmd_LOWER_QWORD 0x1243234 300*4882a593Smuzhiyun #define mmSW_imm_resp_UPPER_WORD 0x1243238 301*4882a593Smuzhiyun #define mmSW_imm_resp_LOWER_QWORD 0x124323C 302*4882a593Smuzhiyun #define mmSW_imm_cmd_sts 0x1243240 303*4882a593Smuzhiyun #define mmSW_BRA_BASE_ADDRESS 0x1243244 304*4882a593Smuzhiyun #define mmSW_BRA_TRANSFER_SIZE 0x1243248 305*4882a593Smuzhiyun #define mmSW_BRA_DMA_BUSY 0x124324C 306*4882a593Smuzhiyun #define mmSW_BRA_RESP 0x1243250 307*4882a593Smuzhiyun #define mmSW_BRA_RESP_FRAME_ADDR 0x1243254 308*4882a593Smuzhiyun #define mmSW_BRA_CURRENT_TRANSFER_SIZE 0x1243258 309*4882a593Smuzhiyun #define mmSW_STATE_CHANGE_STATUS_0TO7 0x124325C 310*4882a593Smuzhiyun #define mmSW_STATE_CHANGE_STATUS_8TO11 0x1243260 311*4882a593Smuzhiyun #define mmSW_STATE_CHANGE_STATUS_MASK_0to7 0x1243264 312*4882a593Smuzhiyun #define mmSW_STATE_CHANGE_STATUS_MASK_8to11 0x1243268 313*4882a593Smuzhiyun #define mmSW_CLK_FREQUENCY_CTRL 0x124326C 314*4882a593Smuzhiyun #define mmSW_ERROR_INTR_MASK 0x1243270 315*4882a593Smuzhiyun #define mmSW_PHY_TEST_MODE_DATA_OFF 0x1243274 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun // Registers from ACP_SW_SWCLK block 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun #define mmACP_SW_EN 0x1243000 321*4882a593Smuzhiyun #define mmACP_SW_EN_STATUS 0x1243004 322*4882a593Smuzhiyun #define mmACP_SW_FRAMESIZE 0x1243008 323*4882a593Smuzhiyun #define mmACP_SW_SSP_Counter 0x124300C 324*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_EN 0x1243010 325*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_EN_STATUS 0x1243014 326*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_Frame_Format 0x1243018 327*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_SampleInterval 0x124301C 328*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_Hctrl_DP0 0x1243020 329*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_Hctrl_DP1 0x1243024 330*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_Hctrl_DP2 0x1243028 331*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_Hctrl_DP3 0x124302C 332*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_offset_DP0 0x1243030 333*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_offset_DP1 0x1243034 334*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_offset_DP2 0x1243038 335*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_offset_DP3 0x124303C 336*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_Channel_Enable_DP0 0x1243040 337*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_Channel_Enable_DP1 0x1243044 338*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_Channel_Enable_DP2 0x1243048 339*4882a593Smuzhiyun #define mmACP_SW_Audio_TX_Channel_Enable_DP3 0x124304C 340*4882a593Smuzhiyun #define mmACP_SW_BT_TX_EN 0x1243050 341*4882a593Smuzhiyun #define mmACP_SW_BT_TX_EN_STATUS 0x1243054 342*4882a593Smuzhiyun #define mmACP_SW_BT_TX_Frame_Format 0x1243058 343*4882a593Smuzhiyun #define mmACP_SW_BT_TX_SampleInterval 0x124305C 344*4882a593Smuzhiyun #define mmACP_SW_BT_TX_Hctrl 0x1243060 345*4882a593Smuzhiyun #define mmACP_SW_BT_TX_offset 0x1243064 346*4882a593Smuzhiyun #define mmACP_SW_BT_TX_Channel_Enable_DP0 0x1243068 347*4882a593Smuzhiyun #define mmACP_SW_Headset_TX_EN 0x124306C 348*4882a593Smuzhiyun #define mmACP_SW_Headset_TX_EN_STATUS 0x1243070 349*4882a593Smuzhiyun #define mmACP_SW_Headset_TX_Frame_Format 0x1243074 350*4882a593Smuzhiyun #define mmACP_SW_Headset_TX_SampleInterval 0x1243078 351*4882a593Smuzhiyun #define mmACP_SW_Headset_TX_Hctrl 0x124307C 352*4882a593Smuzhiyun #define mmACP_SW_Headset_TX_offset 0x1243080 353*4882a593Smuzhiyun #define mmACP_SW_Headset_TX_Channel_Enable_DP0 0x1243084 354*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_EN 0x1243088 355*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_EN_STATUS 0x124308C 356*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_Frame_Format 0x1243090 357*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_SampleInterval 0x1243094 358*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_Hctrl_DP0 0x1243098 359*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_Hctrl_DP1 0x124309C 360*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_Hctrl_DP2 0x1243100 361*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_Hctrl_DP3 0x1243104 362*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_offset_DP0 0x1243108 363*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_offset_DP1 0x124310C 364*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_offset_DP2 0x1243110 365*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_offset_DP3 0x1243114 366*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_Channel_Enable_DP0 0x1243118 367*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_Channel_Enable_DP1 0x124311C 368*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_Channel_Enable_DP2 0x1243120 369*4882a593Smuzhiyun #define mmACP_SW_Audio_RX_Channel_Enable_DP3 0x1243124 370*4882a593Smuzhiyun #define mmACP_SW_BT_RX_EN 0x1243128 371*4882a593Smuzhiyun #define mmACP_SW_BT_RX_EN_STATUS 0x124312C 372*4882a593Smuzhiyun #define mmACP_SW_BT_RX_Frame_Format 0x1243130 373*4882a593Smuzhiyun #define mmACP_SW_BT_RX_SampleInterval 0x1243134 374*4882a593Smuzhiyun #define mmACP_SW_BT_RX_Hctrl 0x1243138 375*4882a593Smuzhiyun #define mmACP_SW_BT_RX_offset 0x124313C 376*4882a593Smuzhiyun #define mmACP_SW_BT_RX_Channel_Enable_DP0 0x1243140 377*4882a593Smuzhiyun #define mmACP_SW_Headset_RX_EN 0x1243144 378*4882a593Smuzhiyun #define mmACP_SW_Headset_RX_EN_STATUS 0x1243148 379*4882a593Smuzhiyun #define mmACP_SW_Headset_RX_Frame_Format 0x124314C 380*4882a593Smuzhiyun #define mmACP_SW_Headset_RX_SampleInterval 0x1243150 381*4882a593Smuzhiyun #define mmACP_SW_Headset_RX_Hctrl 0x1243154 382*4882a593Smuzhiyun #define mmACP_SW_Headset_RX_offset 0x1243158 383*4882a593Smuzhiyun #define mmACP_SW_Headset_RX_Channel_Enable_DP0 0x124315C 384*4882a593Smuzhiyun #define mmACP_SW_BPT_PORT_EN 0x1243160 385*4882a593Smuzhiyun #define mmACP_SW_BPT_PORT_EN_STATUS 0x1243164 386*4882a593Smuzhiyun #define mmACP_SW_BPT_PORT_Frame_Format 0x1243168 387*4882a593Smuzhiyun #define mmACP_SW_BPT_PORT_SampleInterval 0x124316C 388*4882a593Smuzhiyun #define mmACP_SW_BPT_PORT_Hctrl 0x1243170 389*4882a593Smuzhiyun #define mmACP_SW_BPT_PORT_offset 0x1243174 390*4882a593Smuzhiyun #define mmACP_SW_BPT_PORT_Channel_Enable 0x1243178 391*4882a593Smuzhiyun #define mmACP_SW_BPT_PORT_First_byte_addr 0x124317C 392*4882a593Smuzhiyun #define mmACP_SW_CLK_RESUME_CTRL 0x1243180 393*4882a593Smuzhiyun #define mmACP_SW_CLK_RESUME_Delay_Cntr 0x1243184 394*4882a593Smuzhiyun #define mmACP_SW_BUS_RESET_CTRL 0x1243188 395*4882a593Smuzhiyun #define mmACP_SW_PRBS_ERR_STATUS 0x124318C 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun // Registers from ACP_AUDIO_BUFFERS block 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun #define mmACP_I2S_RX_RINGBUFADDR 0x1242000 401*4882a593Smuzhiyun #define mmACP_I2S_RX_RINGBUFSIZE 0x1242004 402*4882a593Smuzhiyun #define mmACP_I2S_RX_LINKPOSITIONCNTR 0x1242008 403*4882a593Smuzhiyun #define mmACP_I2S_RX_FIFOADDR 0x124200C 404*4882a593Smuzhiyun #define mmACP_I2S_RX_FIFOSIZE 0x1242010 405*4882a593Smuzhiyun #define mmACP_I2S_RX_DMA_SIZE 0x1242014 406*4882a593Smuzhiyun #define mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018 407*4882a593Smuzhiyun #define mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C 408*4882a593Smuzhiyun #define mmACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020 409*4882a593Smuzhiyun #define mmACP_I2S_TX_RINGBUFADDR 0x1242024 410*4882a593Smuzhiyun #define mmACP_I2S_TX_RINGBUFSIZE 0x1242028 411*4882a593Smuzhiyun #define mmACP_I2S_TX_LINKPOSITIONCNTR 0x124202C 412*4882a593Smuzhiyun #define mmACP_I2S_TX_FIFOADDR 0x1242030 413*4882a593Smuzhiyun #define mmACP_I2S_TX_FIFOSIZE 0x1242034 414*4882a593Smuzhiyun #define mmACP_I2S_TX_DMA_SIZE 0x1242038 415*4882a593Smuzhiyun #define mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C 416*4882a593Smuzhiyun #define mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040 417*4882a593Smuzhiyun #define mmACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044 418*4882a593Smuzhiyun #define mmACP_BT_RX_RINGBUFADDR 0x1242048 419*4882a593Smuzhiyun #define mmACP_BT_RX_RINGBUFSIZE 0x124204C 420*4882a593Smuzhiyun #define mmACP_BT_RX_LINKPOSITIONCNTR 0x1242050 421*4882a593Smuzhiyun #define mmACP_BT_RX_FIFOADDR 0x1242054 422*4882a593Smuzhiyun #define mmACP_BT_RX_FIFOSIZE 0x1242058 423*4882a593Smuzhiyun #define mmACP_BT_RX_DMA_SIZE 0x124205C 424*4882a593Smuzhiyun #define mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060 425*4882a593Smuzhiyun #define mmACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064 426*4882a593Smuzhiyun #define mmACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068 427*4882a593Smuzhiyun #define mmACP_BT_TX_RINGBUFADDR 0x124206C 428*4882a593Smuzhiyun #define mmACP_BT_TX_RINGBUFSIZE 0x1242070 429*4882a593Smuzhiyun #define mmACP_BT_TX_LINKPOSITIONCNTR 0x1242074 430*4882a593Smuzhiyun #define mmACP_BT_TX_FIFOADDR 0x1242078 431*4882a593Smuzhiyun #define mmACP_BT_TX_FIFOSIZE 0x124207C 432*4882a593Smuzhiyun #define mmACP_BT_TX_DMA_SIZE 0x1242080 433*4882a593Smuzhiyun #define mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084 434*4882a593Smuzhiyun #define mmACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088 435*4882a593Smuzhiyun #define mmACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C 436*4882a593Smuzhiyun #define mmACP_HS_RX_RINGBUFADDR 0x1242090 437*4882a593Smuzhiyun #define mmACP_HS_RX_RINGBUFSIZE 0x1242094 438*4882a593Smuzhiyun #define mmACP_HS_RX_LINKPOSITIONCNTR 0x1242098 439*4882a593Smuzhiyun #define mmACP_HS_RX_FIFOADDR 0x124209C 440*4882a593Smuzhiyun #define mmACP_HS_RX_FIFOSIZE 0x12420A0 441*4882a593Smuzhiyun #define mmACP_HS_RX_DMA_SIZE 0x12420A4 442*4882a593Smuzhiyun #define mmACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8 443*4882a593Smuzhiyun #define mmACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC 444*4882a593Smuzhiyun #define mmACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0 445*4882a593Smuzhiyun #define mmACP_HS_TX_RINGBUFADDR 0x12420B4 446*4882a593Smuzhiyun #define mmACP_HS_TX_RINGBUFSIZE 0x12420B8 447*4882a593Smuzhiyun #define mmACP_HS_TX_LINKPOSITIONCNTR 0x12420BC 448*4882a593Smuzhiyun #define mmACP_HS_TX_FIFOADDR 0x12420C0 449*4882a593Smuzhiyun #define mmACP_HS_TX_FIFOSIZE 0x12420C4 450*4882a593Smuzhiyun #define mmACP_HS_TX_DMA_SIZE 0x12420C8 451*4882a593Smuzhiyun #define mmACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC 452*4882a593Smuzhiyun #define mmACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0 453*4882a593Smuzhiyun #define mmACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun // Registers from ACP_I2S_TDM block 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun #define mmACP_I2STDM_IER 0x1242400 459*4882a593Smuzhiyun #define mmACP_I2STDM_IRER 0x1242404 460*4882a593Smuzhiyun #define mmACP_I2STDM_RXFRMT 0x1242408 461*4882a593Smuzhiyun #define mmACP_I2STDM_ITER 0x124240C 462*4882a593Smuzhiyun #define mmACP_I2STDM_TXFRMT 0x1242410 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun // Registers from ACP_BT_TDM block 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun #define mmACP_BTTDM_IER 0x1242800 468*4882a593Smuzhiyun #define mmACP_BTTDM_IRER 0x1242804 469*4882a593Smuzhiyun #define mmACP_BTTDM_RXFRMT 0x1242808 470*4882a593Smuzhiyun #define mmACP_BTTDM_ITER 0x124280C 471*4882a593Smuzhiyun #define mmACP_BTTDM_TXFRMT 0x1242810 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun // Registers from AZALIA_IP block 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun #define mmAudio_Az_Global_Capabilities 0x1200000 477*4882a593Smuzhiyun #define mmAudio_Az_Minor_Version 0x1200002 478*4882a593Smuzhiyun #define mmAudio_Az_Major_Version 0x1200003 479*4882a593Smuzhiyun #define mmAudio_Az_Output_Payload_Capability 0x1200004 480*4882a593Smuzhiyun #define mmAudio_Az_Input_Payload_Capability 0x1200006 481*4882a593Smuzhiyun #define mmAudio_Az_Global_Control 0x1200008 482*4882a593Smuzhiyun #define mmAudio_Az_Wake_Enable 0x120000C 483*4882a593Smuzhiyun #define mmAudio_Az_State_Change_Status 0x120000E 484*4882a593Smuzhiyun #define mmAudio_Az_Global_Status 0x1200010 485*4882a593Smuzhiyun #define mmAudio_Az_Linked_List_Capability_Header 0x1200014 486*4882a593Smuzhiyun #define mmAudio_Az_Output_Stream_Payload_Capability 0x1200018 487*4882a593Smuzhiyun #define mmAudio_Az_Input_Stream_Payload_Capability 0x120001A 488*4882a593Smuzhiyun #define mmAudio_Az_Interrupt_Control 0x1200020 489*4882a593Smuzhiyun #define mmAudio_Az_Interrupt_Status 0x1200024 490*4882a593Smuzhiyun #define mmAudio_Az_Wall_Clock_Counter 0x1200030 491*4882a593Smuzhiyun #define mmAudio_Az_Stream_Synchronization 0x1200038 492*4882a593Smuzhiyun #define mmAudio_Az_CORB_Lower_Base_Address 0x1200040 493*4882a593Smuzhiyun #define mmAudio_Az_CORB_Upper_Base_Address 0x1200044 494*4882a593Smuzhiyun #define mmAudio_Az_CORB_Write_Pointer 0x1200048 495*4882a593Smuzhiyun #define mmAudio_Az_CORB_Read_Pointer 0x120004A 496*4882a593Smuzhiyun #define mmAudio_Az_CORB_Control 0x120004C 497*4882a593Smuzhiyun #define mmAudio_Az_CORB_Status 0x120004D 498*4882a593Smuzhiyun #define mmAudio_Az_CORB_Size 0x120004E 499*4882a593Smuzhiyun #define mmAudio_Az_RIRB_Lower_Base_Address 0x1200050 500*4882a593Smuzhiyun #define mmAudio_Az_RIRB_Upper_Base_Address 0x1200054 501*4882a593Smuzhiyun #define mmAudio_Az_RIRB_Write_Pointer 0x1200058 502*4882a593Smuzhiyun #define mmAudio_Az_RIRB_Response_Interrupt_Count 0x120005A 503*4882a593Smuzhiyun #define mmAudio_Az_RIRB_Control 0x120005C 504*4882a593Smuzhiyun #define mmAudio_Az_RIRB_Status 0x120005D 505*4882a593Smuzhiyun #define mmAudio_Az_RIRB_Size 0x120005E 506*4882a593Smuzhiyun #define mmAudio_Az_Immediate_Command_Output_Interface 0x1200060 507*4882a593Smuzhiyun #define mmAudio_Az_Immediate_Response_Input_Interface 0x1200064 508*4882a593Smuzhiyun #define mmAudio_Az_Immediate_Command_Status 0x1200068 509*4882a593Smuzhiyun #define mmAudio_Az_DPLBASE 0x1200070 510*4882a593Smuzhiyun #define mmAudio_Az_DPUBASE 0x1200074 511*4882a593Smuzhiyun #define mmAudio_Az_Input_SD0CTL_and_STS 0x1200080 512*4882a593Smuzhiyun #define mmAudio_Az_Input_SD0LPIB 0x1200084 513*4882a593Smuzhiyun #define mmAudio_Az_Input_SD0CBL 0x1200088 514*4882a593Smuzhiyun #define mmAudio_Az_Input_SD0LVI 0x120008C 515*4882a593Smuzhiyun #define mmAudio_Az_Input_SD0FIFOS 0x1200090 516*4882a593Smuzhiyun #define mmAudio_Az_Input_SD0FMT 0x1200092 517*4882a593Smuzhiyun #define mmAudio_Az_Input_SD0BDPL 0x1200098 518*4882a593Smuzhiyun #define mmAudio_Az_Input_SD0BDPU 0x120009C 519*4882a593Smuzhiyun #define mmAudio_Az_Input_SD1CTL_and_STS 0x12000A0 520*4882a593Smuzhiyun #define mmAudio_Az_Input_SD1LPIB 0x12000A4 521*4882a593Smuzhiyun #define mmAudio_Az_Input_SD1CBL 0x12000A8 522*4882a593Smuzhiyun #define mmAudio_Az_Input_SD1LVI 0x12000AC 523*4882a593Smuzhiyun #define mmAudio_Az_Input_SD1FIFOS 0x12000B0 524*4882a593Smuzhiyun #define mmAudio_Az_Input_SD1FMT 0x12000B2 525*4882a593Smuzhiyun #define mmAudio_Az_Input_SD1BDPL 0x12000B8 526*4882a593Smuzhiyun #define mmAudio_Az_Input_SD1BDPU 0x12000BC 527*4882a593Smuzhiyun #define mmAudio_Az_Input_SD2CTL_and_STS 0x12000C0 528*4882a593Smuzhiyun #define mmAudio_Az_Input_SD2LPIB 0x12000C4 529*4882a593Smuzhiyun #define mmAudio_Az_Input_SD2CBL 0x12000C8 530*4882a593Smuzhiyun #define mmAudio_Az_Input_SD2LVI 0x12000CC 531*4882a593Smuzhiyun #define mmAudio_Az_Input_SD2FIFOS 0x12000D0 532*4882a593Smuzhiyun #define mmAudio_Az_Input_SD2FMT 0x12000D2 533*4882a593Smuzhiyun #define mmAudio_Az_Input_SD2BDPL 0x12000D8 534*4882a593Smuzhiyun #define mmAudio_Az_Input_SD2BDPU 0x12000DC 535*4882a593Smuzhiyun #define mmAudio_Az_Input_SD3CTL_and_STS 0x12000E0 536*4882a593Smuzhiyun #define mmAudio_Az_Input_SD3LPIB 0x12000E4 537*4882a593Smuzhiyun #define mmAudio_Az_Input_SD3CBL 0x12000E8 538*4882a593Smuzhiyun #define mmAudio_Az_Input_SD3LVI 0x12000EC 539*4882a593Smuzhiyun #define mmAudio_Az_Input_SD3FIFOS 0x12000F0 540*4882a593Smuzhiyun #define mmAudio_Az_Input_SD3FMT 0x12000F2 541*4882a593Smuzhiyun #define mmAudio_Az_Input_SD3BDPL 0x12000F8 542*4882a593Smuzhiyun #define mmAudio_Az_Input_SD3BDPU 0x12000FC 543*4882a593Smuzhiyun #define mmAudio_Az_Output_SD0CTL_and_STS 0x1200100 544*4882a593Smuzhiyun #define mmAudio_Az_Output_SD0LPIB 0x1200104 545*4882a593Smuzhiyun #define mmAudio_Az_Output_SD0CBL 0x1200108 546*4882a593Smuzhiyun #define mmAudio_Az_Output_SD0LVI 0x120010C 547*4882a593Smuzhiyun #define mmAudio_Az_Output_SD0FIFOS 0x1200110 548*4882a593Smuzhiyun #define mmAudio_Az_Output_SD0FMT 0x1200112 549*4882a593Smuzhiyun #define mmAudio_Az_Output_SD0BDPL 0x1200118 550*4882a593Smuzhiyun #define mmAudio_Az_Output_SD0BDPU 0x120011C 551*4882a593Smuzhiyun #define mmAudio_Az_Output_SD1CTL_and_STS 0x1200120 552*4882a593Smuzhiyun #define mmAudio_Az_Output_SD1LPIB 0x1200124 553*4882a593Smuzhiyun #define mmAudio_Az_Output_SD1CBL 0x1200128 554*4882a593Smuzhiyun #define mmAudio_Az_Output_SD1LVI 0x120012C 555*4882a593Smuzhiyun #define mmAudio_Az_Output_SD1FIFOS 0x1200130 556*4882a593Smuzhiyun #define mmAudio_Az_Output_SD1FMT 0x1200132 557*4882a593Smuzhiyun #define mmAudio_Az_Output_SD1BDPL 0x1200138 558*4882a593Smuzhiyun #define mmAudio_Az_Output_SD1BDPU 0x120013C 559*4882a593Smuzhiyun #define mmAudio_Az_Output_SD2CTL_and_STS 0x1200140 560*4882a593Smuzhiyun #define mmAudio_Az_Output_SD2LPIB 0x1200144 561*4882a593Smuzhiyun #define mmAudio_Az_Output_SD2CBL 0x1200148 562*4882a593Smuzhiyun #define mmAudio_Az_Output_SD2LVI 0x120014C 563*4882a593Smuzhiyun #define mmAudio_Az_Output_SD2FIFOS 0x1200150 564*4882a593Smuzhiyun #define mmAudio_Az_Output_SD2FMT 0x1200152 565*4882a593Smuzhiyun #define mmAudio_Az_Output_SD2BDPL 0x1200158 566*4882a593Smuzhiyun #define mmAudio_Az_Output_SD2BDPU 0x120015C 567*4882a593Smuzhiyun #define mmAudio_Az_Output_SD3CTL_and_STS 0x1200160 568*4882a593Smuzhiyun #define mmAudio_Az_Output_SD3LPIB 0x1200164 569*4882a593Smuzhiyun #define mmAudio_Az_Output_SD3CBL 0x1200168 570*4882a593Smuzhiyun #define mmAudio_Az_Output_SD3LVI 0x120016C 571*4882a593Smuzhiyun #define mmAudio_Az_Output_SD3FIFOS 0x1200170 572*4882a593Smuzhiyun #define mmAudio_Az_Output_SD3FMT 0x1200172 573*4882a593Smuzhiyun #define mmAudio_Az_Output_SD3BDPL 0x1200178 574*4882a593Smuzhiyun #define mmAudio_Az_Output_SD3BDPU 0x120017C 575*4882a593Smuzhiyun #define mmAudioAZ_Misc_Control_Register_1 0x1200180 576*4882a593Smuzhiyun #define mmAudioAZ_Misc_Control_Register_2 0x1200182 577*4882a593Smuzhiyun #define mmAudioAZ_Misc_Control_Register_3 0x1200183 578*4882a593Smuzhiyun #define mmAudio_AZ_Multiple_Links_Capability_Header 0x1200200 579*4882a593Smuzhiyun #define mmAudio_AZ_Multiple_Links_Capability_Declaration 0x1200204 580*4882a593Smuzhiyun #define mmAudio_AZ_Link0_Capabilities 0x1200240 581*4882a593Smuzhiyun #define mmAudio_AZ_Link0_Control 0x1200244 582*4882a593Smuzhiyun #define mmAudio_AZ_Link0_Output_Stream_ID 0x1200248 583*4882a593Smuzhiyun #define mmAudio_AZ_Link0_SDI_Identifier 0x120024C 584*4882a593Smuzhiyun #define mmAudio_AZ_Link0_Per_Stream_Overhead 0x1200250 585*4882a593Smuzhiyun #define mmAudio_AZ_Link0_Wall_Frame_Counter 0x1200258 586*4882a593Smuzhiyun #define mmAudio_AZ_Link0_Output_Payload_Capability_L 0x1200260 587*4882a593Smuzhiyun #define mmAudio_AZ_Link0_Output_Payload_Capability_U 0x1200264 588*4882a593Smuzhiyun #define mmAudio_AZ_Link0_Input_Payload_Capability_L 0x1200270 589*4882a593Smuzhiyun #define mmAudio_AZ_Link0_Input_Payload_Capability_U 0x1200274 590*4882a593Smuzhiyun #define mmAudio_Az_Input_SD0LICBA 0x1202084 591*4882a593Smuzhiyun #define mmAudio_Az_Input_SD1LICBA 0x12020A4 592*4882a593Smuzhiyun #define mmAudio_Az_Input_SD2LICBA 0x12020C4 593*4882a593Smuzhiyun #define mmAudio_Az_Input_SD3LICBA 0x12020E4 594*4882a593Smuzhiyun #define mmAudio_Az_Output_SD0LICBA 0x1202104 595*4882a593Smuzhiyun #define mmAudio_Az_Output_SD1LICBA 0x1202124 596*4882a593Smuzhiyun #define mmAudio_Az_Output_SD2LICBA 0x1202144 597*4882a593Smuzhiyun #define mmAudio_Az_Output_SD3LICBA 0x1202164 598*4882a593Smuzhiyun #define mmAUDIO_AZ_POWER_MANAGEMENT_CONTROL 0x1204000 599*4882a593Smuzhiyun #define mmAUDIO_AZ_IOC_SOFTRST_CONTROL 0x1204004 600*4882a593Smuzhiyun #define mmAUDIO_AZ_IOC_CLKGATE_CONTROL 0x1204008 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun 603*4882a593Smuzhiyun // Registers from ACP_AZALIA block 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun #define mmACP_AZ_PAGE0_LBASE_ADDR 0x1243800 606*4882a593Smuzhiyun #define mmACP_AZ_PAGE0_UBASE_ADDR 0x1243804 607*4882a593Smuzhiyun #define mmACP_AZ_PAGE0_PGEN_SIZE 0x1243808 608*4882a593Smuzhiyun #define mmACP_AZ_PAGE0_OFFSET 0x124380C 609*4882a593Smuzhiyun #define mmACP_AZ_PAGE1_LBASE_ADDR 0x1243810 610*4882a593Smuzhiyun #define mmACP_AZ_PAGE1_UBASE_ADDR 0x1243814 611*4882a593Smuzhiyun #define mmACP_AZ_PAGE1_PGEN_SIZE 0x1243818 612*4882a593Smuzhiyun #define mmACP_AZ_PAGE1_OFFSET 0x124381C 613*4882a593Smuzhiyun #define mmACP_AZ_PAGE2_LBASE_ADDR 0x1243820 614*4882a593Smuzhiyun #define mmACP_AZ_PAGE2_UBASE_ADDR 0x1243824 615*4882a593Smuzhiyun #define mmACP_AZ_PAGE2_PGEN_SIZE 0x1243828 616*4882a593Smuzhiyun #define mmACP_AZ_PAGE2_OFFSET 0x124382C 617*4882a593Smuzhiyun #define mmACP_AZ_PAGE3_LBASE_ADDR 0x1243830 618*4882a593Smuzhiyun #define mmACP_AZ_PAGE3_UBASE_ADDR 0x1243834 619*4882a593Smuzhiyun #define mmACP_AZ_PAGE3_PGEN_SIZE 0x1243838 620*4882a593Smuzhiyun #define mmACP_AZ_PAGE3_OFFSET 0x124383C 621*4882a593Smuzhiyun #define mmACP_AZ_PAGE4_LBASE_ADDR 0x1243840 622*4882a593Smuzhiyun #define mmACP_AZ_PAGE4_UBASE_ADDR 0x1243844 623*4882a593Smuzhiyun #define mmACP_AZ_PAGE4_PGEN_SIZE 0x1243848 624*4882a593Smuzhiyun #define mmACP_AZ_PAGE4_OFFSET 0x124384C 625*4882a593Smuzhiyun #define mmACP_AZ_PAGE5_LBASE_ADDR 0x1243850 626*4882a593Smuzhiyun #define mmACP_AZ_PAGE5_UBASE_ADDR 0x1243854 627*4882a593Smuzhiyun #define mmACP_AZ_PAGE5_PGEN_SIZE 0x1243858 628*4882a593Smuzhiyun #define mmACP_AZ_PAGE5_OFFSET 0x124385C 629*4882a593Smuzhiyun #define mmACP_AZ_PAGE6_LBASE_ADDR 0x1243860 630*4882a593Smuzhiyun #define mmACP_AZ_PAGE6_UBASE_ADDR 0x1243864 631*4882a593Smuzhiyun #define mmACP_AZ_PAGE6_PGEN_SIZE 0x1243868 632*4882a593Smuzhiyun #define mmACP_AZ_PAGE6_OFFSET 0x124386C 633*4882a593Smuzhiyun #define mmACP_AZ_PAGE7_LBASE_ADDR 0x1243870 634*4882a593Smuzhiyun #define mmACP_AZ_PAGE7_UBASE_ADDR 0x1243874 635*4882a593Smuzhiyun #define mmACP_AZ_PAGE7_PGEN_SIZE 0x1243878 636*4882a593Smuzhiyun #define mmACP_AZ_PAGE7_OFFSET 0x124387C 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun #endif 640