1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // AMD ALSA SoC PCM Driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun //Copyright 2016 Advanced Micro Devices, Inc.
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/platform_device.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <sound/pcm_params.h>
12*4882a593Smuzhiyun #include <sound/soc.h>
13*4882a593Smuzhiyun #include <sound/soc-dai.h>
14*4882a593Smuzhiyun #include <linux/dma-mapping.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "acp3x.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define DRV_NAME "acp3x_i2s_playcap"
19*4882a593Smuzhiyun
acp3x_i2s_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)20*4882a593Smuzhiyun static int acp3x_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
21*4882a593Smuzhiyun unsigned int fmt)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct i2s_dev_data *adata;
24*4882a593Smuzhiyun int mode;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun adata = snd_soc_dai_get_drvdata(cpu_dai);
27*4882a593Smuzhiyun mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
28*4882a593Smuzhiyun switch (mode) {
29*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
30*4882a593Smuzhiyun adata->tdm_mode = TDM_DISABLE;
31*4882a593Smuzhiyun break;
32*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
33*4882a593Smuzhiyun adata->tdm_mode = TDM_ENABLE;
34*4882a593Smuzhiyun break;
35*4882a593Smuzhiyun default:
36*4882a593Smuzhiyun return -EINVAL;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun return 0;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
acp3x_i2s_set_tdm_slot(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)41*4882a593Smuzhiyun static int acp3x_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
42*4882a593Smuzhiyun u32 tx_mask, u32 rx_mask, int slots, int slot_width)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct i2s_dev_data *adata;
45*4882a593Smuzhiyun u32 frm_len;
46*4882a593Smuzhiyun u16 slot_len;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun adata = snd_soc_dai_get_drvdata(cpu_dai);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* These values are as per Hardware Spec */
51*4882a593Smuzhiyun switch (slot_width) {
52*4882a593Smuzhiyun case SLOT_WIDTH_8:
53*4882a593Smuzhiyun slot_len = 8;
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun case SLOT_WIDTH_16:
56*4882a593Smuzhiyun slot_len = 16;
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun case SLOT_WIDTH_24:
59*4882a593Smuzhiyun slot_len = 24;
60*4882a593Smuzhiyun break;
61*4882a593Smuzhiyun case SLOT_WIDTH_32:
62*4882a593Smuzhiyun slot_len = 0;
63*4882a593Smuzhiyun break;
64*4882a593Smuzhiyun default:
65*4882a593Smuzhiyun return -EINVAL;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun frm_len = FRM_LEN | (slots << 15) | (slot_len << 18);
68*4882a593Smuzhiyun adata->tdm_fmt = frm_len;
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
acp3x_i2s_hwparams(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)72*4882a593Smuzhiyun static int acp3x_i2s_hwparams(struct snd_pcm_substream *substream,
73*4882a593Smuzhiyun struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun struct i2s_stream_instance *rtd;
76*4882a593Smuzhiyun struct snd_soc_pcm_runtime *prtd;
77*4882a593Smuzhiyun struct snd_soc_card *card;
78*4882a593Smuzhiyun struct acp3x_platform_info *pinfo;
79*4882a593Smuzhiyun struct i2s_dev_data *adata;
80*4882a593Smuzhiyun u32 val;
81*4882a593Smuzhiyun u32 reg_val, frmt_reg;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun prtd = asoc_substream_to_rtd(substream);
84*4882a593Smuzhiyun rtd = substream->runtime->private_data;
85*4882a593Smuzhiyun card = prtd->card;
86*4882a593Smuzhiyun adata = snd_soc_dai_get_drvdata(dai);
87*4882a593Smuzhiyun pinfo = snd_soc_card_get_drvdata(card);
88*4882a593Smuzhiyun if (pinfo) {
89*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
90*4882a593Smuzhiyun rtd->i2s_instance = pinfo->play_i2s_instance;
91*4882a593Smuzhiyun else
92*4882a593Smuzhiyun rtd->i2s_instance = pinfo->cap_i2s_instance;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* These values are as per Hardware Spec */
96*4882a593Smuzhiyun switch (params_format(params)) {
97*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_U8:
98*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S8:
99*4882a593Smuzhiyun rtd->xfer_resolution = 0x0;
100*4882a593Smuzhiyun break;
101*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S16_LE:
102*4882a593Smuzhiyun rtd->xfer_resolution = 0x02;
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S24_LE:
105*4882a593Smuzhiyun rtd->xfer_resolution = 0x04;
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S32_LE:
108*4882a593Smuzhiyun rtd->xfer_resolution = 0x05;
109*4882a593Smuzhiyun break;
110*4882a593Smuzhiyun default:
111*4882a593Smuzhiyun return -EINVAL;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
114*4882a593Smuzhiyun switch (rtd->i2s_instance) {
115*4882a593Smuzhiyun case I2S_BT_INSTANCE:
116*4882a593Smuzhiyun reg_val = mmACP_BTTDM_ITER;
117*4882a593Smuzhiyun frmt_reg = mmACP_BTTDM_TXFRMT;
118*4882a593Smuzhiyun break;
119*4882a593Smuzhiyun case I2S_SP_INSTANCE:
120*4882a593Smuzhiyun default:
121*4882a593Smuzhiyun reg_val = mmACP_I2STDM_ITER;
122*4882a593Smuzhiyun frmt_reg = mmACP_I2STDM_TXFRMT;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun } else {
125*4882a593Smuzhiyun switch (rtd->i2s_instance) {
126*4882a593Smuzhiyun case I2S_BT_INSTANCE:
127*4882a593Smuzhiyun reg_val = mmACP_BTTDM_IRER;
128*4882a593Smuzhiyun frmt_reg = mmACP_BTTDM_RXFRMT;
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun case I2S_SP_INSTANCE:
131*4882a593Smuzhiyun default:
132*4882a593Smuzhiyun reg_val = mmACP_I2STDM_IRER;
133*4882a593Smuzhiyun frmt_reg = mmACP_I2STDM_RXFRMT;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun if (adata->tdm_mode) {
137*4882a593Smuzhiyun val = rv_readl(rtd->acp3x_base + reg_val);
138*4882a593Smuzhiyun rv_writel(val | 0x2, rtd->acp3x_base + reg_val);
139*4882a593Smuzhiyun rv_writel(adata->tdm_fmt, rtd->acp3x_base + frmt_reg);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun val = rv_readl(rtd->acp3x_base + reg_val);
142*4882a593Smuzhiyun val &= ~ACP3x_ITER_IRER_SAMP_LEN_MASK;
143*4882a593Smuzhiyun val = val | (rtd->xfer_resolution << 3);
144*4882a593Smuzhiyun rv_writel(val, rtd->acp3x_base + reg_val);
145*4882a593Smuzhiyun return 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
acp3x_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)148*4882a593Smuzhiyun static int acp3x_i2s_trigger(struct snd_pcm_substream *substream,
149*4882a593Smuzhiyun int cmd, struct snd_soc_dai *dai)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun struct i2s_stream_instance *rtd;
152*4882a593Smuzhiyun u32 ret, val, period_bytes, reg_val, ier_val, water_val;
153*4882a593Smuzhiyun u32 buf_size, buf_reg;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun rtd = substream->runtime->private_data;
156*4882a593Smuzhiyun period_bytes = frames_to_bytes(substream->runtime,
157*4882a593Smuzhiyun substream->runtime->period_size);
158*4882a593Smuzhiyun buf_size = frames_to_bytes(substream->runtime,
159*4882a593Smuzhiyun substream->runtime->buffer_size);
160*4882a593Smuzhiyun switch (cmd) {
161*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
162*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
163*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
164*4882a593Smuzhiyun rtd->bytescount = acp_get_byte_count(rtd,
165*4882a593Smuzhiyun substream->stream);
166*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
167*4882a593Smuzhiyun switch (rtd->i2s_instance) {
168*4882a593Smuzhiyun case I2S_BT_INSTANCE:
169*4882a593Smuzhiyun water_val =
170*4882a593Smuzhiyun mmACP_BT_TX_INTR_WATERMARK_SIZE;
171*4882a593Smuzhiyun reg_val = mmACP_BTTDM_ITER;
172*4882a593Smuzhiyun ier_val = mmACP_BTTDM_IER;
173*4882a593Smuzhiyun buf_reg = mmACP_BT_TX_RINGBUFSIZE;
174*4882a593Smuzhiyun break;
175*4882a593Smuzhiyun case I2S_SP_INSTANCE:
176*4882a593Smuzhiyun default:
177*4882a593Smuzhiyun water_val =
178*4882a593Smuzhiyun mmACP_I2S_TX_INTR_WATERMARK_SIZE;
179*4882a593Smuzhiyun reg_val = mmACP_I2STDM_ITER;
180*4882a593Smuzhiyun ier_val = mmACP_I2STDM_IER;
181*4882a593Smuzhiyun buf_reg = mmACP_I2S_TX_RINGBUFSIZE;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun } else {
184*4882a593Smuzhiyun switch (rtd->i2s_instance) {
185*4882a593Smuzhiyun case I2S_BT_INSTANCE:
186*4882a593Smuzhiyun water_val =
187*4882a593Smuzhiyun mmACP_BT_RX_INTR_WATERMARK_SIZE;
188*4882a593Smuzhiyun reg_val = mmACP_BTTDM_IRER;
189*4882a593Smuzhiyun ier_val = mmACP_BTTDM_IER;
190*4882a593Smuzhiyun buf_reg = mmACP_BT_RX_RINGBUFSIZE;
191*4882a593Smuzhiyun break;
192*4882a593Smuzhiyun case I2S_SP_INSTANCE:
193*4882a593Smuzhiyun default:
194*4882a593Smuzhiyun water_val =
195*4882a593Smuzhiyun mmACP_I2S_RX_INTR_WATERMARK_SIZE;
196*4882a593Smuzhiyun reg_val = mmACP_I2STDM_IRER;
197*4882a593Smuzhiyun ier_val = mmACP_I2STDM_IER;
198*4882a593Smuzhiyun buf_reg = mmACP_I2S_RX_RINGBUFSIZE;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun rv_writel(period_bytes, rtd->acp3x_base + water_val);
202*4882a593Smuzhiyun rv_writel(buf_size, rtd->acp3x_base + buf_reg);
203*4882a593Smuzhiyun val = rv_readl(rtd->acp3x_base + reg_val);
204*4882a593Smuzhiyun val = val | BIT(0);
205*4882a593Smuzhiyun rv_writel(val, rtd->acp3x_base + reg_val);
206*4882a593Smuzhiyun rv_writel(1, rtd->acp3x_base + ier_val);
207*4882a593Smuzhiyun ret = 0;
208*4882a593Smuzhiyun break;
209*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
210*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
211*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
212*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
213*4882a593Smuzhiyun switch (rtd->i2s_instance) {
214*4882a593Smuzhiyun case I2S_BT_INSTANCE:
215*4882a593Smuzhiyun reg_val = mmACP_BTTDM_ITER;
216*4882a593Smuzhiyun break;
217*4882a593Smuzhiyun case I2S_SP_INSTANCE:
218*4882a593Smuzhiyun default:
219*4882a593Smuzhiyun reg_val = mmACP_I2STDM_ITER;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun } else {
223*4882a593Smuzhiyun switch (rtd->i2s_instance) {
224*4882a593Smuzhiyun case I2S_BT_INSTANCE:
225*4882a593Smuzhiyun reg_val = mmACP_BTTDM_IRER;
226*4882a593Smuzhiyun break;
227*4882a593Smuzhiyun case I2S_SP_INSTANCE:
228*4882a593Smuzhiyun default:
229*4882a593Smuzhiyun reg_val = mmACP_I2STDM_IRER;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun val = rv_readl(rtd->acp3x_base + reg_val);
233*4882a593Smuzhiyun val = val & ~BIT(0);
234*4882a593Smuzhiyun rv_writel(val, rtd->acp3x_base + reg_val);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun if (!(rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER) & BIT(0)) &&
237*4882a593Smuzhiyun !(rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER) & BIT(0)))
238*4882a593Smuzhiyun rv_writel(0, rtd->acp3x_base + mmACP_BTTDM_IER);
239*4882a593Smuzhiyun if (!(rv_readl(rtd->acp3x_base + mmACP_I2STDM_ITER) & BIT(0)) &&
240*4882a593Smuzhiyun !(rv_readl(rtd->acp3x_base + mmACP_I2STDM_IRER) & BIT(0)))
241*4882a593Smuzhiyun rv_writel(0, rtd->acp3x_base + mmACP_I2STDM_IER);
242*4882a593Smuzhiyun ret = 0;
243*4882a593Smuzhiyun break;
244*4882a593Smuzhiyun default:
245*4882a593Smuzhiyun ret = -EINVAL;
246*4882a593Smuzhiyun break;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun return ret;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static struct snd_soc_dai_ops acp3x_i2s_dai_ops = {
253*4882a593Smuzhiyun .hw_params = acp3x_i2s_hwparams,
254*4882a593Smuzhiyun .trigger = acp3x_i2s_trigger,
255*4882a593Smuzhiyun .set_fmt = acp3x_i2s_set_fmt,
256*4882a593Smuzhiyun .set_tdm_slot = acp3x_i2s_set_tdm_slot,
257*4882a593Smuzhiyun };
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun static const struct snd_soc_component_driver acp3x_dai_component = {
260*4882a593Smuzhiyun .name = DRV_NAME,
261*4882a593Smuzhiyun };
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun static struct snd_soc_dai_driver acp3x_i2s_dai = {
264*4882a593Smuzhiyun .playback = {
265*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_96000,
266*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
267*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |
268*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE,
269*4882a593Smuzhiyun .channels_min = 2,
270*4882a593Smuzhiyun .channels_max = 8,
271*4882a593Smuzhiyun .rate_min = 8000,
272*4882a593Smuzhiyun .rate_max = 96000,
273*4882a593Smuzhiyun },
274*4882a593Smuzhiyun .capture = {
275*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_48000,
276*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
277*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |
278*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE,
279*4882a593Smuzhiyun .channels_min = 2,
280*4882a593Smuzhiyun .channels_max = 2,
281*4882a593Smuzhiyun .rate_min = 8000,
282*4882a593Smuzhiyun .rate_max = 48000,
283*4882a593Smuzhiyun },
284*4882a593Smuzhiyun .ops = &acp3x_i2s_dai_ops,
285*4882a593Smuzhiyun };
286*4882a593Smuzhiyun
acp3x_dai_probe(struct platform_device * pdev)287*4882a593Smuzhiyun static int acp3x_dai_probe(struct platform_device *pdev)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun struct resource *res;
290*4882a593Smuzhiyun struct i2s_dev_data *adata;
291*4882a593Smuzhiyun int ret;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun adata = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dev_data),
294*4882a593Smuzhiyun GFP_KERNEL);
295*4882a593Smuzhiyun if (!adata)
296*4882a593Smuzhiyun return -ENOMEM;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
299*4882a593Smuzhiyun if (!res) {
300*4882a593Smuzhiyun dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
301*4882a593Smuzhiyun return -ENOMEM;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun adata->acp3x_base = devm_ioremap(&pdev->dev, res->start,
304*4882a593Smuzhiyun resource_size(res));
305*4882a593Smuzhiyun if (!adata->acp3x_base)
306*4882a593Smuzhiyun return -ENOMEM;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun adata->i2s_irq = res->start;
309*4882a593Smuzhiyun dev_set_drvdata(&pdev->dev, adata);
310*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&pdev->dev,
311*4882a593Smuzhiyun &acp3x_dai_component, &acp3x_i2s_dai, 1);
312*4882a593Smuzhiyun if (ret) {
313*4882a593Smuzhiyun dev_err(&pdev->dev, "Fail to register acp i2s dai\n");
314*4882a593Smuzhiyun return -ENODEV;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun return 0;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
acp3x_dai_remove(struct platform_device * pdev)319*4882a593Smuzhiyun static int acp3x_dai_remove(struct platform_device *pdev)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun /* As we use devm_ memory alloc there is nothing TBD here */
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun return 0;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun static struct platform_driver acp3x_dai_driver = {
327*4882a593Smuzhiyun .probe = acp3x_dai_probe,
328*4882a593Smuzhiyun .remove = acp3x_dai_remove,
329*4882a593Smuzhiyun .driver = {
330*4882a593Smuzhiyun .name = "acp3x_i2s_playcap",
331*4882a593Smuzhiyun },
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun module_platform_driver(acp3x_dai_driver);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun MODULE_AUTHOR("Vishnuvardhanrao.Ravulapati@amd.com");
337*4882a593Smuzhiyun MODULE_DESCRIPTION("AMD ACP 3.x PCM Driver");
338*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
339*4882a593Smuzhiyun MODULE_ALIAS("platform:"DRV_NAME);
340