1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for Digigram VXpocket soundcards 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __VXPOCKET_H 9*4882a593Smuzhiyun #define __VXPOCKET_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <sound/vx_core.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <pcmcia/cistpl.h> 14*4882a593Smuzhiyun #include <pcmcia/ds.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct snd_vxpocket { 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct vx_core core; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun unsigned long port; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun int mic_level; /* analog mic level (or boost) */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun unsigned int regCDSP; /* current CDSP register */ 25*4882a593Smuzhiyun unsigned int regDIALOG; /* current DIALOG register */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun int index; /* card index */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* pcmcia stuff */ 30*4882a593Smuzhiyun struct pcmcia_device *p_dev; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define to_vxpocket(x) container_of(x, struct snd_vxpocket, core) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun extern const struct snd_vx_ops snd_vxpocket_ops; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun void vx_set_mic_boost(struct vx_core *chip, int boost); 38*4882a593Smuzhiyun void vx_set_mic_level(struct vx_core *chip, int level); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun int vxp_add_mic_controls(struct vx_core *chip); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Constants used to access the CDSP register (0x08). */ 43*4882a593Smuzhiyun #define CDSP_MAGIC 0xA7 /* magic value (for read) */ 44*4882a593Smuzhiyun /* for write */ 45*4882a593Smuzhiyun #define VXP_CDSP_CLOCKIN_SEL_MASK 0x80 /* 0 (internal), 1 (AES/EBU) */ 46*4882a593Smuzhiyun #define VXP_CDSP_DATAIN_SEL_MASK 0x40 /* 0 (analog), 1 (UER) */ 47*4882a593Smuzhiyun #define VXP_CDSP_SMPTE_SEL_MASK 0x20 48*4882a593Smuzhiyun #define VXP_CDSP_RESERVED_MASK 0x10 49*4882a593Smuzhiyun #define VXP_CDSP_MIC_SEL_MASK 0x08 50*4882a593Smuzhiyun #define VXP_CDSP_VALID_IRQ_MASK 0x04 51*4882a593Smuzhiyun #define VXP_CDSP_CODEC_RESET_MASK 0x02 52*4882a593Smuzhiyun #define VXP_CDSP_DSP_RESET_MASK 0x01 53*4882a593Smuzhiyun /* VXPOCKET 240/440 */ 54*4882a593Smuzhiyun #define P24_CDSP_MICS_SEL_MASK 0x18 55*4882a593Smuzhiyun #define P24_CDSP_MIC20_SEL_MASK 0x10 56*4882a593Smuzhiyun #define P24_CDSP_MIC38_SEL_MASK 0x08 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Constants used to access the MEMIRQ register (0x0C). */ 59*4882a593Smuzhiyun #define P44_MEMIRQ_MASTER_SLAVE_SEL_MASK 0x08 60*4882a593Smuzhiyun #define P44_MEMIRQ_SYNCED_ALONE_SEL_MASK 0x04 61*4882a593Smuzhiyun #define P44_MEMIRQ_WCLK_OUT_IN_SEL_MASK 0x02 /* Not used */ 62*4882a593Smuzhiyun #define P44_MEMIRQ_WCLK_UER_SEL_MASK 0x01 /* Not used */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Micro levels (0x0C) */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Constants used to access the DIALOG register (0x0D). */ 67*4882a593Smuzhiyun #define VXP_DLG_XILINX_REPROG_MASK 0x80 /* W */ 68*4882a593Smuzhiyun #define VXP_DLG_DATA_XICOR_MASK 0x80 /* R */ 69*4882a593Smuzhiyun #define VXP_DLG_RESERVED4_0_MASK 0x40 70*4882a593Smuzhiyun #define VXP_DLG_RESERVED2_0_MASK 0x20 71*4882a593Smuzhiyun #define VXP_DLG_RESERVED1_0_MASK 0x10 72*4882a593Smuzhiyun #define VXP_DLG_DMAWRITE_SEL_MASK 0x08 /* W */ 73*4882a593Smuzhiyun #define VXP_DLG_DMAREAD_SEL_MASK 0x04 /* W */ 74*4882a593Smuzhiyun #define VXP_DLG_MEMIRQ_MASK 0x02 /* R */ 75*4882a593Smuzhiyun #define VXP_DLG_DMA16_SEL_MASK 0x02 /* W */ 76*4882a593Smuzhiyun #define VXP_DLG_ACK_MEMIRQ_MASK 0x01 /* R/W */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* __VXPOCKET_H */ 80