xref: /OK3568_Linux_fs/kernel/sound/pcmcia/pdaudiocf/pdaudiocf.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Driver for Sound Cors PDAudioCF soundcard
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2003 by Jaroslav Kysela <perex@perex.cz>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __PDAUDIOCF_H
9*4882a593Smuzhiyun #define __PDAUDIOCF_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <sound/pcm.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <pcmcia/cistpl.h>
15*4882a593Smuzhiyun #include <pcmcia/ds.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <sound/ak4117.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun /* PDAUDIOCF registers */
20*4882a593Smuzhiyun #define PDAUDIOCF_REG_MD	0x00	/* music data, R/O */
21*4882a593Smuzhiyun #define PDAUDIOCF_REG_WDP	0x02	/* write data pointer / 2, R/O */
22*4882a593Smuzhiyun #define PDAUDIOCF_REG_RDP	0x04	/* read data pointer / 2, R/O */
23*4882a593Smuzhiyun #define PDAUDIOCF_REG_TCR	0x06	/* test control register W/O */
24*4882a593Smuzhiyun #define PDAUDIOCF_REG_SCR	0x08	/* status and control, R/W (see bit description) */
25*4882a593Smuzhiyun #define PDAUDIOCF_REG_ISR	0x0a	/* interrupt status, R/O */
26*4882a593Smuzhiyun #define PDAUDIOCF_REG_IER	0x0c	/* interrupt enable, R/W */
27*4882a593Smuzhiyun #define PDAUDIOCF_REG_AK_IFR	0x0e	/* AK interface register, R/W */
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /* PDAUDIOCF_REG_TCR */
30*4882a593Smuzhiyun #define PDAUDIOCF_ELIMAKMBIT	(1<<0)	/* simulate AKM music data */
31*4882a593Smuzhiyun #define PDAUDIOCF_TESTDATASEL	(1<<1)	/* test data selection, 0 = 0x55, 1 = pseudo-random */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* PDAUDIOCF_REG_SCR */
34*4882a593Smuzhiyun #define PDAUDIOCF_AK_SBP	(1<<0)	/* serial port busy flag */
35*4882a593Smuzhiyun #define PDAUDIOCF_RST		(1<<2)	/* FPGA, AKM + SRAM buffer reset */
36*4882a593Smuzhiyun #define PDAUDIOCF_PDN		(1<<3)	/* power down bit */
37*4882a593Smuzhiyun #define PDAUDIOCF_CLKDIV0	(1<<4)	/* choose 24.576Mhz clock divided by 1,2,3 or 4 */
38*4882a593Smuzhiyun #define PDAUDIOCF_CLKDIV1	(1<<5)
39*4882a593Smuzhiyun #define PDAUDIOCF_RECORD	(1<<6)	/* start capturing to SRAM */
40*4882a593Smuzhiyun #define PDAUDIOCF_AK_SDD	(1<<7)	/* music data detected */
41*4882a593Smuzhiyun #define PDAUDIOCF_RED_LED_OFF	(1<<8)	/* red LED off override */
42*4882a593Smuzhiyun #define PDAUDIOCF_BLUE_LED_OFF	(1<<9)	/* blue LED off override */
43*4882a593Smuzhiyun #define PDAUDIOCF_DATAFMT0	(1<<10)	/* data format bits: 00 = 16-bit, 01 = 18-bit */
44*4882a593Smuzhiyun #define PDAUDIOCF_DATAFMT1	(1<<11)	/* 10 = 20-bit, 11 = 24-bit, all right justified */
45*4882a593Smuzhiyun #define PDAUDIOCF_FPGAREV(x)	((x>>12)&0x0f) /* FPGA revision */
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* PDAUDIOCF_REG_ISR */
48*4882a593Smuzhiyun #define PDAUDIOCF_IRQLVL	(1<<0)	/* Buffer level IRQ */
49*4882a593Smuzhiyun #define PDAUDIOCF_IRQOVR	(1<<1)	/* Overrun IRQ */
50*4882a593Smuzhiyun #define PDAUDIOCF_IRQAKM	(1<<2)	/* AKM IRQ */
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /* PDAUDIOCF_REG_IER */
53*4882a593Smuzhiyun #define PDAUDIOCF_IRQLVLEN0	(1<<0)	/* fill threshold levels; 00 = none, 01 = 1/8th of buffer */
54*4882a593Smuzhiyun #define PDAUDIOCF_IRQLVLEN1	(1<<1)	/* 10 = 1/4th of buffer, 11 = 1/2th of buffer */
55*4882a593Smuzhiyun #define PDAUDIOCF_IRQOVREN	(1<<2)	/* enable overrun IRQ */
56*4882a593Smuzhiyun #define PDAUDIOCF_IRQAKMEN	(1<<3)	/* enable AKM IRQ */
57*4882a593Smuzhiyun #define PDAUDIOCF_BLUEDUTY0	(1<<8)	/* blue LED duty cycle; 00 = 100%, 01 = 50% */
58*4882a593Smuzhiyun #define PDAUDIOCF_BLUEDUTY1	(1<<9)	/* 02 = 25%, 11 = 12% */
59*4882a593Smuzhiyun #define PDAUDIOCF_REDDUTY0	(1<<10)	/* red LED duty cycle; 00 = 100%, 01 = 50% */
60*4882a593Smuzhiyun #define PDAUDIOCF_REDDUTY1	(1<<11)	/* 02 = 25%, 11 = 12% */
61*4882a593Smuzhiyun #define PDAUDIOCF_BLUESDD	(1<<12)	/* blue LED against SDD bit */
62*4882a593Smuzhiyun #define PDAUDIOCF_BLUEMODULATE	(1<<13)	/* save power when 100% duty cycle selected */
63*4882a593Smuzhiyun #define PDAUDIOCF_REDMODULATE	(1<<14)	/* save power when 100% duty cycle selected */
64*4882a593Smuzhiyun #define PDAUDIOCF_HALFRATE	(1<<15)	/* slow both LED blinks by half (also spdif detect rate) */
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /* chip status */
67*4882a593Smuzhiyun #define PDAUDIOCF_STAT_IS_STALE	(1<<0)
68*4882a593Smuzhiyun #define PDAUDIOCF_STAT_IS_CONFIGURED (1<<1)
69*4882a593Smuzhiyun #define PDAUDIOCF_STAT_IS_SUSPENDED (1<<2)
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun struct snd_pdacf {
72*4882a593Smuzhiyun 	struct snd_card *card;
73*4882a593Smuzhiyun 	int index;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	unsigned long port;
76*4882a593Smuzhiyun 	int irq;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	struct mutex reg_lock;
79*4882a593Smuzhiyun 	unsigned short regmap[8];
80*4882a593Smuzhiyun 	unsigned short suspend_reg_scr;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	spinlock_t ak4117_lock;
83*4882a593Smuzhiyun 	struct ak4117 *ak4117;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	unsigned int chip_status;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	struct snd_pcm *pcm;
88*4882a593Smuzhiyun 	struct snd_pcm_substream *pcm_substream;
89*4882a593Smuzhiyun 	unsigned int pcm_running: 1;
90*4882a593Smuzhiyun 	unsigned int pcm_channels;
91*4882a593Smuzhiyun 	unsigned int pcm_swab;
92*4882a593Smuzhiyun 	unsigned int pcm_little;
93*4882a593Smuzhiyun 	unsigned int pcm_frame;
94*4882a593Smuzhiyun 	unsigned int pcm_sample;
95*4882a593Smuzhiyun 	unsigned int pcm_xor;
96*4882a593Smuzhiyun 	unsigned int pcm_size;
97*4882a593Smuzhiyun 	unsigned int pcm_period;
98*4882a593Smuzhiyun 	unsigned int pcm_tdone;
99*4882a593Smuzhiyun 	unsigned int pcm_hwptr;
100*4882a593Smuzhiyun 	void *pcm_area;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	/* pcmcia stuff */
103*4882a593Smuzhiyun 	struct pcmcia_device	*p_dev;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
pdacf_reg_write(struct snd_pdacf * chip,unsigned char reg,unsigned short val)106*4882a593Smuzhiyun static inline void pdacf_reg_write(struct snd_pdacf *chip, unsigned char reg, unsigned short val)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	outw(chip->regmap[reg>>1] = val, chip->port + reg);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
pdacf_reg_read(struct snd_pdacf * chip,unsigned char reg)111*4882a593Smuzhiyun static inline unsigned short pdacf_reg_read(struct snd_pdacf *chip, unsigned char reg)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun 	return inw(chip->port + reg);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun struct snd_pdacf *snd_pdacf_create(struct snd_card *card);
117*4882a593Smuzhiyun int snd_pdacf_ak4117_create(struct snd_pdacf *pdacf);
118*4882a593Smuzhiyun void snd_pdacf_powerdown(struct snd_pdacf *chip);
119*4882a593Smuzhiyun #ifdef CONFIG_PM
120*4882a593Smuzhiyun int snd_pdacf_suspend(struct snd_pdacf *chip);
121*4882a593Smuzhiyun int snd_pdacf_resume(struct snd_pdacf *chip);
122*4882a593Smuzhiyun #endif
123*4882a593Smuzhiyun int snd_pdacf_pcm_new(struct snd_pdacf *chip);
124*4882a593Smuzhiyun irqreturn_t pdacf_interrupt(int irq, void *dev);
125*4882a593Smuzhiyun irqreturn_t pdacf_threaded_irq(int irq, void *dev);
126*4882a593Smuzhiyun void pdacf_reinit(struct snd_pdacf *chip, int resume);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun #endif /* __PDAUDIOCF_H */
129