1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for Digigram VX222 PCI soundcards 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __VX222_H 9*4882a593Smuzhiyun #define __VX222_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <sound/vx_core.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct snd_vx222 { 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct vx_core core; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* h/w config; for PLX and for DSP */ 18*4882a593Smuzhiyun struct pci_dev *pci; 19*4882a593Smuzhiyun unsigned long port[2]; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun unsigned int regCDSP; /* current CDSP register */ 22*4882a593Smuzhiyun unsigned int regCFG; /* current CFG register */ 23*4882a593Smuzhiyun unsigned int regSELMIC; /* current SELMIC reg. (for VX222 Mic) */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun int input_level[2]; /* input level for vx222 mic */ 26*4882a593Smuzhiyun int mic_level; /* mic level for vx222 mic */ 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define to_vx222(x) container_of(x, struct snd_vx222, core) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* we use a lookup table with 148 values, see vx_mixer.c */ 32*4882a593Smuzhiyun #define VX2_AKM_LEVEL_MAX 0x93 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun extern const struct snd_vx_ops vx222_ops; 35*4882a593Smuzhiyun extern const struct snd_vx_ops vx222_old_ops; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Offset of registers with base equal to portDSP. */ 38*4882a593Smuzhiyun #define VX_RESET_DMA_REGISTER_OFFSET 0x00000008 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Constants used to access the INTCSR register. */ 41*4882a593Smuzhiyun #define VX_INTCSR_VALUE 0x00000001 42*4882a593Smuzhiyun #define VX_PCI_INTERRUPT_MASK 0x00000040 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Constants used to access the CDSP register (0x20). */ 45*4882a593Smuzhiyun #define VX_CDSP_TEST1_MASK 0x00000080 46*4882a593Smuzhiyun #define VX_CDSP_TOR1_MASK 0x00000040 47*4882a593Smuzhiyun #define VX_CDSP_TOR2_MASK 0x00000020 48*4882a593Smuzhiyun #define VX_CDSP_RESERVED0_0_MASK 0x00000010 49*4882a593Smuzhiyun #define VX_CDSP_CODEC_RESET_MASK 0x00000008 50*4882a593Smuzhiyun #define VX_CDSP_VALID_IRQ_MASK 0x00000004 51*4882a593Smuzhiyun #define VX_CDSP_TEST0_MASK 0x00000002 52*4882a593Smuzhiyun #define VX_CDSP_DSP_RESET_MASK 0x00000001 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define VX_CDSP_GPIO_OUT_MASK 0x00000060 55*4882a593Smuzhiyun #define VX_GPIO_OUT_BIT_OFFSET 5 // transform output to bit 0 and 1 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Constants used to access the CFG register (0x24). */ 58*4882a593Smuzhiyun #define VX_CFG_SYNCDSP_MASK 0x00000080 59*4882a593Smuzhiyun #define VX_CFG_RESERVED0_0_MASK 0x00000040 60*4882a593Smuzhiyun #define VX_CFG_RESERVED1_0_MASK 0x00000020 61*4882a593Smuzhiyun #define VX_CFG_RESERVED2_0_MASK 0x00000010 62*4882a593Smuzhiyun #define VX_CFG_DATAIN_SEL_MASK 0x00000008 // 0 (ana), 1 (UER) 63*4882a593Smuzhiyun #define VX_CFG_RESERVED3_0_MASK 0x00000004 64*4882a593Smuzhiyun #define VX_CFG_RESERVED4_0_MASK 0x00000002 65*4882a593Smuzhiyun #define VX_CFG_CLOCKIN_SEL_MASK 0x00000001 // 0 (internal), 1 (AES/EBU) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Constants used to access the STATUS register (0x30). */ 68*4882a593Smuzhiyun #define VX_STATUS_DATA_XICOR_MASK 0x00000080 69*4882a593Smuzhiyun #define VX_STATUS_VAL_TEST1_MASK 0x00000040 70*4882a593Smuzhiyun #define VX_STATUS_VAL_TEST0_MASK 0x00000020 71*4882a593Smuzhiyun #define VX_STATUS_RESERVED0_MASK 0x00000010 72*4882a593Smuzhiyun #define VX_STATUS_VAL_TOR1_MASK 0x00000008 73*4882a593Smuzhiyun #define VX_STATUS_VAL_TOR0_MASK 0x00000004 74*4882a593Smuzhiyun #define VX_STATUS_LEVEL_IN_MASK 0x00000002 // 6 dBu (0), 22 dBu (1) 75*4882a593Smuzhiyun #define VX_STATUS_MEMIRQ_MASK 0x00000001 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define VX_STATUS_GPIO_IN_MASK 0x0000000C 78*4882a593Smuzhiyun #define VX_GPIO_IN_BIT_OFFSET 0 // leave input as bit 2 and 3 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Constants used to access the MICRO INPUT SELECT register (0x40). */ 81*4882a593Smuzhiyun #define MICRO_SELECT_INPUT_NORM 0x00 82*4882a593Smuzhiyun #define MICRO_SELECT_INPUT_MUTE 0x01 83*4882a593Smuzhiyun #define MICRO_SELECT_INPUT_LIMIT 0x02 84*4882a593Smuzhiyun #define MICRO_SELECT_INPUT_MASK 0x03 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define MICRO_SELECT_PREAMPLI_G_0 0x00 87*4882a593Smuzhiyun #define MICRO_SELECT_PREAMPLI_G_1 0x04 88*4882a593Smuzhiyun #define MICRO_SELECT_PREAMPLI_G_2 0x08 89*4882a593Smuzhiyun #define MICRO_SELECT_PREAMPLI_G_3 0x0C 90*4882a593Smuzhiyun #define MICRO_SELECT_PREAMPLI_MASK 0x0C 91*4882a593Smuzhiyun #define MICRO_SELECT_PREAMPLI_OFFSET 2 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define MICRO_SELECT_RAISE_COMPR 0x10 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define MICRO_SELECT_NOISE_T_52DB 0x00 96*4882a593Smuzhiyun #define MICRO_SELECT_NOISE_T_42DB 0x20 97*4882a593Smuzhiyun #define MICRO_SELECT_NOISE_T_32DB 0x40 98*4882a593Smuzhiyun #define MICRO_SELECT_NOISE_T_MASK 0x60 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define MICRO_SELECT_PHANTOM_ALIM 0x80 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #endif /* __VX222_H */ 104