xref: /OK3568_Linux_fs/kernel/sound/pci/via82xx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *   ALSA driver for VIA VT82xx (South Bridge)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *   VT82C686A/B/C, VT8233A/C, VT8235
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *	Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
8*4882a593Smuzhiyun  *	                   Tjeerd.Mulder <Tjeerd.Mulder@fujitsu-siemens.com>
9*4882a593Smuzhiyun  *                    2002 Takashi Iwai <tiwai@suse.de>
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun /*
13*4882a593Smuzhiyun  * Changes:
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * Dec. 19, 2002	Takashi Iwai <tiwai@suse.de>
16*4882a593Smuzhiyun  *	- use the DSX channels for the first pcm playback.
17*4882a593Smuzhiyun  *	  (on VIA8233, 8233C and 8235 only)
18*4882a593Smuzhiyun  *	  this will allow you play simultaneously up to 4 streams.
19*4882a593Smuzhiyun  *	  multi-channel playback is assigned to the second device
20*4882a593Smuzhiyun  *	  on these chips.
21*4882a593Smuzhiyun  *	- support the secondary capture (on VIA8233/C,8235)
22*4882a593Smuzhiyun  *	- SPDIF support
23*4882a593Smuzhiyun  *	  the DSX3 channel can be used for SPDIF output.
24*4882a593Smuzhiyun  *	  on VIA8233A, this channel is assigned to the second pcm
25*4882a593Smuzhiyun  *	  playback.
26*4882a593Smuzhiyun  *	  the card config of alsa-lib will assign the correct
27*4882a593Smuzhiyun  *	  device for applications.
28*4882a593Smuzhiyun  *	- clean up the code, separate low-level initialization
29*4882a593Smuzhiyun  *	  routines for each chipset.
30*4882a593Smuzhiyun  *
31*4882a593Smuzhiyun  * Sep. 26, 2005	Karsten Wiese <annabellesgarden@yahoo.de>
32*4882a593Smuzhiyun  *	- Optimize position calculation for the 823x chips.
33*4882a593Smuzhiyun  */
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #include <linux/io.h>
36*4882a593Smuzhiyun #include <linux/delay.h>
37*4882a593Smuzhiyun #include <linux/interrupt.h>
38*4882a593Smuzhiyun #include <linux/init.h>
39*4882a593Smuzhiyun #include <linux/pci.h>
40*4882a593Smuzhiyun #include <linux/slab.h>
41*4882a593Smuzhiyun #include <linux/gameport.h>
42*4882a593Smuzhiyun #include <linux/module.h>
43*4882a593Smuzhiyun #include <sound/core.h>
44*4882a593Smuzhiyun #include <sound/pcm.h>
45*4882a593Smuzhiyun #include <sound/pcm_params.h>
46*4882a593Smuzhiyun #include <sound/info.h>
47*4882a593Smuzhiyun #include <sound/tlv.h>
48*4882a593Smuzhiyun #include <sound/ac97_codec.h>
49*4882a593Smuzhiyun #include <sound/mpu401.h>
50*4882a593Smuzhiyun #include <sound/initval.h>
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #if 0
53*4882a593Smuzhiyun #define POINTER_DEBUG
54*4882a593Smuzhiyun #endif
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
57*4882a593Smuzhiyun MODULE_DESCRIPTION("VIA VT82xx audio");
58*4882a593Smuzhiyun MODULE_LICENSE("GPL");
59*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{{VIA,VT82C686A/B/C,pci},{VIA,VT8233A/C,8235}}");
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #if IS_REACHABLE(CONFIG_GAMEPORT)
62*4882a593Smuzhiyun #define SUPPORT_JOYSTICK 1
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun static int index = SNDRV_DEFAULT_IDX1;	/* Index 0-MAX */
66*4882a593Smuzhiyun static char *id = SNDRV_DEFAULT_STR1;	/* ID for this card */
67*4882a593Smuzhiyun static long mpu_port;
68*4882a593Smuzhiyun #ifdef SUPPORT_JOYSTICK
69*4882a593Smuzhiyun static bool joystick;
70*4882a593Smuzhiyun #endif
71*4882a593Smuzhiyun static int ac97_clock = 48000;
72*4882a593Smuzhiyun static char *ac97_quirk;
73*4882a593Smuzhiyun static int dxs_support;
74*4882a593Smuzhiyun static int dxs_init_volume = 31;
75*4882a593Smuzhiyun static int nodelay;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun module_param(index, int, 0444);
78*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for VIA 82xx bridge.");
79*4882a593Smuzhiyun module_param(id, charp, 0444);
80*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for VIA 82xx bridge.");
81*4882a593Smuzhiyun module_param_hw(mpu_port, long, ioport, 0444);
82*4882a593Smuzhiyun MODULE_PARM_DESC(mpu_port, "MPU-401 port. (VT82C686x only)");
83*4882a593Smuzhiyun #ifdef SUPPORT_JOYSTICK
84*4882a593Smuzhiyun module_param(joystick, bool, 0444);
85*4882a593Smuzhiyun MODULE_PARM_DESC(joystick, "Enable joystick. (VT82C686x only)");
86*4882a593Smuzhiyun #endif
87*4882a593Smuzhiyun module_param(ac97_clock, int, 0444);
88*4882a593Smuzhiyun MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
89*4882a593Smuzhiyun module_param(ac97_quirk, charp, 0444);
90*4882a593Smuzhiyun MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
91*4882a593Smuzhiyun module_param(dxs_support, int, 0444);
92*4882a593Smuzhiyun MODULE_PARM_DESC(dxs_support, "Support for DXS channels (0 = auto, 1 = enable, 2 = disable, 3 = 48k only, 4 = no VRA, 5 = enable any sample rate)");
93*4882a593Smuzhiyun module_param(dxs_init_volume, int, 0644);
94*4882a593Smuzhiyun MODULE_PARM_DESC(dxs_init_volume, "initial DXS volume (0-31)");
95*4882a593Smuzhiyun module_param(nodelay, int, 0444);
96*4882a593Smuzhiyun MODULE_PARM_DESC(nodelay, "Disable 500ms init delay");
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /* just for backward compatibility */
99*4882a593Smuzhiyun static bool enable;
100*4882a593Smuzhiyun module_param(enable, bool, 0444);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* revision numbers for via686 */
104*4882a593Smuzhiyun #define VIA_REV_686_A		0x10
105*4882a593Smuzhiyun #define VIA_REV_686_B		0x11
106*4882a593Smuzhiyun #define VIA_REV_686_C		0x12
107*4882a593Smuzhiyun #define VIA_REV_686_D		0x13
108*4882a593Smuzhiyun #define VIA_REV_686_E		0x14
109*4882a593Smuzhiyun #define VIA_REV_686_H		0x20
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /* revision numbers for via8233 */
112*4882a593Smuzhiyun #define VIA_REV_PRE_8233	0x10	/* not in market */
113*4882a593Smuzhiyun #define VIA_REV_8233C		0x20	/* 2 rec, 4 pb, 1 multi-pb */
114*4882a593Smuzhiyun #define VIA_REV_8233		0x30	/* 2 rec, 4 pb, 1 multi-pb, spdif */
115*4882a593Smuzhiyun #define VIA_REV_8233A		0x40	/* 1 rec, 1 multi-pb, spdf */
116*4882a593Smuzhiyun #define VIA_REV_8235		0x50	/* 2 rec, 4 pb, 1 multi-pb, spdif */
117*4882a593Smuzhiyun #define VIA_REV_8237		0x60
118*4882a593Smuzhiyun #define VIA_REV_8251		0x70
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /*
121*4882a593Smuzhiyun  *  Direct registers
122*4882a593Smuzhiyun  */
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun #define VIAREG(via, x) ((via)->port + VIA_REG_##x)
125*4882a593Smuzhiyun #define VIADEV_REG(viadev, x) ((viadev)->port + VIA_REG_##x)
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun /* common offsets */
128*4882a593Smuzhiyun #define VIA_REG_OFFSET_STATUS		0x00	/* byte - channel status */
129*4882a593Smuzhiyun #define   VIA_REG_STAT_ACTIVE		0x80	/* RO */
130*4882a593Smuzhiyun #define   VIA8233_SHADOW_STAT_ACTIVE	0x08	/* RO */
131*4882a593Smuzhiyun #define   VIA_REG_STAT_PAUSED		0x40	/* RO */
132*4882a593Smuzhiyun #define   VIA_REG_STAT_TRIGGER_QUEUED	0x08	/* RO */
133*4882a593Smuzhiyun #define   VIA_REG_STAT_STOPPED		0x04	/* RWC */
134*4882a593Smuzhiyun #define   VIA_REG_STAT_EOL		0x02	/* RWC */
135*4882a593Smuzhiyun #define   VIA_REG_STAT_FLAG		0x01	/* RWC */
136*4882a593Smuzhiyun #define VIA_REG_OFFSET_CONTROL		0x01	/* byte - channel control */
137*4882a593Smuzhiyun #define   VIA_REG_CTRL_START		0x80	/* WO */
138*4882a593Smuzhiyun #define   VIA_REG_CTRL_TERMINATE	0x40	/* WO */
139*4882a593Smuzhiyun #define   VIA_REG_CTRL_AUTOSTART	0x20
140*4882a593Smuzhiyun #define   VIA_REG_CTRL_PAUSE		0x08	/* RW */
141*4882a593Smuzhiyun #define   VIA_REG_CTRL_INT_STOP		0x04
142*4882a593Smuzhiyun #define   VIA_REG_CTRL_INT_EOL		0x02
143*4882a593Smuzhiyun #define   VIA_REG_CTRL_INT_FLAG		0x01
144*4882a593Smuzhiyun #define   VIA_REG_CTRL_RESET		0x01	/* RW - probably reset? undocumented */
145*4882a593Smuzhiyun #define   VIA_REG_CTRL_INT (VIA_REG_CTRL_INT_FLAG | VIA_REG_CTRL_INT_EOL | VIA_REG_CTRL_AUTOSTART)
146*4882a593Smuzhiyun #define VIA_REG_OFFSET_TYPE		0x02	/* byte - channel type (686 only) */
147*4882a593Smuzhiyun #define   VIA_REG_TYPE_AUTOSTART	0x80	/* RW - autostart at EOL */
148*4882a593Smuzhiyun #define   VIA_REG_TYPE_16BIT		0x20	/* RW */
149*4882a593Smuzhiyun #define   VIA_REG_TYPE_STEREO		0x10	/* RW */
150*4882a593Smuzhiyun #define   VIA_REG_TYPE_INT_LLINE	0x00
151*4882a593Smuzhiyun #define   VIA_REG_TYPE_INT_LSAMPLE	0x04
152*4882a593Smuzhiyun #define   VIA_REG_TYPE_INT_LESSONE	0x08
153*4882a593Smuzhiyun #define   VIA_REG_TYPE_INT_MASK		0x0c
154*4882a593Smuzhiyun #define   VIA_REG_TYPE_INT_EOL		0x02
155*4882a593Smuzhiyun #define   VIA_REG_TYPE_INT_FLAG		0x01
156*4882a593Smuzhiyun #define VIA_REG_OFFSET_TABLE_PTR	0x04	/* dword - channel table pointer */
157*4882a593Smuzhiyun #define VIA_REG_OFFSET_CURR_PTR		0x04	/* dword - channel current pointer */
158*4882a593Smuzhiyun #define VIA_REG_OFFSET_STOP_IDX		0x08	/* dword - stop index, channel type, sample rate */
159*4882a593Smuzhiyun #define   VIA8233_REG_TYPE_16BIT	0x00200000	/* RW */
160*4882a593Smuzhiyun #define   VIA8233_REG_TYPE_STEREO	0x00100000	/* RW */
161*4882a593Smuzhiyun #define VIA_REG_OFFSET_CURR_COUNT	0x0c	/* dword - channel current count (24 bit) */
162*4882a593Smuzhiyun #define VIA_REG_OFFSET_CURR_INDEX	0x0f	/* byte - channel current index (for via8233 only) */
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun #define DEFINE_VIA_REGSET(name,val) \
165*4882a593Smuzhiyun enum {\
166*4882a593Smuzhiyun 	VIA_REG_##name##_STATUS		= (val),\
167*4882a593Smuzhiyun 	VIA_REG_##name##_CONTROL	= (val) + 0x01,\
168*4882a593Smuzhiyun 	VIA_REG_##name##_TYPE		= (val) + 0x02,\
169*4882a593Smuzhiyun 	VIA_REG_##name##_TABLE_PTR	= (val) + 0x04,\
170*4882a593Smuzhiyun 	VIA_REG_##name##_CURR_PTR	= (val) + 0x04,\
171*4882a593Smuzhiyun 	VIA_REG_##name##_STOP_IDX	= (val) + 0x08,\
172*4882a593Smuzhiyun 	VIA_REG_##name##_CURR_COUNT	= (val) + 0x0c,\
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun /* playback block */
176*4882a593Smuzhiyun DEFINE_VIA_REGSET(PLAYBACK, 0x00);
177*4882a593Smuzhiyun DEFINE_VIA_REGSET(CAPTURE, 0x10);
178*4882a593Smuzhiyun DEFINE_VIA_REGSET(FM, 0x20);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /* AC'97 */
181*4882a593Smuzhiyun #define VIA_REG_AC97			0x80	/* dword */
182*4882a593Smuzhiyun #define   VIA_REG_AC97_CODEC_ID_MASK	(3<<30)
183*4882a593Smuzhiyun #define   VIA_REG_AC97_CODEC_ID_SHIFT	30
184*4882a593Smuzhiyun #define   VIA_REG_AC97_CODEC_ID_PRIMARY	0x00
185*4882a593Smuzhiyun #define   VIA_REG_AC97_CODEC_ID_SECONDARY 0x01
186*4882a593Smuzhiyun #define   VIA_REG_AC97_SECONDARY_VALID	(1<<27)
187*4882a593Smuzhiyun #define   VIA_REG_AC97_PRIMARY_VALID	(1<<25)
188*4882a593Smuzhiyun #define   VIA_REG_AC97_BUSY		(1<<24)
189*4882a593Smuzhiyun #define   VIA_REG_AC97_READ		(1<<23)
190*4882a593Smuzhiyun #define   VIA_REG_AC97_CMD_SHIFT	16
191*4882a593Smuzhiyun #define   VIA_REG_AC97_CMD_MASK		0x7e
192*4882a593Smuzhiyun #define   VIA_REG_AC97_DATA_SHIFT	0
193*4882a593Smuzhiyun #define   VIA_REG_AC97_DATA_MASK	0xffff
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun #define VIA_REG_SGD_SHADOW		0x84	/* dword */
196*4882a593Smuzhiyun /* via686 */
197*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_PB_FLAG	(1<<0)
198*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_CP_FLAG	(1<<1)
199*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_FM_FLAG	(1<<2)
200*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_PB_EOL	(1<<4)
201*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_CP_EOL	(1<<5)
202*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_FM_EOL	(1<<6)
203*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_PB_STOP	(1<<8)
204*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_CP_STOP	(1<<9)
205*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_FM_STOP	(1<<10)
206*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_PB_ACTIVE	(1<<12)
207*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_CP_ACTIVE	(1<<13)
208*4882a593Smuzhiyun #define   VIA_REG_SGD_STAT_FM_ACTIVE	(1<<14)
209*4882a593Smuzhiyun /* via8233 */
210*4882a593Smuzhiyun #define   VIA8233_REG_SGD_STAT_FLAG	(1<<0)
211*4882a593Smuzhiyun #define   VIA8233_REG_SGD_STAT_EOL	(1<<1)
212*4882a593Smuzhiyun #define   VIA8233_REG_SGD_STAT_STOP	(1<<2)
213*4882a593Smuzhiyun #define   VIA8233_REG_SGD_STAT_ACTIVE	(1<<3)
214*4882a593Smuzhiyun #define VIA8233_INTR_MASK(chan) ((VIA8233_REG_SGD_STAT_FLAG|VIA8233_REG_SGD_STAT_EOL) << ((chan) * 4))
215*4882a593Smuzhiyun #define   VIA8233_REG_SGD_CHAN_SDX	0
216*4882a593Smuzhiyun #define   VIA8233_REG_SGD_CHAN_MULTI	4
217*4882a593Smuzhiyun #define   VIA8233_REG_SGD_CHAN_REC	6
218*4882a593Smuzhiyun #define   VIA8233_REG_SGD_CHAN_REC1	7
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun #define VIA_REG_GPI_STATUS		0x88
221*4882a593Smuzhiyun #define VIA_REG_GPI_INTR		0x8c
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun /* multi-channel and capture registers for via8233 */
224*4882a593Smuzhiyun DEFINE_VIA_REGSET(MULTPLAY, 0x40);
225*4882a593Smuzhiyun DEFINE_VIA_REGSET(CAPTURE_8233, 0x60);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun /* via8233-specific registers */
228*4882a593Smuzhiyun #define VIA_REG_OFS_PLAYBACK_VOLUME_L	0x02	/* byte */
229*4882a593Smuzhiyun #define VIA_REG_OFS_PLAYBACK_VOLUME_R	0x03	/* byte */
230*4882a593Smuzhiyun #define VIA_REG_OFS_MULTPLAY_FORMAT	0x02	/* byte - format and channels */
231*4882a593Smuzhiyun #define   VIA_REG_MULTPLAY_FMT_8BIT	0x00
232*4882a593Smuzhiyun #define   VIA_REG_MULTPLAY_FMT_16BIT	0x80
233*4882a593Smuzhiyun #define   VIA_REG_MULTPLAY_FMT_CH_MASK	0x70	/* # channels << 4 (valid = 1,2,4,6) */
234*4882a593Smuzhiyun #define VIA_REG_OFS_CAPTURE_FIFO	0x02	/* byte - bit 6 = fifo  enable */
235*4882a593Smuzhiyun #define   VIA_REG_CAPTURE_FIFO_ENABLE	0x40
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun #define VIA_DXS_MAX_VOLUME		31	/* max. volume (attenuation) of reg 0x32/33 */
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun #define VIA_REG_CAPTURE_CHANNEL		0x63	/* byte - input select */
240*4882a593Smuzhiyun #define   VIA_REG_CAPTURE_CHANNEL_MIC	0x4
241*4882a593Smuzhiyun #define   VIA_REG_CAPTURE_CHANNEL_LINE	0
242*4882a593Smuzhiyun #define   VIA_REG_CAPTURE_SELECT_CODEC	0x03	/* recording source codec (0 = primary) */
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun #define VIA_TBL_BIT_FLAG	0x40000000
245*4882a593Smuzhiyun #define VIA_TBL_BIT_EOL		0x80000000
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun /* pci space */
248*4882a593Smuzhiyun #define VIA_ACLINK_STAT		0x40
249*4882a593Smuzhiyun #define  VIA_ACLINK_C11_READY	0x20
250*4882a593Smuzhiyun #define  VIA_ACLINK_C10_READY	0x10
251*4882a593Smuzhiyun #define  VIA_ACLINK_C01_READY	0x04 /* secondary codec ready */
252*4882a593Smuzhiyun #define  VIA_ACLINK_LOWPOWER	0x02 /* low-power state */
253*4882a593Smuzhiyun #define  VIA_ACLINK_C00_READY	0x01 /* primary codec ready */
254*4882a593Smuzhiyun #define VIA_ACLINK_CTRL		0x41
255*4882a593Smuzhiyun #define  VIA_ACLINK_CTRL_ENABLE	0x80 /* 0: disable, 1: enable */
256*4882a593Smuzhiyun #define  VIA_ACLINK_CTRL_RESET	0x40 /* 0: assert, 1: de-assert */
257*4882a593Smuzhiyun #define  VIA_ACLINK_CTRL_SYNC	0x20 /* 0: release SYNC, 1: force SYNC hi */
258*4882a593Smuzhiyun #define  VIA_ACLINK_CTRL_SDO	0x10 /* 0: release SDO, 1: force SDO hi */
259*4882a593Smuzhiyun #define  VIA_ACLINK_CTRL_VRA	0x08 /* 0: disable VRA, 1: enable VRA */
260*4882a593Smuzhiyun #define  VIA_ACLINK_CTRL_PCM	0x04 /* 0: disable PCM, 1: enable PCM */
261*4882a593Smuzhiyun #define  VIA_ACLINK_CTRL_FM	0x02 /* via686 only */
262*4882a593Smuzhiyun #define  VIA_ACLINK_CTRL_SB	0x01 /* via686 only */
263*4882a593Smuzhiyun #define  VIA_ACLINK_CTRL_INIT	(VIA_ACLINK_CTRL_ENABLE|\
264*4882a593Smuzhiyun 				 VIA_ACLINK_CTRL_RESET|\
265*4882a593Smuzhiyun 				 VIA_ACLINK_CTRL_PCM|\
266*4882a593Smuzhiyun 				 VIA_ACLINK_CTRL_VRA)
267*4882a593Smuzhiyun #define VIA_FUNC_ENABLE		0x42
268*4882a593Smuzhiyun #define  VIA_FUNC_MIDI_PNP	0x80 /* FIXME: it's 0x40 in the datasheet! */
269*4882a593Smuzhiyun #define  VIA_FUNC_MIDI_IRQMASK	0x40 /* FIXME: not documented! */
270*4882a593Smuzhiyun #define  VIA_FUNC_RX2C_WRITE	0x20
271*4882a593Smuzhiyun #define  VIA_FUNC_SB_FIFO_EMPTY	0x10
272*4882a593Smuzhiyun #define  VIA_FUNC_ENABLE_GAME	0x08
273*4882a593Smuzhiyun #define  VIA_FUNC_ENABLE_FM	0x04
274*4882a593Smuzhiyun #define  VIA_FUNC_ENABLE_MIDI	0x02
275*4882a593Smuzhiyun #define  VIA_FUNC_ENABLE_SB	0x01
276*4882a593Smuzhiyun #define VIA_PNP_CONTROL		0x43
277*4882a593Smuzhiyun #define VIA_FM_NMI_CTRL		0x48
278*4882a593Smuzhiyun #define VIA8233_VOLCHG_CTRL	0x48
279*4882a593Smuzhiyun #define VIA8233_SPDIF_CTRL	0x49
280*4882a593Smuzhiyun #define  VIA8233_SPDIF_DX3	0x08
281*4882a593Smuzhiyun #define  VIA8233_SPDIF_SLOT_MASK	0x03
282*4882a593Smuzhiyun #define  VIA8233_SPDIF_SLOT_1011	0x00
283*4882a593Smuzhiyun #define  VIA8233_SPDIF_SLOT_34		0x01
284*4882a593Smuzhiyun #define  VIA8233_SPDIF_SLOT_78		0x02
285*4882a593Smuzhiyun #define  VIA8233_SPDIF_SLOT_69		0x03
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun /*
288*4882a593Smuzhiyun  */
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun #define VIA_DXS_AUTO	0
291*4882a593Smuzhiyun #define VIA_DXS_ENABLE	1
292*4882a593Smuzhiyun #define VIA_DXS_DISABLE	2
293*4882a593Smuzhiyun #define VIA_DXS_48K	3
294*4882a593Smuzhiyun #define VIA_DXS_NO_VRA	4
295*4882a593Smuzhiyun #define VIA_DXS_SRC	5
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun /*
299*4882a593Smuzhiyun  * pcm stream
300*4882a593Smuzhiyun  */
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun struct snd_via_sg_table {
303*4882a593Smuzhiyun 	unsigned int offset;
304*4882a593Smuzhiyun 	unsigned int size;
305*4882a593Smuzhiyun } ;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun #define VIA_TABLE_SIZE	255
308*4882a593Smuzhiyun #define VIA_MAX_BUFSIZE	(1<<24)
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun struct viadev {
311*4882a593Smuzhiyun 	unsigned int reg_offset;
312*4882a593Smuzhiyun 	unsigned long port;
313*4882a593Smuzhiyun 	int direction;	/* playback = 0, capture = 1 */
314*4882a593Smuzhiyun         struct snd_pcm_substream *substream;
315*4882a593Smuzhiyun 	int running;
316*4882a593Smuzhiyun 	unsigned int tbl_entries; /* # descriptors */
317*4882a593Smuzhiyun 	struct snd_dma_buffer table;
318*4882a593Smuzhiyun 	struct snd_via_sg_table *idx_table;
319*4882a593Smuzhiyun 	/* for recovery from the unexpected pointer */
320*4882a593Smuzhiyun 	unsigned int lastpos;
321*4882a593Smuzhiyun 	unsigned int fragsize;
322*4882a593Smuzhiyun 	unsigned int bufsize;
323*4882a593Smuzhiyun 	unsigned int bufsize2;
324*4882a593Smuzhiyun 	int hwptr_done;		/* processed frame position in the buffer */
325*4882a593Smuzhiyun 	int in_interrupt;
326*4882a593Smuzhiyun 	int shadow_shift;
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun enum { TYPE_CARD_VIA686 = 1, TYPE_CARD_VIA8233 };
331*4882a593Smuzhiyun enum { TYPE_VIA686, TYPE_VIA8233, TYPE_VIA8233A };
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun #define VIA_MAX_DEVS	7	/* 4 playback, 1 multi, 2 capture */
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun struct via_rate_lock {
336*4882a593Smuzhiyun 	spinlock_t lock;
337*4882a593Smuzhiyun 	int rate;
338*4882a593Smuzhiyun 	int used;
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun struct via82xx {
342*4882a593Smuzhiyun 	int irq;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	unsigned long port;
345*4882a593Smuzhiyun 	struct resource *mpu_res;
346*4882a593Smuzhiyun 	int chip_type;
347*4882a593Smuzhiyun 	unsigned char revision;
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	unsigned char old_legacy;
350*4882a593Smuzhiyun 	unsigned char old_legacy_cfg;
351*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
352*4882a593Smuzhiyun 	unsigned char legacy_saved;
353*4882a593Smuzhiyun 	unsigned char legacy_cfg_saved;
354*4882a593Smuzhiyun 	unsigned char spdif_ctrl_saved;
355*4882a593Smuzhiyun 	unsigned char capture_src_saved[2];
356*4882a593Smuzhiyun 	unsigned int mpu_port_saved;
357*4882a593Smuzhiyun #endif
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	unsigned char playback_volume[4][2]; /* for VIA8233/C/8235; default = 0 */
360*4882a593Smuzhiyun 	unsigned char playback_volume_c[2]; /* for VIA8233/C/8235; default = 0 */
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	unsigned int intr_mask; /* SGD_SHADOW mask to check interrupts */
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	struct pci_dev *pci;
365*4882a593Smuzhiyun 	struct snd_card *card;
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	unsigned int num_devs;
368*4882a593Smuzhiyun 	unsigned int playback_devno, multi_devno, capture_devno;
369*4882a593Smuzhiyun 	struct viadev devs[VIA_MAX_DEVS];
370*4882a593Smuzhiyun 	struct via_rate_lock rates[2]; /* playback and capture */
371*4882a593Smuzhiyun 	unsigned int dxs_fixed: 1;	/* DXS channel accepts only 48kHz */
372*4882a593Smuzhiyun 	unsigned int no_vra: 1;		/* no need to set VRA on DXS channels */
373*4882a593Smuzhiyun 	unsigned int dxs_src: 1;	/* use full SRC capabilities of DXS */
374*4882a593Smuzhiyun 	unsigned int spdif_on: 1;	/* only spdif rates work to external DACs */
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	struct snd_pcm *pcms[2];
377*4882a593Smuzhiyun 	struct snd_rawmidi *rmidi;
378*4882a593Smuzhiyun 	struct snd_kcontrol *dxs_controls[4];
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	struct snd_ac97_bus *ac97_bus;
381*4882a593Smuzhiyun 	struct snd_ac97 *ac97;
382*4882a593Smuzhiyun 	unsigned int ac97_clock;
383*4882a593Smuzhiyun 	unsigned int ac97_secondary;	/* secondary AC'97 codec is present */
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	spinlock_t reg_lock;
386*4882a593Smuzhiyun 	struct snd_info_entry *proc_entry;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun #ifdef SUPPORT_JOYSTICK
389*4882a593Smuzhiyun 	struct gameport *gameport;
390*4882a593Smuzhiyun #endif
391*4882a593Smuzhiyun };
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun static const struct pci_device_id snd_via82xx_ids[] = {
394*4882a593Smuzhiyun 	/* 0x1106, 0x3058 */
395*4882a593Smuzhiyun 	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C686_5), TYPE_CARD_VIA686, },	/* 686A */
396*4882a593Smuzhiyun 	/* 0x1106, 0x3059 */
397*4882a593Smuzhiyun 	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_8233_5), TYPE_CARD_VIA8233, },	/* VT8233 */
398*4882a593Smuzhiyun 	{ 0, }
399*4882a593Smuzhiyun };
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, snd_via82xx_ids);
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun /*
404*4882a593Smuzhiyun  */
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun /*
407*4882a593Smuzhiyun  * allocate and initialize the descriptor buffers
408*4882a593Smuzhiyun  * periods = number of periods
409*4882a593Smuzhiyun  * fragsize = period size in bytes
410*4882a593Smuzhiyun  */
build_via_table(struct viadev * dev,struct snd_pcm_substream * substream,struct pci_dev * pci,unsigned int periods,unsigned int fragsize)411*4882a593Smuzhiyun static int build_via_table(struct viadev *dev, struct snd_pcm_substream *substream,
412*4882a593Smuzhiyun 			   struct pci_dev *pci,
413*4882a593Smuzhiyun 			   unsigned int periods, unsigned int fragsize)
414*4882a593Smuzhiyun {
415*4882a593Smuzhiyun 	unsigned int i, idx, ofs, rest;
416*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
417*4882a593Smuzhiyun 	__le32 *pgtbl;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	if (dev->table.area == NULL) {
420*4882a593Smuzhiyun 		/* the start of each lists must be aligned to 8 bytes,
421*4882a593Smuzhiyun 		 * but the kernel pages are much bigger, so we don't care
422*4882a593Smuzhiyun 		 */
423*4882a593Smuzhiyun 		if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
424*4882a593Smuzhiyun 					PAGE_ALIGN(VIA_TABLE_SIZE * 2 * 8),
425*4882a593Smuzhiyun 					&dev->table) < 0)
426*4882a593Smuzhiyun 			return -ENOMEM;
427*4882a593Smuzhiyun 	}
428*4882a593Smuzhiyun 	if (! dev->idx_table) {
429*4882a593Smuzhiyun 		dev->idx_table = kmalloc_array(VIA_TABLE_SIZE,
430*4882a593Smuzhiyun 					       sizeof(*dev->idx_table),
431*4882a593Smuzhiyun 					       GFP_KERNEL);
432*4882a593Smuzhiyun 		if (! dev->idx_table)
433*4882a593Smuzhiyun 			return -ENOMEM;
434*4882a593Smuzhiyun 	}
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	/* fill the entries */
437*4882a593Smuzhiyun 	idx = 0;
438*4882a593Smuzhiyun 	ofs = 0;
439*4882a593Smuzhiyun 	pgtbl = (__le32 *)dev->table.area;
440*4882a593Smuzhiyun 	for (i = 0; i < periods; i++) {
441*4882a593Smuzhiyun 		rest = fragsize;
442*4882a593Smuzhiyun 		/* fill descriptors for a period.
443*4882a593Smuzhiyun 		 * a period can be split to several descriptors if it's
444*4882a593Smuzhiyun 		 * over page boundary.
445*4882a593Smuzhiyun 		 */
446*4882a593Smuzhiyun 		do {
447*4882a593Smuzhiyun 			unsigned int r;
448*4882a593Smuzhiyun 			unsigned int flag;
449*4882a593Smuzhiyun 			unsigned int addr;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 			if (idx >= VIA_TABLE_SIZE) {
452*4882a593Smuzhiyun 				dev_err(&pci->dev, "too much table size!\n");
453*4882a593Smuzhiyun 				return -EINVAL;
454*4882a593Smuzhiyun 			}
455*4882a593Smuzhiyun 			addr = snd_pcm_sgbuf_get_addr(substream, ofs);
456*4882a593Smuzhiyun 			pgtbl[idx << 1] = cpu_to_le32(addr);
457*4882a593Smuzhiyun 			r = snd_pcm_sgbuf_get_chunk_size(substream, ofs, rest);
458*4882a593Smuzhiyun 			rest -= r;
459*4882a593Smuzhiyun 			if (! rest) {
460*4882a593Smuzhiyun 				if (i == periods - 1)
461*4882a593Smuzhiyun 					flag = VIA_TBL_BIT_EOL; /* buffer boundary */
462*4882a593Smuzhiyun 				else
463*4882a593Smuzhiyun 					flag = VIA_TBL_BIT_FLAG; /* period boundary */
464*4882a593Smuzhiyun 			} else
465*4882a593Smuzhiyun 				flag = 0; /* period continues to the next */
466*4882a593Smuzhiyun 			/*
467*4882a593Smuzhiyun 			dev_dbg(&pci->dev,
468*4882a593Smuzhiyun 				"tbl %d: at %d  size %d (rest %d)\n",
469*4882a593Smuzhiyun 				idx, ofs, r, rest);
470*4882a593Smuzhiyun 			*/
471*4882a593Smuzhiyun 			pgtbl[(idx<<1) + 1] = cpu_to_le32(r | flag);
472*4882a593Smuzhiyun 			dev->idx_table[idx].offset = ofs;
473*4882a593Smuzhiyun 			dev->idx_table[idx].size = r;
474*4882a593Smuzhiyun 			ofs += r;
475*4882a593Smuzhiyun 			idx++;
476*4882a593Smuzhiyun 		} while (rest > 0);
477*4882a593Smuzhiyun 	}
478*4882a593Smuzhiyun 	dev->tbl_entries = idx;
479*4882a593Smuzhiyun 	dev->bufsize = periods * fragsize;
480*4882a593Smuzhiyun 	dev->bufsize2 = dev->bufsize / 2;
481*4882a593Smuzhiyun 	dev->fragsize = fragsize;
482*4882a593Smuzhiyun 	return 0;
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 
clean_via_table(struct viadev * dev,struct snd_pcm_substream * substream,struct pci_dev * pci)486*4882a593Smuzhiyun static int clean_via_table(struct viadev *dev, struct snd_pcm_substream *substream,
487*4882a593Smuzhiyun 			   struct pci_dev *pci)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun 	if (dev->table.area) {
490*4882a593Smuzhiyun 		snd_dma_free_pages(&dev->table);
491*4882a593Smuzhiyun 		dev->table.area = NULL;
492*4882a593Smuzhiyun 	}
493*4882a593Smuzhiyun 	kfree(dev->idx_table);
494*4882a593Smuzhiyun 	dev->idx_table = NULL;
495*4882a593Smuzhiyun 	return 0;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun /*
499*4882a593Smuzhiyun  *  Basic I/O
500*4882a593Smuzhiyun  */
501*4882a593Smuzhiyun 
snd_via82xx_codec_xread(struct via82xx * chip)502*4882a593Smuzhiyun static inline unsigned int snd_via82xx_codec_xread(struct via82xx *chip)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun 	return inl(VIAREG(chip, AC97));
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun 
snd_via82xx_codec_xwrite(struct via82xx * chip,unsigned int val)507*4882a593Smuzhiyun static inline void snd_via82xx_codec_xwrite(struct via82xx *chip, unsigned int val)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun 	outl(val, VIAREG(chip, AC97));
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun 
snd_via82xx_codec_ready(struct via82xx * chip,int secondary)512*4882a593Smuzhiyun static int snd_via82xx_codec_ready(struct via82xx *chip, int secondary)
513*4882a593Smuzhiyun {
514*4882a593Smuzhiyun 	unsigned int timeout = 1000;	/* 1ms */
515*4882a593Smuzhiyun 	unsigned int val;
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun 	while (timeout-- > 0) {
518*4882a593Smuzhiyun 		udelay(1);
519*4882a593Smuzhiyun 		if (!((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY))
520*4882a593Smuzhiyun 			return val & 0xffff;
521*4882a593Smuzhiyun 	}
522*4882a593Smuzhiyun 	dev_err(chip->card->dev, "codec_ready: codec %i is not ready [0x%x]\n",
523*4882a593Smuzhiyun 		   secondary, snd_via82xx_codec_xread(chip));
524*4882a593Smuzhiyun 	return -EIO;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun 
snd_via82xx_codec_valid(struct via82xx * chip,int secondary)527*4882a593Smuzhiyun static int snd_via82xx_codec_valid(struct via82xx *chip, int secondary)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun 	unsigned int timeout = 1000;	/* 1ms */
530*4882a593Smuzhiyun 	unsigned int val, val1;
531*4882a593Smuzhiyun 	unsigned int stat = !secondary ? VIA_REG_AC97_PRIMARY_VALID :
532*4882a593Smuzhiyun 					 VIA_REG_AC97_SECONDARY_VALID;
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	while (timeout-- > 0) {
535*4882a593Smuzhiyun 		val = snd_via82xx_codec_xread(chip);
536*4882a593Smuzhiyun 		val1 = val & (VIA_REG_AC97_BUSY | stat);
537*4882a593Smuzhiyun 		if (val1 == stat)
538*4882a593Smuzhiyun 			return val & 0xffff;
539*4882a593Smuzhiyun 		udelay(1);
540*4882a593Smuzhiyun 	}
541*4882a593Smuzhiyun 	return -EIO;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun 
snd_via82xx_codec_wait(struct snd_ac97 * ac97)544*4882a593Smuzhiyun static void snd_via82xx_codec_wait(struct snd_ac97 *ac97)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun 	struct via82xx *chip = ac97->private_data;
547*4882a593Smuzhiyun 	__always_unused int err;
548*4882a593Smuzhiyun 	err = snd_via82xx_codec_ready(chip, ac97->num);
549*4882a593Smuzhiyun 	/* here we need to wait fairly for long time.. */
550*4882a593Smuzhiyun 	if (!nodelay)
551*4882a593Smuzhiyun 		msleep(500);
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun 
snd_via82xx_codec_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)554*4882a593Smuzhiyun static void snd_via82xx_codec_write(struct snd_ac97 *ac97,
555*4882a593Smuzhiyun 				    unsigned short reg,
556*4882a593Smuzhiyun 				    unsigned short val)
557*4882a593Smuzhiyun {
558*4882a593Smuzhiyun 	struct via82xx *chip = ac97->private_data;
559*4882a593Smuzhiyun 	unsigned int xval;
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	xval = !ac97->num ? VIA_REG_AC97_CODEC_ID_PRIMARY : VIA_REG_AC97_CODEC_ID_SECONDARY;
562*4882a593Smuzhiyun 	xval <<= VIA_REG_AC97_CODEC_ID_SHIFT;
563*4882a593Smuzhiyun 	xval |= reg << VIA_REG_AC97_CMD_SHIFT;
564*4882a593Smuzhiyun 	xval |= val << VIA_REG_AC97_DATA_SHIFT;
565*4882a593Smuzhiyun 	snd_via82xx_codec_xwrite(chip, xval);
566*4882a593Smuzhiyun 	snd_via82xx_codec_ready(chip, ac97->num);
567*4882a593Smuzhiyun }
568*4882a593Smuzhiyun 
snd_via82xx_codec_read(struct snd_ac97 * ac97,unsigned short reg)569*4882a593Smuzhiyun static unsigned short snd_via82xx_codec_read(struct snd_ac97 *ac97, unsigned short reg)
570*4882a593Smuzhiyun {
571*4882a593Smuzhiyun 	struct via82xx *chip = ac97->private_data;
572*4882a593Smuzhiyun 	unsigned int xval, val = 0xffff;
573*4882a593Smuzhiyun 	int again = 0;
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	xval = ac97->num << VIA_REG_AC97_CODEC_ID_SHIFT;
576*4882a593Smuzhiyun 	xval |= ac97->num ? VIA_REG_AC97_SECONDARY_VALID : VIA_REG_AC97_PRIMARY_VALID;
577*4882a593Smuzhiyun 	xval |= VIA_REG_AC97_READ;
578*4882a593Smuzhiyun 	xval |= (reg & 0x7f) << VIA_REG_AC97_CMD_SHIFT;
579*4882a593Smuzhiyun       	while (1) {
580*4882a593Smuzhiyun       		if (again++ > 3) {
581*4882a593Smuzhiyun 			dev_err(chip->card->dev,
582*4882a593Smuzhiyun 				"codec_read: codec %i is not valid [0x%x]\n",
583*4882a593Smuzhiyun 				   ac97->num, snd_via82xx_codec_xread(chip));
584*4882a593Smuzhiyun 		      	return 0xffff;
585*4882a593Smuzhiyun 		}
586*4882a593Smuzhiyun 		snd_via82xx_codec_xwrite(chip, xval);
587*4882a593Smuzhiyun 		udelay (20);
588*4882a593Smuzhiyun 		if (snd_via82xx_codec_valid(chip, ac97->num) >= 0) {
589*4882a593Smuzhiyun 			udelay(25);
590*4882a593Smuzhiyun 			val = snd_via82xx_codec_xread(chip);
591*4882a593Smuzhiyun 			break;
592*4882a593Smuzhiyun 		}
593*4882a593Smuzhiyun 	}
594*4882a593Smuzhiyun 	return val & 0xffff;
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun 
snd_via82xx_channel_reset(struct via82xx * chip,struct viadev * viadev)597*4882a593Smuzhiyun static void snd_via82xx_channel_reset(struct via82xx *chip, struct viadev *viadev)
598*4882a593Smuzhiyun {
599*4882a593Smuzhiyun 	outb(VIA_REG_CTRL_PAUSE | VIA_REG_CTRL_TERMINATE | VIA_REG_CTRL_RESET,
600*4882a593Smuzhiyun 	     VIADEV_REG(viadev, OFFSET_CONTROL));
601*4882a593Smuzhiyun 	inb(VIADEV_REG(viadev, OFFSET_CONTROL));
602*4882a593Smuzhiyun 	udelay(50);
603*4882a593Smuzhiyun 	/* disable interrupts */
604*4882a593Smuzhiyun 	outb(0x00, VIADEV_REG(viadev, OFFSET_CONTROL));
605*4882a593Smuzhiyun 	/* clear interrupts */
606*4882a593Smuzhiyun 	outb(0x03, VIADEV_REG(viadev, OFFSET_STATUS));
607*4882a593Smuzhiyun 	outb(0x00, VIADEV_REG(viadev, OFFSET_TYPE)); /* for via686 */
608*4882a593Smuzhiyun 	// outl(0, VIADEV_REG(viadev, OFFSET_CURR_PTR));
609*4882a593Smuzhiyun 	viadev->lastpos = 0;
610*4882a593Smuzhiyun 	viadev->hwptr_done = 0;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun /*
615*4882a593Smuzhiyun  *  Interrupt handler
616*4882a593Smuzhiyun  *  Used for 686 and 8233A
617*4882a593Smuzhiyun  */
snd_via686_interrupt(int irq,void * dev_id)618*4882a593Smuzhiyun static irqreturn_t snd_via686_interrupt(int irq, void *dev_id)
619*4882a593Smuzhiyun {
620*4882a593Smuzhiyun 	struct via82xx *chip = dev_id;
621*4882a593Smuzhiyun 	unsigned int status;
622*4882a593Smuzhiyun 	unsigned int i;
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	status = inl(VIAREG(chip, SGD_SHADOW));
625*4882a593Smuzhiyun 	if (! (status & chip->intr_mask)) {
626*4882a593Smuzhiyun 		if (chip->rmidi)
627*4882a593Smuzhiyun 			/* check mpu401 interrupt */
628*4882a593Smuzhiyun 			return snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
629*4882a593Smuzhiyun 		return IRQ_NONE;
630*4882a593Smuzhiyun 	}
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 	/* check status for each stream */
633*4882a593Smuzhiyun 	spin_lock(&chip->reg_lock);
634*4882a593Smuzhiyun 	for (i = 0; i < chip->num_devs; i++) {
635*4882a593Smuzhiyun 		struct viadev *viadev = &chip->devs[i];
636*4882a593Smuzhiyun 		unsigned char c_status = inb(VIADEV_REG(viadev, OFFSET_STATUS));
637*4882a593Smuzhiyun 		if (! (c_status & (VIA_REG_STAT_EOL|VIA_REG_STAT_FLAG|VIA_REG_STAT_STOPPED)))
638*4882a593Smuzhiyun 			continue;
639*4882a593Smuzhiyun 		if (viadev->substream && viadev->running) {
640*4882a593Smuzhiyun 			/*
641*4882a593Smuzhiyun 			 * Update hwptr_done based on 'period elapsed'
642*4882a593Smuzhiyun 			 * interrupts. We'll use it, when the chip returns 0
643*4882a593Smuzhiyun 			 * for OFFSET_CURR_COUNT.
644*4882a593Smuzhiyun 			 */
645*4882a593Smuzhiyun 			if (c_status & VIA_REG_STAT_EOL)
646*4882a593Smuzhiyun 				viadev->hwptr_done = 0;
647*4882a593Smuzhiyun 			else
648*4882a593Smuzhiyun 				viadev->hwptr_done += viadev->fragsize;
649*4882a593Smuzhiyun 			viadev->in_interrupt = c_status;
650*4882a593Smuzhiyun 			spin_unlock(&chip->reg_lock);
651*4882a593Smuzhiyun 			snd_pcm_period_elapsed(viadev->substream);
652*4882a593Smuzhiyun 			spin_lock(&chip->reg_lock);
653*4882a593Smuzhiyun 			viadev->in_interrupt = 0;
654*4882a593Smuzhiyun 		}
655*4882a593Smuzhiyun 		outb(c_status, VIADEV_REG(viadev, OFFSET_STATUS)); /* ack */
656*4882a593Smuzhiyun 	}
657*4882a593Smuzhiyun 	spin_unlock(&chip->reg_lock);
658*4882a593Smuzhiyun 	return IRQ_HANDLED;
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun /*
662*4882a593Smuzhiyun  *  Interrupt handler
663*4882a593Smuzhiyun  */
snd_via8233_interrupt(int irq,void * dev_id)664*4882a593Smuzhiyun static irqreturn_t snd_via8233_interrupt(int irq, void *dev_id)
665*4882a593Smuzhiyun {
666*4882a593Smuzhiyun 	struct via82xx *chip = dev_id;
667*4882a593Smuzhiyun 	unsigned int status;
668*4882a593Smuzhiyun 	unsigned int i;
669*4882a593Smuzhiyun 	int irqreturn = 0;
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	/* check status for each stream */
672*4882a593Smuzhiyun 	spin_lock(&chip->reg_lock);
673*4882a593Smuzhiyun 	status = inl(VIAREG(chip, SGD_SHADOW));
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	for (i = 0; i < chip->num_devs; i++) {
676*4882a593Smuzhiyun 		struct viadev *viadev = &chip->devs[i];
677*4882a593Smuzhiyun 		struct snd_pcm_substream *substream;
678*4882a593Smuzhiyun 		unsigned char c_status, shadow_status;
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 		shadow_status = (status >> viadev->shadow_shift) &
681*4882a593Smuzhiyun 			(VIA8233_SHADOW_STAT_ACTIVE|VIA_REG_STAT_EOL|
682*4882a593Smuzhiyun 			 VIA_REG_STAT_FLAG);
683*4882a593Smuzhiyun 		c_status = shadow_status & (VIA_REG_STAT_EOL|VIA_REG_STAT_FLAG);
684*4882a593Smuzhiyun 		if (!c_status)
685*4882a593Smuzhiyun 			continue;
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun 		substream = viadev->substream;
688*4882a593Smuzhiyun 		if (substream && viadev->running) {
689*4882a593Smuzhiyun 			/*
690*4882a593Smuzhiyun 			 * Update hwptr_done based on 'period elapsed'
691*4882a593Smuzhiyun 			 * interrupts. We'll use it, when the chip returns 0
692*4882a593Smuzhiyun 			 * for OFFSET_CURR_COUNT.
693*4882a593Smuzhiyun 			 */
694*4882a593Smuzhiyun 			if (c_status & VIA_REG_STAT_EOL)
695*4882a593Smuzhiyun 				viadev->hwptr_done = 0;
696*4882a593Smuzhiyun 			else
697*4882a593Smuzhiyun 				viadev->hwptr_done += viadev->fragsize;
698*4882a593Smuzhiyun 			viadev->in_interrupt = c_status;
699*4882a593Smuzhiyun 			if (shadow_status & VIA8233_SHADOW_STAT_ACTIVE)
700*4882a593Smuzhiyun 				viadev->in_interrupt |= VIA_REG_STAT_ACTIVE;
701*4882a593Smuzhiyun 			spin_unlock(&chip->reg_lock);
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 			snd_pcm_period_elapsed(substream);
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun 			spin_lock(&chip->reg_lock);
706*4882a593Smuzhiyun 			viadev->in_interrupt = 0;
707*4882a593Smuzhiyun 		}
708*4882a593Smuzhiyun 		outb(c_status, VIADEV_REG(viadev, OFFSET_STATUS)); /* ack */
709*4882a593Smuzhiyun 		irqreturn = 1;
710*4882a593Smuzhiyun 	}
711*4882a593Smuzhiyun 	spin_unlock(&chip->reg_lock);
712*4882a593Smuzhiyun 	return IRQ_RETVAL(irqreturn);
713*4882a593Smuzhiyun }
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun /*
716*4882a593Smuzhiyun  *  PCM callbacks
717*4882a593Smuzhiyun  */
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun /*
720*4882a593Smuzhiyun  * trigger callback
721*4882a593Smuzhiyun  */
snd_via82xx_pcm_trigger(struct snd_pcm_substream * substream,int cmd)722*4882a593Smuzhiyun static int snd_via82xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
723*4882a593Smuzhiyun {
724*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
725*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
726*4882a593Smuzhiyun 	unsigned char val;
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	if (chip->chip_type != TYPE_VIA686)
729*4882a593Smuzhiyun 		val = VIA_REG_CTRL_INT;
730*4882a593Smuzhiyun 	else
731*4882a593Smuzhiyun 		val = 0;
732*4882a593Smuzhiyun 	switch (cmd) {
733*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_START:
734*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_RESUME:
735*4882a593Smuzhiyun 		val |= VIA_REG_CTRL_START;
736*4882a593Smuzhiyun 		viadev->running = 1;
737*4882a593Smuzhiyun 		break;
738*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_STOP:
739*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_SUSPEND:
740*4882a593Smuzhiyun 		val = VIA_REG_CTRL_TERMINATE;
741*4882a593Smuzhiyun 		viadev->running = 0;
742*4882a593Smuzhiyun 		break;
743*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
744*4882a593Smuzhiyun 		val |= VIA_REG_CTRL_PAUSE;
745*4882a593Smuzhiyun 		viadev->running = 0;
746*4882a593Smuzhiyun 		break;
747*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
748*4882a593Smuzhiyun 		viadev->running = 1;
749*4882a593Smuzhiyun 		break;
750*4882a593Smuzhiyun 	default:
751*4882a593Smuzhiyun 		return -EINVAL;
752*4882a593Smuzhiyun 	}
753*4882a593Smuzhiyun 	outb(val, VIADEV_REG(viadev, OFFSET_CONTROL));
754*4882a593Smuzhiyun 	if (cmd == SNDRV_PCM_TRIGGER_STOP)
755*4882a593Smuzhiyun 		snd_via82xx_channel_reset(chip, viadev);
756*4882a593Smuzhiyun 	return 0;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun /*
761*4882a593Smuzhiyun  * pointer callbacks
762*4882a593Smuzhiyun  */
763*4882a593Smuzhiyun 
764*4882a593Smuzhiyun /*
765*4882a593Smuzhiyun  * calculate the linear position at the given sg-buffer index and the rest count
766*4882a593Smuzhiyun  */
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun #define check_invalid_pos(viadev,pos) \
769*4882a593Smuzhiyun 	((pos) < viadev->lastpos && ((pos) >= viadev->bufsize2 ||\
770*4882a593Smuzhiyun 				     viadev->lastpos < viadev->bufsize2))
771*4882a593Smuzhiyun 
calc_linear_pos(struct via82xx * chip,struct viadev * viadev,unsigned int idx,unsigned int count)772*4882a593Smuzhiyun static inline unsigned int calc_linear_pos(struct via82xx *chip,
773*4882a593Smuzhiyun 					   struct viadev *viadev,
774*4882a593Smuzhiyun 					   unsigned int idx,
775*4882a593Smuzhiyun 					   unsigned int count)
776*4882a593Smuzhiyun {
777*4882a593Smuzhiyun 	unsigned int size, base, res;
778*4882a593Smuzhiyun 
779*4882a593Smuzhiyun 	size = viadev->idx_table[idx].size;
780*4882a593Smuzhiyun 	base = viadev->idx_table[idx].offset;
781*4882a593Smuzhiyun 	res = base + size - count;
782*4882a593Smuzhiyun 	if (res >= viadev->bufsize)
783*4882a593Smuzhiyun 		res -= viadev->bufsize;
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun 	/* check the validity of the calculated position */
786*4882a593Smuzhiyun 	if (size < count) {
787*4882a593Smuzhiyun 		dev_dbg(chip->card->dev,
788*4882a593Smuzhiyun 			"invalid via82xx_cur_ptr (size = %d, count = %d)\n",
789*4882a593Smuzhiyun 			   (int)size, (int)count);
790*4882a593Smuzhiyun 		res = viadev->lastpos;
791*4882a593Smuzhiyun 	} else {
792*4882a593Smuzhiyun 		if (! count) {
793*4882a593Smuzhiyun 			/* Some mobos report count = 0 on the DMA boundary,
794*4882a593Smuzhiyun 			 * i.e. count = size indeed.
795*4882a593Smuzhiyun 			 * Let's check whether this step is above the expected size.
796*4882a593Smuzhiyun 			 */
797*4882a593Smuzhiyun 			int delta = res - viadev->lastpos;
798*4882a593Smuzhiyun 			if (delta < 0)
799*4882a593Smuzhiyun 				delta += viadev->bufsize;
800*4882a593Smuzhiyun 			if ((unsigned int)delta > viadev->fragsize)
801*4882a593Smuzhiyun 				res = base;
802*4882a593Smuzhiyun 		}
803*4882a593Smuzhiyun 		if (check_invalid_pos(viadev, res)) {
804*4882a593Smuzhiyun #ifdef POINTER_DEBUG
805*4882a593Smuzhiyun 			dev_dbg(chip->card->dev,
806*4882a593Smuzhiyun 				"fail: idx = %i/%i, lastpos = 0x%x, bufsize2 = 0x%x, offsize = 0x%x, size = 0x%x, count = 0x%x\n",
807*4882a593Smuzhiyun 				idx, viadev->tbl_entries,
808*4882a593Smuzhiyun 			       viadev->lastpos, viadev->bufsize2,
809*4882a593Smuzhiyun 			       viadev->idx_table[idx].offset,
810*4882a593Smuzhiyun 			       viadev->idx_table[idx].size, count);
811*4882a593Smuzhiyun #endif
812*4882a593Smuzhiyun 			/* count register returns full size when end of buffer is reached */
813*4882a593Smuzhiyun 			res = base + size;
814*4882a593Smuzhiyun 			if (check_invalid_pos(viadev, res)) {
815*4882a593Smuzhiyun 				dev_dbg(chip->card->dev,
816*4882a593Smuzhiyun 					"invalid via82xx_cur_ptr (2), using last valid pointer\n");
817*4882a593Smuzhiyun 				res = viadev->lastpos;
818*4882a593Smuzhiyun 			}
819*4882a593Smuzhiyun 		}
820*4882a593Smuzhiyun 	}
821*4882a593Smuzhiyun 	return res;
822*4882a593Smuzhiyun }
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun /*
825*4882a593Smuzhiyun  * get the current pointer on via686
826*4882a593Smuzhiyun  */
snd_via686_pcm_pointer(struct snd_pcm_substream * substream)827*4882a593Smuzhiyun static snd_pcm_uframes_t snd_via686_pcm_pointer(struct snd_pcm_substream *substream)
828*4882a593Smuzhiyun {
829*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
830*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
831*4882a593Smuzhiyun 	unsigned int idx, ptr, count, res;
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 	if (snd_BUG_ON(!viadev->tbl_entries))
834*4882a593Smuzhiyun 		return 0;
835*4882a593Smuzhiyun 	if (!(inb(VIADEV_REG(viadev, OFFSET_STATUS)) & VIA_REG_STAT_ACTIVE))
836*4882a593Smuzhiyun 		return 0;
837*4882a593Smuzhiyun 
838*4882a593Smuzhiyun 	spin_lock(&chip->reg_lock);
839*4882a593Smuzhiyun 	count = inl(VIADEV_REG(viadev, OFFSET_CURR_COUNT)) & 0xffffff;
840*4882a593Smuzhiyun 	/* The via686a does not have the current index register,
841*4882a593Smuzhiyun 	 * so we need to calculate the index from CURR_PTR.
842*4882a593Smuzhiyun 	 */
843*4882a593Smuzhiyun 	ptr = inl(VIADEV_REG(viadev, OFFSET_CURR_PTR));
844*4882a593Smuzhiyun 	if (ptr <= (unsigned int)viadev->table.addr)
845*4882a593Smuzhiyun 		idx = 0;
846*4882a593Smuzhiyun 	else /* CURR_PTR holds the address + 8 */
847*4882a593Smuzhiyun 		idx = ((ptr - (unsigned int)viadev->table.addr) / 8 - 1) % viadev->tbl_entries;
848*4882a593Smuzhiyun 	res = calc_linear_pos(chip, viadev, idx, count);
849*4882a593Smuzhiyun 	viadev->lastpos = res; /* remember the last position */
850*4882a593Smuzhiyun 	spin_unlock(&chip->reg_lock);
851*4882a593Smuzhiyun 
852*4882a593Smuzhiyun 	return bytes_to_frames(substream->runtime, res);
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun /*
856*4882a593Smuzhiyun  * get the current pointer on via823x
857*4882a593Smuzhiyun  */
snd_via8233_pcm_pointer(struct snd_pcm_substream * substream)858*4882a593Smuzhiyun static snd_pcm_uframes_t snd_via8233_pcm_pointer(struct snd_pcm_substream *substream)
859*4882a593Smuzhiyun {
860*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
861*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
862*4882a593Smuzhiyun 	unsigned int idx, count, res;
863*4882a593Smuzhiyun 	int status;
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun 	if (snd_BUG_ON(!viadev->tbl_entries))
866*4882a593Smuzhiyun 		return 0;
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun 	spin_lock(&chip->reg_lock);
869*4882a593Smuzhiyun 	count = inl(VIADEV_REG(viadev, OFFSET_CURR_COUNT));
870*4882a593Smuzhiyun 	status = viadev->in_interrupt;
871*4882a593Smuzhiyun 	if (!status)
872*4882a593Smuzhiyun 		status = inb(VIADEV_REG(viadev, OFFSET_STATUS));
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun 	/* An apparent bug in the 8251 is worked around by sending a
875*4882a593Smuzhiyun 	 * REG_CTRL_START. */
876*4882a593Smuzhiyun 	if (chip->revision == VIA_REV_8251 && (status & VIA_REG_STAT_EOL))
877*4882a593Smuzhiyun 		snd_via82xx_pcm_trigger(substream, SNDRV_PCM_TRIGGER_START);
878*4882a593Smuzhiyun 
879*4882a593Smuzhiyun 	if (!(status & VIA_REG_STAT_ACTIVE)) {
880*4882a593Smuzhiyun 		res = 0;
881*4882a593Smuzhiyun 		goto unlock;
882*4882a593Smuzhiyun 	}
883*4882a593Smuzhiyun 	if (count & 0xffffff) {
884*4882a593Smuzhiyun 		idx = count >> 24;
885*4882a593Smuzhiyun 		if (idx >= viadev->tbl_entries) {
886*4882a593Smuzhiyun #ifdef POINTER_DEBUG
887*4882a593Smuzhiyun 			dev_dbg(chip->card->dev,
888*4882a593Smuzhiyun 				"fail: invalid idx = %i/%i\n", idx,
889*4882a593Smuzhiyun 			       viadev->tbl_entries);
890*4882a593Smuzhiyun #endif
891*4882a593Smuzhiyun 			res = viadev->lastpos;
892*4882a593Smuzhiyun 		} else {
893*4882a593Smuzhiyun 			count &= 0xffffff;
894*4882a593Smuzhiyun 			res = calc_linear_pos(chip, viadev, idx, count);
895*4882a593Smuzhiyun 		}
896*4882a593Smuzhiyun 	} else {
897*4882a593Smuzhiyun 		res = viadev->hwptr_done;
898*4882a593Smuzhiyun 		if (!viadev->in_interrupt) {
899*4882a593Smuzhiyun 			if (status & VIA_REG_STAT_EOL) {
900*4882a593Smuzhiyun 				res = 0;
901*4882a593Smuzhiyun 			} else
902*4882a593Smuzhiyun 				if (status & VIA_REG_STAT_FLAG) {
903*4882a593Smuzhiyun 					res += viadev->fragsize;
904*4882a593Smuzhiyun 				}
905*4882a593Smuzhiyun 		}
906*4882a593Smuzhiyun 	}
907*4882a593Smuzhiyun unlock:
908*4882a593Smuzhiyun 	viadev->lastpos = res;
909*4882a593Smuzhiyun 	spin_unlock(&chip->reg_lock);
910*4882a593Smuzhiyun 
911*4882a593Smuzhiyun 	return bytes_to_frames(substream->runtime, res);
912*4882a593Smuzhiyun }
913*4882a593Smuzhiyun 
914*4882a593Smuzhiyun 
915*4882a593Smuzhiyun /*
916*4882a593Smuzhiyun  * hw_params callback:
917*4882a593Smuzhiyun  * allocate the buffer and build up the buffer description table
918*4882a593Smuzhiyun  */
snd_via82xx_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)919*4882a593Smuzhiyun static int snd_via82xx_hw_params(struct snd_pcm_substream *substream,
920*4882a593Smuzhiyun 				 struct snd_pcm_hw_params *hw_params)
921*4882a593Smuzhiyun {
922*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
923*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 	return build_via_table(viadev, substream, chip->pci,
926*4882a593Smuzhiyun 			       params_periods(hw_params),
927*4882a593Smuzhiyun 			       params_period_bytes(hw_params));
928*4882a593Smuzhiyun }
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun /*
931*4882a593Smuzhiyun  * hw_free callback:
932*4882a593Smuzhiyun  * clean up the buffer description table and release the buffer
933*4882a593Smuzhiyun  */
snd_via82xx_hw_free(struct snd_pcm_substream * substream)934*4882a593Smuzhiyun static int snd_via82xx_hw_free(struct snd_pcm_substream *substream)
935*4882a593Smuzhiyun {
936*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
937*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun 	clean_via_table(viadev, substream, chip->pci);
940*4882a593Smuzhiyun 	return 0;
941*4882a593Smuzhiyun }
942*4882a593Smuzhiyun 
943*4882a593Smuzhiyun 
944*4882a593Smuzhiyun /*
945*4882a593Smuzhiyun  * set up the table pointer
946*4882a593Smuzhiyun  */
snd_via82xx_set_table_ptr(struct via82xx * chip,struct viadev * viadev)947*4882a593Smuzhiyun static void snd_via82xx_set_table_ptr(struct via82xx *chip, struct viadev *viadev)
948*4882a593Smuzhiyun {
949*4882a593Smuzhiyun 	snd_via82xx_codec_ready(chip, 0);
950*4882a593Smuzhiyun 	outl((u32)viadev->table.addr, VIADEV_REG(viadev, OFFSET_TABLE_PTR));
951*4882a593Smuzhiyun 	udelay(20);
952*4882a593Smuzhiyun 	snd_via82xx_codec_ready(chip, 0);
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun 
955*4882a593Smuzhiyun /*
956*4882a593Smuzhiyun  * prepare callback for playback and capture on via686
957*4882a593Smuzhiyun  */
via686_setup_format(struct via82xx * chip,struct viadev * viadev,struct snd_pcm_runtime * runtime)958*4882a593Smuzhiyun static void via686_setup_format(struct via82xx *chip, struct viadev *viadev,
959*4882a593Smuzhiyun 				struct snd_pcm_runtime *runtime)
960*4882a593Smuzhiyun {
961*4882a593Smuzhiyun 	snd_via82xx_channel_reset(chip, viadev);
962*4882a593Smuzhiyun 	/* this must be set after channel_reset */
963*4882a593Smuzhiyun 	snd_via82xx_set_table_ptr(chip, viadev);
964*4882a593Smuzhiyun 	outb(VIA_REG_TYPE_AUTOSTART |
965*4882a593Smuzhiyun 	     (runtime->format == SNDRV_PCM_FORMAT_S16_LE ? VIA_REG_TYPE_16BIT : 0) |
966*4882a593Smuzhiyun 	     (runtime->channels > 1 ? VIA_REG_TYPE_STEREO : 0) |
967*4882a593Smuzhiyun 	     ((viadev->reg_offset & 0x10) == 0 ? VIA_REG_TYPE_INT_LSAMPLE : 0) |
968*4882a593Smuzhiyun 	     VIA_REG_TYPE_INT_EOL |
969*4882a593Smuzhiyun 	     VIA_REG_TYPE_INT_FLAG, VIADEV_REG(viadev, OFFSET_TYPE));
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun 
snd_via686_playback_prepare(struct snd_pcm_substream * substream)972*4882a593Smuzhiyun static int snd_via686_playback_prepare(struct snd_pcm_substream *substream)
973*4882a593Smuzhiyun {
974*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
975*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
976*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun 	snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate);
979*4882a593Smuzhiyun 	snd_ac97_set_rate(chip->ac97, AC97_SPDIF, runtime->rate);
980*4882a593Smuzhiyun 	via686_setup_format(chip, viadev, runtime);
981*4882a593Smuzhiyun 	return 0;
982*4882a593Smuzhiyun }
983*4882a593Smuzhiyun 
snd_via686_capture_prepare(struct snd_pcm_substream * substream)984*4882a593Smuzhiyun static int snd_via686_capture_prepare(struct snd_pcm_substream *substream)
985*4882a593Smuzhiyun {
986*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
987*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
988*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun 	snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
991*4882a593Smuzhiyun 	via686_setup_format(chip, viadev, runtime);
992*4882a593Smuzhiyun 	return 0;
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun /*
996*4882a593Smuzhiyun  * lock the current rate
997*4882a593Smuzhiyun  */
via_lock_rate(struct via_rate_lock * rec,int rate)998*4882a593Smuzhiyun static int via_lock_rate(struct via_rate_lock *rec, int rate)
999*4882a593Smuzhiyun {
1000*4882a593Smuzhiyun 	int changed = 0;
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 	spin_lock_irq(&rec->lock);
1003*4882a593Smuzhiyun 	if (rec->rate != rate) {
1004*4882a593Smuzhiyun 		if (rec->rate && rec->used > 1) /* already set */
1005*4882a593Smuzhiyun 			changed = -EINVAL;
1006*4882a593Smuzhiyun 		else {
1007*4882a593Smuzhiyun 			rec->rate = rate;
1008*4882a593Smuzhiyun 			changed = 1;
1009*4882a593Smuzhiyun 		}
1010*4882a593Smuzhiyun 	}
1011*4882a593Smuzhiyun 	spin_unlock_irq(&rec->lock);
1012*4882a593Smuzhiyun 	return changed;
1013*4882a593Smuzhiyun }
1014*4882a593Smuzhiyun 
1015*4882a593Smuzhiyun /*
1016*4882a593Smuzhiyun  * prepare callback for DSX playback on via823x
1017*4882a593Smuzhiyun  */
snd_via8233_playback_prepare(struct snd_pcm_substream * substream)1018*4882a593Smuzhiyun static int snd_via8233_playback_prepare(struct snd_pcm_substream *substream)
1019*4882a593Smuzhiyun {
1020*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
1021*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
1022*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
1023*4882a593Smuzhiyun 	int ac97_rate = chip->dxs_src ? 48000 : runtime->rate;
1024*4882a593Smuzhiyun 	int rate_changed;
1025*4882a593Smuzhiyun 	u32 rbits;
1026*4882a593Smuzhiyun 
1027*4882a593Smuzhiyun 	if ((rate_changed = via_lock_rate(&chip->rates[0], ac97_rate)) < 0)
1028*4882a593Smuzhiyun 		return rate_changed;
1029*4882a593Smuzhiyun 	if (rate_changed)
1030*4882a593Smuzhiyun 		snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE,
1031*4882a593Smuzhiyun 				  chip->no_vra ? 48000 : runtime->rate);
1032*4882a593Smuzhiyun 	if (chip->spdif_on && viadev->reg_offset == 0x30)
1033*4882a593Smuzhiyun 		snd_ac97_set_rate(chip->ac97, AC97_SPDIF, runtime->rate);
1034*4882a593Smuzhiyun 
1035*4882a593Smuzhiyun 	if (runtime->rate == 48000)
1036*4882a593Smuzhiyun 		rbits = 0xfffff;
1037*4882a593Smuzhiyun 	else
1038*4882a593Smuzhiyun 		rbits = (0x100000 / 48000) * runtime->rate +
1039*4882a593Smuzhiyun 			((0x100000 % 48000) * runtime->rate) / 48000;
1040*4882a593Smuzhiyun 	snd_BUG_ON(rbits & ~0xfffff);
1041*4882a593Smuzhiyun 	snd_via82xx_channel_reset(chip, viadev);
1042*4882a593Smuzhiyun 	snd_via82xx_set_table_ptr(chip, viadev);
1043*4882a593Smuzhiyun 	outb(chip->playback_volume[viadev->reg_offset / 0x10][0],
1044*4882a593Smuzhiyun 	     VIADEV_REG(viadev, OFS_PLAYBACK_VOLUME_L));
1045*4882a593Smuzhiyun 	outb(chip->playback_volume[viadev->reg_offset / 0x10][1],
1046*4882a593Smuzhiyun 	     VIADEV_REG(viadev, OFS_PLAYBACK_VOLUME_R));
1047*4882a593Smuzhiyun 	outl((runtime->format == SNDRV_PCM_FORMAT_S16_LE ? VIA8233_REG_TYPE_16BIT : 0) | /* format */
1048*4882a593Smuzhiyun 	     (runtime->channels > 1 ? VIA8233_REG_TYPE_STEREO : 0) | /* stereo */
1049*4882a593Smuzhiyun 	     rbits | /* rate */
1050*4882a593Smuzhiyun 	     0xff000000,    /* STOP index is never reached */
1051*4882a593Smuzhiyun 	     VIADEV_REG(viadev, OFFSET_STOP_IDX));
1052*4882a593Smuzhiyun 	udelay(20);
1053*4882a593Smuzhiyun 	snd_via82xx_codec_ready(chip, 0);
1054*4882a593Smuzhiyun 	return 0;
1055*4882a593Smuzhiyun }
1056*4882a593Smuzhiyun 
1057*4882a593Smuzhiyun /*
1058*4882a593Smuzhiyun  * prepare callback for multi-channel playback on via823x
1059*4882a593Smuzhiyun  */
snd_via8233_multi_prepare(struct snd_pcm_substream * substream)1060*4882a593Smuzhiyun static int snd_via8233_multi_prepare(struct snd_pcm_substream *substream)
1061*4882a593Smuzhiyun {
1062*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
1063*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
1064*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
1065*4882a593Smuzhiyun 	unsigned int slots;
1066*4882a593Smuzhiyun 	int fmt;
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun 	if (via_lock_rate(&chip->rates[0], runtime->rate) < 0)
1069*4882a593Smuzhiyun 		return -EINVAL;
1070*4882a593Smuzhiyun 	snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate);
1071*4882a593Smuzhiyun 	snd_ac97_set_rate(chip->ac97, AC97_PCM_SURR_DAC_RATE, runtime->rate);
1072*4882a593Smuzhiyun 	snd_ac97_set_rate(chip->ac97, AC97_PCM_LFE_DAC_RATE, runtime->rate);
1073*4882a593Smuzhiyun 	snd_ac97_set_rate(chip->ac97, AC97_SPDIF, runtime->rate);
1074*4882a593Smuzhiyun 	snd_via82xx_channel_reset(chip, viadev);
1075*4882a593Smuzhiyun 	snd_via82xx_set_table_ptr(chip, viadev);
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 	fmt = (runtime->format == SNDRV_PCM_FORMAT_S16_LE) ?
1078*4882a593Smuzhiyun 		VIA_REG_MULTPLAY_FMT_16BIT : VIA_REG_MULTPLAY_FMT_8BIT;
1079*4882a593Smuzhiyun 	fmt |= runtime->channels << 4;
1080*4882a593Smuzhiyun 	outb(fmt, VIADEV_REG(viadev, OFS_MULTPLAY_FORMAT));
1081*4882a593Smuzhiyun #if 0
1082*4882a593Smuzhiyun 	if (chip->revision == VIA_REV_8233A)
1083*4882a593Smuzhiyun 		slots = 0;
1084*4882a593Smuzhiyun 	else
1085*4882a593Smuzhiyun #endif
1086*4882a593Smuzhiyun 	{
1087*4882a593Smuzhiyun 		/* set sample number to slot 3, 4, 7, 8, 6, 9 (for VIA8233/C,8235) */
1088*4882a593Smuzhiyun 		/* corresponding to FL, FR, RL, RR, C, LFE ?? */
1089*4882a593Smuzhiyun 		switch (runtime->channels) {
1090*4882a593Smuzhiyun 		case 1: slots = (1<<0) | (1<<4); break;
1091*4882a593Smuzhiyun 		case 2: slots = (1<<0) | (2<<4); break;
1092*4882a593Smuzhiyun 		case 3: slots = (1<<0) | (2<<4) | (5<<8); break;
1093*4882a593Smuzhiyun 		case 4: slots = (1<<0) | (2<<4) | (3<<8) | (4<<12); break;
1094*4882a593Smuzhiyun 		case 5: slots = (1<<0) | (2<<4) | (3<<8) | (4<<12) | (5<<16); break;
1095*4882a593Smuzhiyun 		case 6: slots = (1<<0) | (2<<4) | (3<<8) | (4<<12) | (5<<16) | (6<<20); break;
1096*4882a593Smuzhiyun 		default: slots = 0; break;
1097*4882a593Smuzhiyun 		}
1098*4882a593Smuzhiyun 	}
1099*4882a593Smuzhiyun 	/* STOP index is never reached */
1100*4882a593Smuzhiyun 	outl(0xff000000 | slots, VIADEV_REG(viadev, OFFSET_STOP_IDX));
1101*4882a593Smuzhiyun 	udelay(20);
1102*4882a593Smuzhiyun 	snd_via82xx_codec_ready(chip, 0);
1103*4882a593Smuzhiyun 	return 0;
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun /*
1107*4882a593Smuzhiyun  * prepare callback for capture on via823x
1108*4882a593Smuzhiyun  */
snd_via8233_capture_prepare(struct snd_pcm_substream * substream)1109*4882a593Smuzhiyun static int snd_via8233_capture_prepare(struct snd_pcm_substream *substream)
1110*4882a593Smuzhiyun {
1111*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
1112*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
1113*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun 	if (via_lock_rate(&chip->rates[1], runtime->rate) < 0)
1116*4882a593Smuzhiyun 		return -EINVAL;
1117*4882a593Smuzhiyun 	snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
1118*4882a593Smuzhiyun 	snd_via82xx_channel_reset(chip, viadev);
1119*4882a593Smuzhiyun 	snd_via82xx_set_table_ptr(chip, viadev);
1120*4882a593Smuzhiyun 	outb(VIA_REG_CAPTURE_FIFO_ENABLE, VIADEV_REG(viadev, OFS_CAPTURE_FIFO));
1121*4882a593Smuzhiyun 	outl((runtime->format == SNDRV_PCM_FORMAT_S16_LE ? VIA8233_REG_TYPE_16BIT : 0) |
1122*4882a593Smuzhiyun 	     (runtime->channels > 1 ? VIA8233_REG_TYPE_STEREO : 0) |
1123*4882a593Smuzhiyun 	     0xff000000,    /* STOP index is never reached */
1124*4882a593Smuzhiyun 	     VIADEV_REG(viadev, OFFSET_STOP_IDX));
1125*4882a593Smuzhiyun 	udelay(20);
1126*4882a593Smuzhiyun 	snd_via82xx_codec_ready(chip, 0);
1127*4882a593Smuzhiyun 	return 0;
1128*4882a593Smuzhiyun }
1129*4882a593Smuzhiyun 
1130*4882a593Smuzhiyun 
1131*4882a593Smuzhiyun /*
1132*4882a593Smuzhiyun  * pcm hardware definition, identical for both playback and capture
1133*4882a593Smuzhiyun  */
1134*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_via82xx_hw =
1135*4882a593Smuzhiyun {
1136*4882a593Smuzhiyun 	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1137*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1138*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_MMAP_VALID |
1139*4882a593Smuzhiyun 				 /* SNDRV_PCM_INFO_RESUME | */
1140*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_PAUSE),
1141*4882a593Smuzhiyun 	.formats =		SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1142*4882a593Smuzhiyun 	.rates =		SNDRV_PCM_RATE_48000,
1143*4882a593Smuzhiyun 	.rate_min =		48000,
1144*4882a593Smuzhiyun 	.rate_max =		48000,
1145*4882a593Smuzhiyun 	.channels_min =		1,
1146*4882a593Smuzhiyun 	.channels_max =		2,
1147*4882a593Smuzhiyun 	.buffer_bytes_max =	VIA_MAX_BUFSIZE,
1148*4882a593Smuzhiyun 	.period_bytes_min =	32,
1149*4882a593Smuzhiyun 	.period_bytes_max =	VIA_MAX_BUFSIZE / 2,
1150*4882a593Smuzhiyun 	.periods_min =		2,
1151*4882a593Smuzhiyun 	.periods_max =		VIA_TABLE_SIZE / 2,
1152*4882a593Smuzhiyun 	.fifo_size =		0,
1153*4882a593Smuzhiyun };
1154*4882a593Smuzhiyun 
1155*4882a593Smuzhiyun 
1156*4882a593Smuzhiyun /*
1157*4882a593Smuzhiyun  * open callback skeleton
1158*4882a593Smuzhiyun  */
snd_via82xx_pcm_open(struct via82xx * chip,struct viadev * viadev,struct snd_pcm_substream * substream)1159*4882a593Smuzhiyun static int snd_via82xx_pcm_open(struct via82xx *chip, struct viadev *viadev,
1160*4882a593Smuzhiyun 				struct snd_pcm_substream *substream)
1161*4882a593Smuzhiyun {
1162*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
1163*4882a593Smuzhiyun 	int err;
1164*4882a593Smuzhiyun 	struct via_rate_lock *ratep;
1165*4882a593Smuzhiyun 	bool use_src = false;
1166*4882a593Smuzhiyun 
1167*4882a593Smuzhiyun 	runtime->hw = snd_via82xx_hw;
1168*4882a593Smuzhiyun 
1169*4882a593Smuzhiyun 	/* set the hw rate condition */
1170*4882a593Smuzhiyun 	ratep = &chip->rates[viadev->direction];
1171*4882a593Smuzhiyun 	spin_lock_irq(&ratep->lock);
1172*4882a593Smuzhiyun 	ratep->used++;
1173*4882a593Smuzhiyun 	if (chip->spdif_on && viadev->reg_offset == 0x30) {
1174*4882a593Smuzhiyun 		/* DXS#3 and spdif is on */
1175*4882a593Smuzhiyun 		runtime->hw.rates = chip->ac97->rates[AC97_RATES_SPDIF];
1176*4882a593Smuzhiyun 		snd_pcm_limit_hw_rates(runtime);
1177*4882a593Smuzhiyun 	} else if (chip->dxs_fixed && viadev->reg_offset < 0x40) {
1178*4882a593Smuzhiyun 		/* fixed DXS playback rate */
1179*4882a593Smuzhiyun 		runtime->hw.rates = SNDRV_PCM_RATE_48000;
1180*4882a593Smuzhiyun 		runtime->hw.rate_min = runtime->hw.rate_max = 48000;
1181*4882a593Smuzhiyun 	} else if (chip->dxs_src && viadev->reg_offset < 0x40) {
1182*4882a593Smuzhiyun 		/* use full SRC capabilities of DXS */
1183*4882a593Smuzhiyun 		runtime->hw.rates = (SNDRV_PCM_RATE_CONTINUOUS |
1184*4882a593Smuzhiyun 				     SNDRV_PCM_RATE_8000_48000);
1185*4882a593Smuzhiyun 		runtime->hw.rate_min = 8000;
1186*4882a593Smuzhiyun 		runtime->hw.rate_max = 48000;
1187*4882a593Smuzhiyun 		use_src = true;
1188*4882a593Smuzhiyun 	} else if (! ratep->rate) {
1189*4882a593Smuzhiyun 		int idx = viadev->direction ? AC97_RATES_ADC : AC97_RATES_FRONT_DAC;
1190*4882a593Smuzhiyun 		runtime->hw.rates = chip->ac97->rates[idx];
1191*4882a593Smuzhiyun 		snd_pcm_limit_hw_rates(runtime);
1192*4882a593Smuzhiyun 	} else {
1193*4882a593Smuzhiyun 		/* a fixed rate */
1194*4882a593Smuzhiyun 		runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
1195*4882a593Smuzhiyun 		runtime->hw.rate_max = runtime->hw.rate_min = ratep->rate;
1196*4882a593Smuzhiyun 	}
1197*4882a593Smuzhiyun 	spin_unlock_irq(&ratep->lock);
1198*4882a593Smuzhiyun 
1199*4882a593Smuzhiyun 	/* we may remove following constaint when we modify table entries
1200*4882a593Smuzhiyun 	   in interrupt */
1201*4882a593Smuzhiyun 	if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1202*4882a593Smuzhiyun 		return err;
1203*4882a593Smuzhiyun 
1204*4882a593Smuzhiyun 	if (use_src) {
1205*4882a593Smuzhiyun 		err = snd_pcm_hw_rule_noresample(runtime, 48000);
1206*4882a593Smuzhiyun 		if (err < 0)
1207*4882a593Smuzhiyun 			return err;
1208*4882a593Smuzhiyun 	}
1209*4882a593Smuzhiyun 
1210*4882a593Smuzhiyun 	runtime->private_data = viadev;
1211*4882a593Smuzhiyun 	viadev->substream = substream;
1212*4882a593Smuzhiyun 
1213*4882a593Smuzhiyun 	return 0;
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun 
1216*4882a593Smuzhiyun 
1217*4882a593Smuzhiyun /*
1218*4882a593Smuzhiyun  * open callback for playback on via686
1219*4882a593Smuzhiyun  */
snd_via686_playback_open(struct snd_pcm_substream * substream)1220*4882a593Smuzhiyun static int snd_via686_playback_open(struct snd_pcm_substream *substream)
1221*4882a593Smuzhiyun {
1222*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
1223*4882a593Smuzhiyun 	struct viadev *viadev = &chip->devs[chip->playback_devno + substream->number];
1224*4882a593Smuzhiyun 	int err;
1225*4882a593Smuzhiyun 
1226*4882a593Smuzhiyun 	if ((err = snd_via82xx_pcm_open(chip, viadev, substream)) < 0)
1227*4882a593Smuzhiyun 		return err;
1228*4882a593Smuzhiyun 	return 0;
1229*4882a593Smuzhiyun }
1230*4882a593Smuzhiyun 
1231*4882a593Smuzhiyun /*
1232*4882a593Smuzhiyun  * open callback for playback on via823x DXS
1233*4882a593Smuzhiyun  */
snd_via8233_playback_open(struct snd_pcm_substream * substream)1234*4882a593Smuzhiyun static int snd_via8233_playback_open(struct snd_pcm_substream *substream)
1235*4882a593Smuzhiyun {
1236*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
1237*4882a593Smuzhiyun 	struct viadev *viadev;
1238*4882a593Smuzhiyun 	unsigned int stream;
1239*4882a593Smuzhiyun 	int err;
1240*4882a593Smuzhiyun 
1241*4882a593Smuzhiyun 	viadev = &chip->devs[chip->playback_devno + substream->number];
1242*4882a593Smuzhiyun 	if ((err = snd_via82xx_pcm_open(chip, viadev, substream)) < 0)
1243*4882a593Smuzhiyun 		return err;
1244*4882a593Smuzhiyun 	stream = viadev->reg_offset / 0x10;
1245*4882a593Smuzhiyun 	if (chip->dxs_controls[stream]) {
1246*4882a593Smuzhiyun 		chip->playback_volume[stream][0] =
1247*4882a593Smuzhiyun 				VIA_DXS_MAX_VOLUME - (dxs_init_volume & 31);
1248*4882a593Smuzhiyun 		chip->playback_volume[stream][1] =
1249*4882a593Smuzhiyun 				VIA_DXS_MAX_VOLUME - (dxs_init_volume & 31);
1250*4882a593Smuzhiyun 		chip->dxs_controls[stream]->vd[0].access &=
1251*4882a593Smuzhiyun 			~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1252*4882a593Smuzhiyun 		snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
1253*4882a593Smuzhiyun 			       SNDRV_CTL_EVENT_MASK_INFO,
1254*4882a593Smuzhiyun 			       &chip->dxs_controls[stream]->id);
1255*4882a593Smuzhiyun 	}
1256*4882a593Smuzhiyun 	return 0;
1257*4882a593Smuzhiyun }
1258*4882a593Smuzhiyun 
1259*4882a593Smuzhiyun /*
1260*4882a593Smuzhiyun  * open callback for playback on via823x multi-channel
1261*4882a593Smuzhiyun  */
snd_via8233_multi_open(struct snd_pcm_substream * substream)1262*4882a593Smuzhiyun static int snd_via8233_multi_open(struct snd_pcm_substream *substream)
1263*4882a593Smuzhiyun {
1264*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
1265*4882a593Smuzhiyun 	struct viadev *viadev = &chip->devs[chip->multi_devno];
1266*4882a593Smuzhiyun 	int err;
1267*4882a593Smuzhiyun 	/* channels constraint for VIA8233A
1268*4882a593Smuzhiyun 	 * 3 and 5 channels are not supported
1269*4882a593Smuzhiyun 	 */
1270*4882a593Smuzhiyun 	static const unsigned int channels[] = {
1271*4882a593Smuzhiyun 		1, 2, 4, 6
1272*4882a593Smuzhiyun 	};
1273*4882a593Smuzhiyun 	static const struct snd_pcm_hw_constraint_list hw_constraints_channels = {
1274*4882a593Smuzhiyun 		.count = ARRAY_SIZE(channels),
1275*4882a593Smuzhiyun 		.list = channels,
1276*4882a593Smuzhiyun 		.mask = 0,
1277*4882a593Smuzhiyun 	};
1278*4882a593Smuzhiyun 
1279*4882a593Smuzhiyun 	if ((err = snd_via82xx_pcm_open(chip, viadev, substream)) < 0)
1280*4882a593Smuzhiyun 		return err;
1281*4882a593Smuzhiyun 	substream->runtime->hw.channels_max = 6;
1282*4882a593Smuzhiyun 	if (chip->revision == VIA_REV_8233A)
1283*4882a593Smuzhiyun 		snd_pcm_hw_constraint_list(substream->runtime, 0,
1284*4882a593Smuzhiyun 					   SNDRV_PCM_HW_PARAM_CHANNELS,
1285*4882a593Smuzhiyun 					   &hw_constraints_channels);
1286*4882a593Smuzhiyun 	return 0;
1287*4882a593Smuzhiyun }
1288*4882a593Smuzhiyun 
1289*4882a593Smuzhiyun /*
1290*4882a593Smuzhiyun  * open callback for capture on via686 and via823x
1291*4882a593Smuzhiyun  */
snd_via82xx_capture_open(struct snd_pcm_substream * substream)1292*4882a593Smuzhiyun static int snd_via82xx_capture_open(struct snd_pcm_substream *substream)
1293*4882a593Smuzhiyun {
1294*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
1295*4882a593Smuzhiyun 	struct viadev *viadev = &chip->devs[chip->capture_devno + substream->pcm->device];
1296*4882a593Smuzhiyun 
1297*4882a593Smuzhiyun 	return snd_via82xx_pcm_open(chip, viadev, substream);
1298*4882a593Smuzhiyun }
1299*4882a593Smuzhiyun 
1300*4882a593Smuzhiyun /*
1301*4882a593Smuzhiyun  * close callback
1302*4882a593Smuzhiyun  */
snd_via82xx_pcm_close(struct snd_pcm_substream * substream)1303*4882a593Smuzhiyun static int snd_via82xx_pcm_close(struct snd_pcm_substream *substream)
1304*4882a593Smuzhiyun {
1305*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
1306*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
1307*4882a593Smuzhiyun 	struct via_rate_lock *ratep;
1308*4882a593Smuzhiyun 
1309*4882a593Smuzhiyun 	/* release the rate lock */
1310*4882a593Smuzhiyun 	ratep = &chip->rates[viadev->direction];
1311*4882a593Smuzhiyun 	spin_lock_irq(&ratep->lock);
1312*4882a593Smuzhiyun 	ratep->used--;
1313*4882a593Smuzhiyun 	if (! ratep->used)
1314*4882a593Smuzhiyun 		ratep->rate = 0;
1315*4882a593Smuzhiyun 	spin_unlock_irq(&ratep->lock);
1316*4882a593Smuzhiyun 	if (! ratep->rate) {
1317*4882a593Smuzhiyun 		if (! viadev->direction) {
1318*4882a593Smuzhiyun 			snd_ac97_update_power(chip->ac97,
1319*4882a593Smuzhiyun 					      AC97_PCM_FRONT_DAC_RATE, 0);
1320*4882a593Smuzhiyun 			snd_ac97_update_power(chip->ac97,
1321*4882a593Smuzhiyun 					      AC97_PCM_SURR_DAC_RATE, 0);
1322*4882a593Smuzhiyun 			snd_ac97_update_power(chip->ac97,
1323*4882a593Smuzhiyun 					      AC97_PCM_LFE_DAC_RATE, 0);
1324*4882a593Smuzhiyun 		} else
1325*4882a593Smuzhiyun 			snd_ac97_update_power(chip->ac97,
1326*4882a593Smuzhiyun 					      AC97_PCM_LR_ADC_RATE, 0);
1327*4882a593Smuzhiyun 	}
1328*4882a593Smuzhiyun 	viadev->substream = NULL;
1329*4882a593Smuzhiyun 	return 0;
1330*4882a593Smuzhiyun }
1331*4882a593Smuzhiyun 
snd_via8233_playback_close(struct snd_pcm_substream * substream)1332*4882a593Smuzhiyun static int snd_via8233_playback_close(struct snd_pcm_substream *substream)
1333*4882a593Smuzhiyun {
1334*4882a593Smuzhiyun 	struct via82xx *chip = snd_pcm_substream_chip(substream);
1335*4882a593Smuzhiyun 	struct viadev *viadev = substream->runtime->private_data;
1336*4882a593Smuzhiyun 	unsigned int stream;
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun 	stream = viadev->reg_offset / 0x10;
1339*4882a593Smuzhiyun 	if (chip->dxs_controls[stream]) {
1340*4882a593Smuzhiyun 		chip->dxs_controls[stream]->vd[0].access |=
1341*4882a593Smuzhiyun 			SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1342*4882a593Smuzhiyun 		snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO,
1343*4882a593Smuzhiyun 			       &chip->dxs_controls[stream]->id);
1344*4882a593Smuzhiyun 	}
1345*4882a593Smuzhiyun 	return snd_via82xx_pcm_close(substream);
1346*4882a593Smuzhiyun }
1347*4882a593Smuzhiyun 
1348*4882a593Smuzhiyun 
1349*4882a593Smuzhiyun /* via686 playback callbacks */
1350*4882a593Smuzhiyun static const struct snd_pcm_ops snd_via686_playback_ops = {
1351*4882a593Smuzhiyun 	.open =		snd_via686_playback_open,
1352*4882a593Smuzhiyun 	.close =	snd_via82xx_pcm_close,
1353*4882a593Smuzhiyun 	.hw_params =	snd_via82xx_hw_params,
1354*4882a593Smuzhiyun 	.hw_free =	snd_via82xx_hw_free,
1355*4882a593Smuzhiyun 	.prepare =	snd_via686_playback_prepare,
1356*4882a593Smuzhiyun 	.trigger =	snd_via82xx_pcm_trigger,
1357*4882a593Smuzhiyun 	.pointer =	snd_via686_pcm_pointer,
1358*4882a593Smuzhiyun };
1359*4882a593Smuzhiyun 
1360*4882a593Smuzhiyun /* via686 capture callbacks */
1361*4882a593Smuzhiyun static const struct snd_pcm_ops snd_via686_capture_ops = {
1362*4882a593Smuzhiyun 	.open =		snd_via82xx_capture_open,
1363*4882a593Smuzhiyun 	.close =	snd_via82xx_pcm_close,
1364*4882a593Smuzhiyun 	.hw_params =	snd_via82xx_hw_params,
1365*4882a593Smuzhiyun 	.hw_free =	snd_via82xx_hw_free,
1366*4882a593Smuzhiyun 	.prepare =	snd_via686_capture_prepare,
1367*4882a593Smuzhiyun 	.trigger =	snd_via82xx_pcm_trigger,
1368*4882a593Smuzhiyun 	.pointer =	snd_via686_pcm_pointer,
1369*4882a593Smuzhiyun };
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun /* via823x DSX playback callbacks */
1372*4882a593Smuzhiyun static const struct snd_pcm_ops snd_via8233_playback_ops = {
1373*4882a593Smuzhiyun 	.open =		snd_via8233_playback_open,
1374*4882a593Smuzhiyun 	.close =	snd_via8233_playback_close,
1375*4882a593Smuzhiyun 	.hw_params =	snd_via82xx_hw_params,
1376*4882a593Smuzhiyun 	.hw_free =	snd_via82xx_hw_free,
1377*4882a593Smuzhiyun 	.prepare =	snd_via8233_playback_prepare,
1378*4882a593Smuzhiyun 	.trigger =	snd_via82xx_pcm_trigger,
1379*4882a593Smuzhiyun 	.pointer =	snd_via8233_pcm_pointer,
1380*4882a593Smuzhiyun };
1381*4882a593Smuzhiyun 
1382*4882a593Smuzhiyun /* via823x multi-channel playback callbacks */
1383*4882a593Smuzhiyun static const struct snd_pcm_ops snd_via8233_multi_ops = {
1384*4882a593Smuzhiyun 	.open =		snd_via8233_multi_open,
1385*4882a593Smuzhiyun 	.close =	snd_via82xx_pcm_close,
1386*4882a593Smuzhiyun 	.hw_params =	snd_via82xx_hw_params,
1387*4882a593Smuzhiyun 	.hw_free =	snd_via82xx_hw_free,
1388*4882a593Smuzhiyun 	.prepare =	snd_via8233_multi_prepare,
1389*4882a593Smuzhiyun 	.trigger =	snd_via82xx_pcm_trigger,
1390*4882a593Smuzhiyun 	.pointer =	snd_via8233_pcm_pointer,
1391*4882a593Smuzhiyun };
1392*4882a593Smuzhiyun 
1393*4882a593Smuzhiyun /* via823x capture callbacks */
1394*4882a593Smuzhiyun static const struct snd_pcm_ops snd_via8233_capture_ops = {
1395*4882a593Smuzhiyun 	.open =		snd_via82xx_capture_open,
1396*4882a593Smuzhiyun 	.close =	snd_via82xx_pcm_close,
1397*4882a593Smuzhiyun 	.hw_params =	snd_via82xx_hw_params,
1398*4882a593Smuzhiyun 	.hw_free =	snd_via82xx_hw_free,
1399*4882a593Smuzhiyun 	.prepare =	snd_via8233_capture_prepare,
1400*4882a593Smuzhiyun 	.trigger =	snd_via82xx_pcm_trigger,
1401*4882a593Smuzhiyun 	.pointer =	snd_via8233_pcm_pointer,
1402*4882a593Smuzhiyun };
1403*4882a593Smuzhiyun 
1404*4882a593Smuzhiyun 
init_viadev(struct via82xx * chip,int idx,unsigned int reg_offset,int shadow_pos,int direction)1405*4882a593Smuzhiyun static void init_viadev(struct via82xx *chip, int idx, unsigned int reg_offset,
1406*4882a593Smuzhiyun 			int shadow_pos, int direction)
1407*4882a593Smuzhiyun {
1408*4882a593Smuzhiyun 	chip->devs[idx].reg_offset = reg_offset;
1409*4882a593Smuzhiyun 	chip->devs[idx].shadow_shift = shadow_pos * 4;
1410*4882a593Smuzhiyun 	chip->devs[idx].direction = direction;
1411*4882a593Smuzhiyun 	chip->devs[idx].port = chip->port + reg_offset;
1412*4882a593Smuzhiyun }
1413*4882a593Smuzhiyun 
1414*4882a593Smuzhiyun /*
1415*4882a593Smuzhiyun  * create pcm instances for VIA8233, 8233C and 8235 (not 8233A)
1416*4882a593Smuzhiyun  */
snd_via8233_pcm_new(struct via82xx * chip)1417*4882a593Smuzhiyun static int snd_via8233_pcm_new(struct via82xx *chip)
1418*4882a593Smuzhiyun {
1419*4882a593Smuzhiyun 	struct snd_pcm *pcm;
1420*4882a593Smuzhiyun 	struct snd_pcm_chmap *chmap;
1421*4882a593Smuzhiyun 	int i, err;
1422*4882a593Smuzhiyun 
1423*4882a593Smuzhiyun 	chip->playback_devno = 0;	/* x 4 */
1424*4882a593Smuzhiyun 	chip->multi_devno = 4;		/* x 1 */
1425*4882a593Smuzhiyun 	chip->capture_devno = 5;	/* x 2 */
1426*4882a593Smuzhiyun 	chip->num_devs = 7;
1427*4882a593Smuzhiyun 	chip->intr_mask = 0x33033333; /* FLAG|EOL for rec0-1, mc, sdx0-3 */
1428*4882a593Smuzhiyun 
1429*4882a593Smuzhiyun 	/* PCM #0:  4 DSX playbacks and 1 capture */
1430*4882a593Smuzhiyun 	err = snd_pcm_new(chip->card, chip->card->shortname, 0, 4, 1, &pcm);
1431*4882a593Smuzhiyun 	if (err < 0)
1432*4882a593Smuzhiyun 		return err;
1433*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_playback_ops);
1434*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via8233_capture_ops);
1435*4882a593Smuzhiyun 	pcm->private_data = chip;
1436*4882a593Smuzhiyun 	strcpy(pcm->name, chip->card->shortname);
1437*4882a593Smuzhiyun 	chip->pcms[0] = pcm;
1438*4882a593Smuzhiyun 	/* set up playbacks */
1439*4882a593Smuzhiyun 	for (i = 0; i < 4; i++)
1440*4882a593Smuzhiyun 		init_viadev(chip, i, 0x10 * i, i, 0);
1441*4882a593Smuzhiyun 	/* capture */
1442*4882a593Smuzhiyun 	init_viadev(chip, chip->capture_devno, VIA_REG_CAPTURE_8233_STATUS, 6, 1);
1443*4882a593Smuzhiyun 
1444*4882a593Smuzhiyun 	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1445*4882a593Smuzhiyun 				       &chip->pci->dev,
1446*4882a593Smuzhiyun 				       64*1024, VIA_MAX_BUFSIZE);
1447*4882a593Smuzhiyun 
1448*4882a593Smuzhiyun 	err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1449*4882a593Smuzhiyun 				     snd_pcm_std_chmaps, 2, 0,
1450*4882a593Smuzhiyun 				     &chmap);
1451*4882a593Smuzhiyun 	if (err < 0)
1452*4882a593Smuzhiyun 		return err;
1453*4882a593Smuzhiyun 
1454*4882a593Smuzhiyun 	/* PCM #1:  multi-channel playback and 2nd capture */
1455*4882a593Smuzhiyun 	err = snd_pcm_new(chip->card, chip->card->shortname, 1, 1, 1, &pcm);
1456*4882a593Smuzhiyun 	if (err < 0)
1457*4882a593Smuzhiyun 		return err;
1458*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_multi_ops);
1459*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via8233_capture_ops);
1460*4882a593Smuzhiyun 	pcm->private_data = chip;
1461*4882a593Smuzhiyun 	strcpy(pcm->name, chip->card->shortname);
1462*4882a593Smuzhiyun 	chip->pcms[1] = pcm;
1463*4882a593Smuzhiyun 	/* set up playback */
1464*4882a593Smuzhiyun 	init_viadev(chip, chip->multi_devno, VIA_REG_MULTPLAY_STATUS, 4, 0);
1465*4882a593Smuzhiyun 	/* set up capture */
1466*4882a593Smuzhiyun 	init_viadev(chip, chip->capture_devno + 1, VIA_REG_CAPTURE_8233_STATUS + 0x10, 7, 1);
1467*4882a593Smuzhiyun 
1468*4882a593Smuzhiyun 	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1469*4882a593Smuzhiyun 				       &chip->pci->dev,
1470*4882a593Smuzhiyun 				       64*1024, VIA_MAX_BUFSIZE);
1471*4882a593Smuzhiyun 
1472*4882a593Smuzhiyun 	err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1473*4882a593Smuzhiyun 				     snd_pcm_alt_chmaps, 6, 0,
1474*4882a593Smuzhiyun 				     &chmap);
1475*4882a593Smuzhiyun 	if (err < 0)
1476*4882a593Smuzhiyun 		return err;
1477*4882a593Smuzhiyun 	chip->ac97->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	return 0;
1480*4882a593Smuzhiyun }
1481*4882a593Smuzhiyun 
1482*4882a593Smuzhiyun /*
1483*4882a593Smuzhiyun  * create pcm instances for VIA8233A
1484*4882a593Smuzhiyun  */
snd_via8233a_pcm_new(struct via82xx * chip)1485*4882a593Smuzhiyun static int snd_via8233a_pcm_new(struct via82xx *chip)
1486*4882a593Smuzhiyun {
1487*4882a593Smuzhiyun 	struct snd_pcm *pcm;
1488*4882a593Smuzhiyun 	struct snd_pcm_chmap *chmap;
1489*4882a593Smuzhiyun 	int err;
1490*4882a593Smuzhiyun 
1491*4882a593Smuzhiyun 	chip->multi_devno = 0;
1492*4882a593Smuzhiyun 	chip->playback_devno = 1;
1493*4882a593Smuzhiyun 	chip->capture_devno = 2;
1494*4882a593Smuzhiyun 	chip->num_devs = 3;
1495*4882a593Smuzhiyun 	chip->intr_mask = 0x03033000; /* FLAG|EOL for rec0, mc, sdx3 */
1496*4882a593Smuzhiyun 
1497*4882a593Smuzhiyun 	/* PCM #0:  multi-channel playback and capture */
1498*4882a593Smuzhiyun 	err = snd_pcm_new(chip->card, chip->card->shortname, 0, 1, 1, &pcm);
1499*4882a593Smuzhiyun 	if (err < 0)
1500*4882a593Smuzhiyun 		return err;
1501*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_multi_ops);
1502*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via8233_capture_ops);
1503*4882a593Smuzhiyun 	pcm->private_data = chip;
1504*4882a593Smuzhiyun 	strcpy(pcm->name, chip->card->shortname);
1505*4882a593Smuzhiyun 	chip->pcms[0] = pcm;
1506*4882a593Smuzhiyun 	/* set up playback */
1507*4882a593Smuzhiyun 	init_viadev(chip, chip->multi_devno, VIA_REG_MULTPLAY_STATUS, 4, 0);
1508*4882a593Smuzhiyun 	/* capture */
1509*4882a593Smuzhiyun 	init_viadev(chip, chip->capture_devno, VIA_REG_CAPTURE_8233_STATUS, 6, 1);
1510*4882a593Smuzhiyun 
1511*4882a593Smuzhiyun 	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1512*4882a593Smuzhiyun 				       &chip->pci->dev,
1513*4882a593Smuzhiyun 				       64*1024, VIA_MAX_BUFSIZE);
1514*4882a593Smuzhiyun 
1515*4882a593Smuzhiyun 	err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1516*4882a593Smuzhiyun 				     snd_pcm_alt_chmaps, 6, 0,
1517*4882a593Smuzhiyun 				     &chmap);
1518*4882a593Smuzhiyun 	if (err < 0)
1519*4882a593Smuzhiyun 		return err;
1520*4882a593Smuzhiyun 	chip->ac97->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1521*4882a593Smuzhiyun 
1522*4882a593Smuzhiyun 	/* SPDIF supported? */
1523*4882a593Smuzhiyun 	if (! ac97_can_spdif(chip->ac97))
1524*4882a593Smuzhiyun 		return 0;
1525*4882a593Smuzhiyun 
1526*4882a593Smuzhiyun 	/* PCM #1:  DXS3 playback (for spdif) */
1527*4882a593Smuzhiyun 	err = snd_pcm_new(chip->card, chip->card->shortname, 1, 1, 0, &pcm);
1528*4882a593Smuzhiyun 	if (err < 0)
1529*4882a593Smuzhiyun 		return err;
1530*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via8233_playback_ops);
1531*4882a593Smuzhiyun 	pcm->private_data = chip;
1532*4882a593Smuzhiyun 	strcpy(pcm->name, chip->card->shortname);
1533*4882a593Smuzhiyun 	chip->pcms[1] = pcm;
1534*4882a593Smuzhiyun 	/* set up playback */
1535*4882a593Smuzhiyun 	init_viadev(chip, chip->playback_devno, 0x30, 3, 0);
1536*4882a593Smuzhiyun 
1537*4882a593Smuzhiyun 	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1538*4882a593Smuzhiyun 				       &chip->pci->dev,
1539*4882a593Smuzhiyun 				       64*1024, VIA_MAX_BUFSIZE);
1540*4882a593Smuzhiyun 	return 0;
1541*4882a593Smuzhiyun }
1542*4882a593Smuzhiyun 
1543*4882a593Smuzhiyun /*
1544*4882a593Smuzhiyun  * create a pcm instance for via686a/b
1545*4882a593Smuzhiyun  */
snd_via686_pcm_new(struct via82xx * chip)1546*4882a593Smuzhiyun static int snd_via686_pcm_new(struct via82xx *chip)
1547*4882a593Smuzhiyun {
1548*4882a593Smuzhiyun 	struct snd_pcm *pcm;
1549*4882a593Smuzhiyun 	int err;
1550*4882a593Smuzhiyun 
1551*4882a593Smuzhiyun 	chip->playback_devno = 0;
1552*4882a593Smuzhiyun 	chip->capture_devno = 1;
1553*4882a593Smuzhiyun 	chip->num_devs = 2;
1554*4882a593Smuzhiyun 	chip->intr_mask = 0x77; /* FLAG | EOL for PB, CP, FM */
1555*4882a593Smuzhiyun 
1556*4882a593Smuzhiyun 	err = snd_pcm_new(chip->card, chip->card->shortname, 0, 1, 1, &pcm);
1557*4882a593Smuzhiyun 	if (err < 0)
1558*4882a593Smuzhiyun 		return err;
1559*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_via686_playback_ops);
1560*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_via686_capture_ops);
1561*4882a593Smuzhiyun 	pcm->private_data = chip;
1562*4882a593Smuzhiyun 	strcpy(pcm->name, chip->card->shortname);
1563*4882a593Smuzhiyun 	chip->pcms[0] = pcm;
1564*4882a593Smuzhiyun 	init_viadev(chip, 0, VIA_REG_PLAYBACK_STATUS, 0, 0);
1565*4882a593Smuzhiyun 	init_viadev(chip, 1, VIA_REG_CAPTURE_STATUS, 0, 1);
1566*4882a593Smuzhiyun 
1567*4882a593Smuzhiyun 	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1568*4882a593Smuzhiyun 				       &chip->pci->dev,
1569*4882a593Smuzhiyun 				       64*1024, VIA_MAX_BUFSIZE);
1570*4882a593Smuzhiyun 	return 0;
1571*4882a593Smuzhiyun }
1572*4882a593Smuzhiyun 
1573*4882a593Smuzhiyun 
1574*4882a593Smuzhiyun /*
1575*4882a593Smuzhiyun  *  Mixer part
1576*4882a593Smuzhiyun  */
1577*4882a593Smuzhiyun 
snd_via8233_capture_source_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1578*4882a593Smuzhiyun static int snd_via8233_capture_source_info(struct snd_kcontrol *kcontrol,
1579*4882a593Smuzhiyun 					   struct snd_ctl_elem_info *uinfo)
1580*4882a593Smuzhiyun {
1581*4882a593Smuzhiyun 	/* formerly they were "Line" and "Mic", but it looks like that they
1582*4882a593Smuzhiyun 	 * have nothing to do with the actual physical connections...
1583*4882a593Smuzhiyun 	 */
1584*4882a593Smuzhiyun 	static const char * const texts[2] = {
1585*4882a593Smuzhiyun 		"Input1", "Input2"
1586*4882a593Smuzhiyun 	};
1587*4882a593Smuzhiyun 	return snd_ctl_enum_info(uinfo, 1, 2, texts);
1588*4882a593Smuzhiyun }
1589*4882a593Smuzhiyun 
snd_via8233_capture_source_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1590*4882a593Smuzhiyun static int snd_via8233_capture_source_get(struct snd_kcontrol *kcontrol,
1591*4882a593Smuzhiyun 					  struct snd_ctl_elem_value *ucontrol)
1592*4882a593Smuzhiyun {
1593*4882a593Smuzhiyun 	struct via82xx *chip = snd_kcontrol_chip(kcontrol);
1594*4882a593Smuzhiyun 	unsigned long port = chip->port + (kcontrol->id.index ? (VIA_REG_CAPTURE_CHANNEL + 0x10) : VIA_REG_CAPTURE_CHANNEL);
1595*4882a593Smuzhiyun 	ucontrol->value.enumerated.item[0] = inb(port) & VIA_REG_CAPTURE_CHANNEL_MIC ? 1 : 0;
1596*4882a593Smuzhiyun 	return 0;
1597*4882a593Smuzhiyun }
1598*4882a593Smuzhiyun 
snd_via8233_capture_source_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1599*4882a593Smuzhiyun static int snd_via8233_capture_source_put(struct snd_kcontrol *kcontrol,
1600*4882a593Smuzhiyun 					  struct snd_ctl_elem_value *ucontrol)
1601*4882a593Smuzhiyun {
1602*4882a593Smuzhiyun 	struct via82xx *chip = snd_kcontrol_chip(kcontrol);
1603*4882a593Smuzhiyun 	unsigned long port = chip->port + (kcontrol->id.index ? (VIA_REG_CAPTURE_CHANNEL + 0x10) : VIA_REG_CAPTURE_CHANNEL);
1604*4882a593Smuzhiyun 	u8 val, oval;
1605*4882a593Smuzhiyun 
1606*4882a593Smuzhiyun 	spin_lock_irq(&chip->reg_lock);
1607*4882a593Smuzhiyun 	oval = inb(port);
1608*4882a593Smuzhiyun 	val = oval & ~VIA_REG_CAPTURE_CHANNEL_MIC;
1609*4882a593Smuzhiyun 	if (ucontrol->value.enumerated.item[0])
1610*4882a593Smuzhiyun 		val |= VIA_REG_CAPTURE_CHANNEL_MIC;
1611*4882a593Smuzhiyun 	if (val != oval)
1612*4882a593Smuzhiyun 		outb(val, port);
1613*4882a593Smuzhiyun 	spin_unlock_irq(&chip->reg_lock);
1614*4882a593Smuzhiyun 	return val != oval;
1615*4882a593Smuzhiyun }
1616*4882a593Smuzhiyun 
1617*4882a593Smuzhiyun static struct snd_kcontrol_new snd_via8233_capture_source = {
1618*4882a593Smuzhiyun 	.name = "Input Source Select",
1619*4882a593Smuzhiyun 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1620*4882a593Smuzhiyun 	.info = snd_via8233_capture_source_info,
1621*4882a593Smuzhiyun 	.get = snd_via8233_capture_source_get,
1622*4882a593Smuzhiyun 	.put = snd_via8233_capture_source_put,
1623*4882a593Smuzhiyun };
1624*4882a593Smuzhiyun 
1625*4882a593Smuzhiyun #define snd_via8233_dxs3_spdif_info	snd_ctl_boolean_mono_info
1626*4882a593Smuzhiyun 
snd_via8233_dxs3_spdif_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1627*4882a593Smuzhiyun static int snd_via8233_dxs3_spdif_get(struct snd_kcontrol *kcontrol,
1628*4882a593Smuzhiyun 				      struct snd_ctl_elem_value *ucontrol)
1629*4882a593Smuzhiyun {
1630*4882a593Smuzhiyun 	struct via82xx *chip = snd_kcontrol_chip(kcontrol);
1631*4882a593Smuzhiyun 	u8 val;
1632*4882a593Smuzhiyun 
1633*4882a593Smuzhiyun 	pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &val);
1634*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (val & VIA8233_SPDIF_DX3) ? 1 : 0;
1635*4882a593Smuzhiyun 	return 0;
1636*4882a593Smuzhiyun }
1637*4882a593Smuzhiyun 
snd_via8233_dxs3_spdif_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1638*4882a593Smuzhiyun static int snd_via8233_dxs3_spdif_put(struct snd_kcontrol *kcontrol,
1639*4882a593Smuzhiyun 				      struct snd_ctl_elem_value *ucontrol)
1640*4882a593Smuzhiyun {
1641*4882a593Smuzhiyun 	struct via82xx *chip = snd_kcontrol_chip(kcontrol);
1642*4882a593Smuzhiyun 	u8 val, oval;
1643*4882a593Smuzhiyun 
1644*4882a593Smuzhiyun 	pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &oval);
1645*4882a593Smuzhiyun 	val = oval & ~VIA8233_SPDIF_DX3;
1646*4882a593Smuzhiyun 	if (ucontrol->value.integer.value[0])
1647*4882a593Smuzhiyun 		val |= VIA8233_SPDIF_DX3;
1648*4882a593Smuzhiyun 	/* save the spdif flag for rate filtering */
1649*4882a593Smuzhiyun 	chip->spdif_on = ucontrol->value.integer.value[0] ? 1 : 0;
1650*4882a593Smuzhiyun 	if (val != oval) {
1651*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, val);
1652*4882a593Smuzhiyun 		return 1;
1653*4882a593Smuzhiyun 	}
1654*4882a593Smuzhiyun 	return 0;
1655*4882a593Smuzhiyun }
1656*4882a593Smuzhiyun 
1657*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_via8233_dxs3_spdif_control = {
1658*4882a593Smuzhiyun 	.name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
1659*4882a593Smuzhiyun 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1660*4882a593Smuzhiyun 	.info = snd_via8233_dxs3_spdif_info,
1661*4882a593Smuzhiyun 	.get = snd_via8233_dxs3_spdif_get,
1662*4882a593Smuzhiyun 	.put = snd_via8233_dxs3_spdif_put,
1663*4882a593Smuzhiyun };
1664*4882a593Smuzhiyun 
snd_via8233_dxs_volume_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1665*4882a593Smuzhiyun static int snd_via8233_dxs_volume_info(struct snd_kcontrol *kcontrol,
1666*4882a593Smuzhiyun 				       struct snd_ctl_elem_info *uinfo)
1667*4882a593Smuzhiyun {
1668*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1669*4882a593Smuzhiyun 	uinfo->count = 2;
1670*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
1671*4882a593Smuzhiyun 	uinfo->value.integer.max = VIA_DXS_MAX_VOLUME;
1672*4882a593Smuzhiyun 	return 0;
1673*4882a593Smuzhiyun }
1674*4882a593Smuzhiyun 
snd_via8233_dxs_volume_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1675*4882a593Smuzhiyun static int snd_via8233_dxs_volume_get(struct snd_kcontrol *kcontrol,
1676*4882a593Smuzhiyun 				      struct snd_ctl_elem_value *ucontrol)
1677*4882a593Smuzhiyun {
1678*4882a593Smuzhiyun 	struct via82xx *chip = snd_kcontrol_chip(kcontrol);
1679*4882a593Smuzhiyun 	unsigned int idx = kcontrol->id.subdevice;
1680*4882a593Smuzhiyun 
1681*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = VIA_DXS_MAX_VOLUME - chip->playback_volume[idx][0];
1682*4882a593Smuzhiyun 	ucontrol->value.integer.value[1] = VIA_DXS_MAX_VOLUME - chip->playback_volume[idx][1];
1683*4882a593Smuzhiyun 	return 0;
1684*4882a593Smuzhiyun }
1685*4882a593Smuzhiyun 
snd_via8233_pcmdxs_volume_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1686*4882a593Smuzhiyun static int snd_via8233_pcmdxs_volume_get(struct snd_kcontrol *kcontrol,
1687*4882a593Smuzhiyun 					 struct snd_ctl_elem_value *ucontrol)
1688*4882a593Smuzhiyun {
1689*4882a593Smuzhiyun 	struct via82xx *chip = snd_kcontrol_chip(kcontrol);
1690*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = VIA_DXS_MAX_VOLUME - chip->playback_volume_c[0];
1691*4882a593Smuzhiyun 	ucontrol->value.integer.value[1] = VIA_DXS_MAX_VOLUME - chip->playback_volume_c[1];
1692*4882a593Smuzhiyun 	return 0;
1693*4882a593Smuzhiyun }
1694*4882a593Smuzhiyun 
snd_via8233_dxs_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1695*4882a593Smuzhiyun static int snd_via8233_dxs_volume_put(struct snd_kcontrol *kcontrol,
1696*4882a593Smuzhiyun 				      struct snd_ctl_elem_value *ucontrol)
1697*4882a593Smuzhiyun {
1698*4882a593Smuzhiyun 	struct via82xx *chip = snd_kcontrol_chip(kcontrol);
1699*4882a593Smuzhiyun 	unsigned int idx = kcontrol->id.subdevice;
1700*4882a593Smuzhiyun 	unsigned long port = chip->port + 0x10 * idx;
1701*4882a593Smuzhiyun 	unsigned char val;
1702*4882a593Smuzhiyun 	int i, change = 0;
1703*4882a593Smuzhiyun 
1704*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
1705*4882a593Smuzhiyun 		val = ucontrol->value.integer.value[i];
1706*4882a593Smuzhiyun 		if (val > VIA_DXS_MAX_VOLUME)
1707*4882a593Smuzhiyun 			val = VIA_DXS_MAX_VOLUME;
1708*4882a593Smuzhiyun 		val = VIA_DXS_MAX_VOLUME - val;
1709*4882a593Smuzhiyun 		change |= val != chip->playback_volume[idx][i];
1710*4882a593Smuzhiyun 		if (change) {
1711*4882a593Smuzhiyun 			chip->playback_volume[idx][i] = val;
1712*4882a593Smuzhiyun 			outb(val, port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i);
1713*4882a593Smuzhiyun 		}
1714*4882a593Smuzhiyun 	}
1715*4882a593Smuzhiyun 	return change;
1716*4882a593Smuzhiyun }
1717*4882a593Smuzhiyun 
snd_via8233_pcmdxs_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1718*4882a593Smuzhiyun static int snd_via8233_pcmdxs_volume_put(struct snd_kcontrol *kcontrol,
1719*4882a593Smuzhiyun 					 struct snd_ctl_elem_value *ucontrol)
1720*4882a593Smuzhiyun {
1721*4882a593Smuzhiyun 	struct via82xx *chip = snd_kcontrol_chip(kcontrol);
1722*4882a593Smuzhiyun 	unsigned int idx;
1723*4882a593Smuzhiyun 	unsigned char val;
1724*4882a593Smuzhiyun 	int i, change = 0;
1725*4882a593Smuzhiyun 
1726*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
1727*4882a593Smuzhiyun 		val = ucontrol->value.integer.value[i];
1728*4882a593Smuzhiyun 		if (val > VIA_DXS_MAX_VOLUME)
1729*4882a593Smuzhiyun 			val = VIA_DXS_MAX_VOLUME;
1730*4882a593Smuzhiyun 		val = VIA_DXS_MAX_VOLUME - val;
1731*4882a593Smuzhiyun 		if (val != chip->playback_volume_c[i]) {
1732*4882a593Smuzhiyun 			change = 1;
1733*4882a593Smuzhiyun 			chip->playback_volume_c[i] = val;
1734*4882a593Smuzhiyun 			for (idx = 0; idx < 4; idx++) {
1735*4882a593Smuzhiyun 				unsigned long port = chip->port + 0x10 * idx;
1736*4882a593Smuzhiyun 				chip->playback_volume[idx][i] = val;
1737*4882a593Smuzhiyun 				outb(val, port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i);
1738*4882a593Smuzhiyun 			}
1739*4882a593Smuzhiyun 		}
1740*4882a593Smuzhiyun 	}
1741*4882a593Smuzhiyun 	return change;
1742*4882a593Smuzhiyun }
1743*4882a593Smuzhiyun 
1744*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_dxs, -4650, 150, 1);
1745*4882a593Smuzhiyun 
1746*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_via8233_pcmdxs_volume_control = {
1747*4882a593Smuzhiyun 	.name = "PCM Playback Volume",
1748*4882a593Smuzhiyun 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1749*4882a593Smuzhiyun 	.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1750*4882a593Smuzhiyun 		   SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1751*4882a593Smuzhiyun 	.info = snd_via8233_dxs_volume_info,
1752*4882a593Smuzhiyun 	.get = snd_via8233_pcmdxs_volume_get,
1753*4882a593Smuzhiyun 	.put = snd_via8233_pcmdxs_volume_put,
1754*4882a593Smuzhiyun 	.tlv = { .p = db_scale_dxs }
1755*4882a593Smuzhiyun };
1756*4882a593Smuzhiyun 
1757*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_via8233_dxs_volume_control = {
1758*4882a593Smuzhiyun 	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1759*4882a593Smuzhiyun 	.device = 0,
1760*4882a593Smuzhiyun 	/* .subdevice set later */
1761*4882a593Smuzhiyun 	.name = "PCM Playback Volume",
1762*4882a593Smuzhiyun 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
1763*4882a593Smuzhiyun 		  SNDRV_CTL_ELEM_ACCESS_TLV_READ |
1764*4882a593Smuzhiyun 		  SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1765*4882a593Smuzhiyun 	.info = snd_via8233_dxs_volume_info,
1766*4882a593Smuzhiyun 	.get = snd_via8233_dxs_volume_get,
1767*4882a593Smuzhiyun 	.put = snd_via8233_dxs_volume_put,
1768*4882a593Smuzhiyun 	.tlv = { .p = db_scale_dxs }
1769*4882a593Smuzhiyun };
1770*4882a593Smuzhiyun 
1771*4882a593Smuzhiyun /*
1772*4882a593Smuzhiyun  */
1773*4882a593Smuzhiyun 
snd_via82xx_mixer_free_ac97_bus(struct snd_ac97_bus * bus)1774*4882a593Smuzhiyun static void snd_via82xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1775*4882a593Smuzhiyun {
1776*4882a593Smuzhiyun 	struct via82xx *chip = bus->private_data;
1777*4882a593Smuzhiyun 	chip->ac97_bus = NULL;
1778*4882a593Smuzhiyun }
1779*4882a593Smuzhiyun 
snd_via82xx_mixer_free_ac97(struct snd_ac97 * ac97)1780*4882a593Smuzhiyun static void snd_via82xx_mixer_free_ac97(struct snd_ac97 *ac97)
1781*4882a593Smuzhiyun {
1782*4882a593Smuzhiyun 	struct via82xx *chip = ac97->private_data;
1783*4882a593Smuzhiyun 	chip->ac97 = NULL;
1784*4882a593Smuzhiyun }
1785*4882a593Smuzhiyun 
1786*4882a593Smuzhiyun static const struct ac97_quirk ac97_quirks[] = {
1787*4882a593Smuzhiyun 	{
1788*4882a593Smuzhiyun 		.subvendor = 0x1106,
1789*4882a593Smuzhiyun 		.subdevice = 0x4161,
1790*4882a593Smuzhiyun 		.codec_id = 0x56494161, /* VT1612A */
1791*4882a593Smuzhiyun 		.name = "Soltek SL-75DRV5",
1792*4882a593Smuzhiyun 		.type = AC97_TUNE_NONE
1793*4882a593Smuzhiyun 	},
1794*4882a593Smuzhiyun 	{	/* FIXME: which codec? */
1795*4882a593Smuzhiyun 		.subvendor = 0x1106,
1796*4882a593Smuzhiyun 		.subdevice = 0x4161,
1797*4882a593Smuzhiyun 		.name = "ASRock K7VT2",
1798*4882a593Smuzhiyun 		.type = AC97_TUNE_HP_ONLY
1799*4882a593Smuzhiyun 	},
1800*4882a593Smuzhiyun 	{
1801*4882a593Smuzhiyun 		.subvendor = 0x110a,
1802*4882a593Smuzhiyun 		.subdevice = 0x0079,
1803*4882a593Smuzhiyun 		.name = "Fujitsu Siemens D1289",
1804*4882a593Smuzhiyun 		.type = AC97_TUNE_HP_ONLY
1805*4882a593Smuzhiyun 	},
1806*4882a593Smuzhiyun 	{
1807*4882a593Smuzhiyun 		.subvendor = 0x1019,
1808*4882a593Smuzhiyun 		.subdevice = 0x0a81,
1809*4882a593Smuzhiyun 		.name = "ECS K7VTA3",
1810*4882a593Smuzhiyun 		.type = AC97_TUNE_HP_ONLY
1811*4882a593Smuzhiyun 	},
1812*4882a593Smuzhiyun 	{
1813*4882a593Smuzhiyun 		.subvendor = 0x1019,
1814*4882a593Smuzhiyun 		.subdevice = 0x0a85,
1815*4882a593Smuzhiyun 		.name = "ECS L7VMM2",
1816*4882a593Smuzhiyun 		.type = AC97_TUNE_HP_ONLY
1817*4882a593Smuzhiyun 	},
1818*4882a593Smuzhiyun 	{
1819*4882a593Smuzhiyun 		.subvendor = 0x1019,
1820*4882a593Smuzhiyun 		.subdevice = 0x1841,
1821*4882a593Smuzhiyun 		.name = "ECS K7VTA3",
1822*4882a593Smuzhiyun 		.type = AC97_TUNE_HP_ONLY
1823*4882a593Smuzhiyun 	},
1824*4882a593Smuzhiyun 	{
1825*4882a593Smuzhiyun 		.subvendor = 0x1849,
1826*4882a593Smuzhiyun 		.subdevice = 0x3059,
1827*4882a593Smuzhiyun 		.name = "ASRock K7VM2",
1828*4882a593Smuzhiyun 		.type = AC97_TUNE_HP_ONLY	/* VT1616 */
1829*4882a593Smuzhiyun 	},
1830*4882a593Smuzhiyun 	{
1831*4882a593Smuzhiyun 		.subvendor = 0x14cd,
1832*4882a593Smuzhiyun 		.subdevice = 0x7002,
1833*4882a593Smuzhiyun 		.name = "Unknown",
1834*4882a593Smuzhiyun 		.type = AC97_TUNE_ALC_JACK
1835*4882a593Smuzhiyun 	},
1836*4882a593Smuzhiyun 	{
1837*4882a593Smuzhiyun 		.subvendor = 0x1071,
1838*4882a593Smuzhiyun 		.subdevice = 0x8590,
1839*4882a593Smuzhiyun 		.name = "Mitac Mobo",
1840*4882a593Smuzhiyun 		.type = AC97_TUNE_ALC_JACK
1841*4882a593Smuzhiyun 	},
1842*4882a593Smuzhiyun 	{
1843*4882a593Smuzhiyun 		.subvendor = 0x161f,
1844*4882a593Smuzhiyun 		.subdevice = 0x202b,
1845*4882a593Smuzhiyun 		.name = "Arima Notebook",
1846*4882a593Smuzhiyun 		.type = AC97_TUNE_HP_ONLY,
1847*4882a593Smuzhiyun 	},
1848*4882a593Smuzhiyun 	{
1849*4882a593Smuzhiyun 		.subvendor = 0x161f,
1850*4882a593Smuzhiyun 		.subdevice = 0x2032,
1851*4882a593Smuzhiyun 		.name = "Targa Traveller 811",
1852*4882a593Smuzhiyun 		.type = AC97_TUNE_HP_ONLY,
1853*4882a593Smuzhiyun 	},
1854*4882a593Smuzhiyun 	{
1855*4882a593Smuzhiyun 		.subvendor = 0x161f,
1856*4882a593Smuzhiyun 		.subdevice = 0x2032,
1857*4882a593Smuzhiyun 		.name = "m680x",
1858*4882a593Smuzhiyun 		.type = AC97_TUNE_HP_ONLY, /* http://launchpad.net/bugs/38546 */
1859*4882a593Smuzhiyun 	},
1860*4882a593Smuzhiyun 	{
1861*4882a593Smuzhiyun 		.subvendor = 0x1297,
1862*4882a593Smuzhiyun 		.subdevice = 0xa232,
1863*4882a593Smuzhiyun 		.name = "Shuttle AK32VN",
1864*4882a593Smuzhiyun 		.type = AC97_TUNE_HP_ONLY
1865*4882a593Smuzhiyun 	},
1866*4882a593Smuzhiyun 	{ } /* terminator */
1867*4882a593Smuzhiyun };
1868*4882a593Smuzhiyun 
snd_via82xx_mixer_new(struct via82xx * chip,const char * quirk_override)1869*4882a593Smuzhiyun static int snd_via82xx_mixer_new(struct via82xx *chip, const char *quirk_override)
1870*4882a593Smuzhiyun {
1871*4882a593Smuzhiyun 	struct snd_ac97_template ac97;
1872*4882a593Smuzhiyun 	int err;
1873*4882a593Smuzhiyun 	static const struct snd_ac97_bus_ops ops = {
1874*4882a593Smuzhiyun 		.write = snd_via82xx_codec_write,
1875*4882a593Smuzhiyun 		.read = snd_via82xx_codec_read,
1876*4882a593Smuzhiyun 		.wait = snd_via82xx_codec_wait,
1877*4882a593Smuzhiyun 	};
1878*4882a593Smuzhiyun 
1879*4882a593Smuzhiyun 	if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1880*4882a593Smuzhiyun 		return err;
1881*4882a593Smuzhiyun 	chip->ac97_bus->private_free = snd_via82xx_mixer_free_ac97_bus;
1882*4882a593Smuzhiyun 	chip->ac97_bus->clock = chip->ac97_clock;
1883*4882a593Smuzhiyun 
1884*4882a593Smuzhiyun 	memset(&ac97, 0, sizeof(ac97));
1885*4882a593Smuzhiyun 	ac97.private_data = chip;
1886*4882a593Smuzhiyun 	ac97.private_free = snd_via82xx_mixer_free_ac97;
1887*4882a593Smuzhiyun 	ac97.pci = chip->pci;
1888*4882a593Smuzhiyun 	ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1889*4882a593Smuzhiyun 	if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1890*4882a593Smuzhiyun 		return err;
1891*4882a593Smuzhiyun 
1892*4882a593Smuzhiyun 	snd_ac97_tune_hardware(chip->ac97, ac97_quirks, quirk_override);
1893*4882a593Smuzhiyun 
1894*4882a593Smuzhiyun 	if (chip->chip_type != TYPE_VIA686) {
1895*4882a593Smuzhiyun 		/* use slot 10/11 */
1896*4882a593Smuzhiyun 		snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
1897*4882a593Smuzhiyun 	}
1898*4882a593Smuzhiyun 
1899*4882a593Smuzhiyun 	return 0;
1900*4882a593Smuzhiyun }
1901*4882a593Smuzhiyun 
1902*4882a593Smuzhiyun #ifdef SUPPORT_JOYSTICK
1903*4882a593Smuzhiyun #define JOYSTICK_ADDR	0x200
snd_via686_create_gameport(struct via82xx * chip,unsigned char * legacy)1904*4882a593Smuzhiyun static int snd_via686_create_gameport(struct via82xx *chip, unsigned char *legacy)
1905*4882a593Smuzhiyun {
1906*4882a593Smuzhiyun 	struct gameport *gp;
1907*4882a593Smuzhiyun 	struct resource *r;
1908*4882a593Smuzhiyun 
1909*4882a593Smuzhiyun 	if (!joystick)
1910*4882a593Smuzhiyun 		return -ENODEV;
1911*4882a593Smuzhiyun 
1912*4882a593Smuzhiyun 	r = request_region(JOYSTICK_ADDR, 8, "VIA686 gameport");
1913*4882a593Smuzhiyun 	if (!r) {
1914*4882a593Smuzhiyun 		dev_warn(chip->card->dev, "cannot reserve joystick port %#x\n",
1915*4882a593Smuzhiyun 		       JOYSTICK_ADDR);
1916*4882a593Smuzhiyun 		return -EBUSY;
1917*4882a593Smuzhiyun 	}
1918*4882a593Smuzhiyun 
1919*4882a593Smuzhiyun 	chip->gameport = gp = gameport_allocate_port();
1920*4882a593Smuzhiyun 	if (!gp) {
1921*4882a593Smuzhiyun 		dev_err(chip->card->dev,
1922*4882a593Smuzhiyun 			"cannot allocate memory for gameport\n");
1923*4882a593Smuzhiyun 		release_and_free_resource(r);
1924*4882a593Smuzhiyun 		return -ENOMEM;
1925*4882a593Smuzhiyun 	}
1926*4882a593Smuzhiyun 
1927*4882a593Smuzhiyun 	gameport_set_name(gp, "VIA686 Gameport");
1928*4882a593Smuzhiyun 	gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1929*4882a593Smuzhiyun 	gameport_set_dev_parent(gp, &chip->pci->dev);
1930*4882a593Smuzhiyun 	gp->io = JOYSTICK_ADDR;
1931*4882a593Smuzhiyun 	gameport_set_port_data(gp, r);
1932*4882a593Smuzhiyun 
1933*4882a593Smuzhiyun 	/* Enable legacy joystick port */
1934*4882a593Smuzhiyun 	*legacy |= VIA_FUNC_ENABLE_GAME;
1935*4882a593Smuzhiyun 	pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, *legacy);
1936*4882a593Smuzhiyun 
1937*4882a593Smuzhiyun 	gameport_register_port(chip->gameport);
1938*4882a593Smuzhiyun 
1939*4882a593Smuzhiyun 	return 0;
1940*4882a593Smuzhiyun }
1941*4882a593Smuzhiyun 
snd_via686_free_gameport(struct via82xx * chip)1942*4882a593Smuzhiyun static void snd_via686_free_gameport(struct via82xx *chip)
1943*4882a593Smuzhiyun {
1944*4882a593Smuzhiyun 	if (chip->gameport) {
1945*4882a593Smuzhiyun 		struct resource *r = gameport_get_port_data(chip->gameport);
1946*4882a593Smuzhiyun 
1947*4882a593Smuzhiyun 		gameport_unregister_port(chip->gameport);
1948*4882a593Smuzhiyun 		chip->gameport = NULL;
1949*4882a593Smuzhiyun 		release_and_free_resource(r);
1950*4882a593Smuzhiyun 	}
1951*4882a593Smuzhiyun }
1952*4882a593Smuzhiyun #else
snd_via686_create_gameport(struct via82xx * chip,unsigned char * legacy)1953*4882a593Smuzhiyun static inline int snd_via686_create_gameport(struct via82xx *chip, unsigned char *legacy)
1954*4882a593Smuzhiyun {
1955*4882a593Smuzhiyun 	return -ENOSYS;
1956*4882a593Smuzhiyun }
snd_via686_free_gameport(struct via82xx * chip)1957*4882a593Smuzhiyun static inline void snd_via686_free_gameport(struct via82xx *chip) { }
1958*4882a593Smuzhiyun #endif
1959*4882a593Smuzhiyun 
1960*4882a593Smuzhiyun 
1961*4882a593Smuzhiyun /*
1962*4882a593Smuzhiyun  *
1963*4882a593Smuzhiyun  */
1964*4882a593Smuzhiyun 
snd_via8233_init_misc(struct via82xx * chip)1965*4882a593Smuzhiyun static int snd_via8233_init_misc(struct via82xx *chip)
1966*4882a593Smuzhiyun {
1967*4882a593Smuzhiyun 	int i, err, caps;
1968*4882a593Smuzhiyun 	unsigned char val;
1969*4882a593Smuzhiyun 
1970*4882a593Smuzhiyun 	caps = chip->chip_type == TYPE_VIA8233A ? 1 : 2;
1971*4882a593Smuzhiyun 	for (i = 0; i < caps; i++) {
1972*4882a593Smuzhiyun 		snd_via8233_capture_source.index = i;
1973*4882a593Smuzhiyun 		err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_via8233_capture_source, chip));
1974*4882a593Smuzhiyun 		if (err < 0)
1975*4882a593Smuzhiyun 			return err;
1976*4882a593Smuzhiyun 	}
1977*4882a593Smuzhiyun 	if (ac97_can_spdif(chip->ac97)) {
1978*4882a593Smuzhiyun 		err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_via8233_dxs3_spdif_control, chip));
1979*4882a593Smuzhiyun 		if (err < 0)
1980*4882a593Smuzhiyun 			return err;
1981*4882a593Smuzhiyun 	}
1982*4882a593Smuzhiyun 	if (chip->chip_type != TYPE_VIA8233A) {
1983*4882a593Smuzhiyun 		/* when no h/w PCM volume control is found, use DXS volume control
1984*4882a593Smuzhiyun 		 * as the PCM vol control
1985*4882a593Smuzhiyun 		 */
1986*4882a593Smuzhiyun 		struct snd_ctl_elem_id sid;
1987*4882a593Smuzhiyun 		memset(&sid, 0, sizeof(sid));
1988*4882a593Smuzhiyun 		strcpy(sid.name, "PCM Playback Volume");
1989*4882a593Smuzhiyun 		sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1990*4882a593Smuzhiyun 		if (! snd_ctl_find_id(chip->card, &sid)) {
1991*4882a593Smuzhiyun 			dev_info(chip->card->dev,
1992*4882a593Smuzhiyun 				 "Using DXS as PCM Playback\n");
1993*4882a593Smuzhiyun 			err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_via8233_pcmdxs_volume_control, chip));
1994*4882a593Smuzhiyun 			if (err < 0)
1995*4882a593Smuzhiyun 				return err;
1996*4882a593Smuzhiyun 		}
1997*4882a593Smuzhiyun 		else /* Using DXS when PCM emulation is enabled is really weird */
1998*4882a593Smuzhiyun 		{
1999*4882a593Smuzhiyun 			for (i = 0; i < 4; ++i) {
2000*4882a593Smuzhiyun 				struct snd_kcontrol *kctl;
2001*4882a593Smuzhiyun 
2002*4882a593Smuzhiyun 				kctl = snd_ctl_new1(
2003*4882a593Smuzhiyun 					&snd_via8233_dxs_volume_control, chip);
2004*4882a593Smuzhiyun 				if (!kctl)
2005*4882a593Smuzhiyun 					return -ENOMEM;
2006*4882a593Smuzhiyun 				kctl->id.subdevice = i;
2007*4882a593Smuzhiyun 				err = snd_ctl_add(chip->card, kctl);
2008*4882a593Smuzhiyun 				if (err < 0)
2009*4882a593Smuzhiyun 					return err;
2010*4882a593Smuzhiyun 				chip->dxs_controls[i] = kctl;
2011*4882a593Smuzhiyun 			}
2012*4882a593Smuzhiyun 		}
2013*4882a593Smuzhiyun 	}
2014*4882a593Smuzhiyun 	/* select spdif data slot 10/11 */
2015*4882a593Smuzhiyun 	pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &val);
2016*4882a593Smuzhiyun 	val = (val & ~VIA8233_SPDIF_SLOT_MASK) | VIA8233_SPDIF_SLOT_1011;
2017*4882a593Smuzhiyun 	val &= ~VIA8233_SPDIF_DX3; /* SPDIF off as default */
2018*4882a593Smuzhiyun 	pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, val);
2019*4882a593Smuzhiyun 
2020*4882a593Smuzhiyun 	return 0;
2021*4882a593Smuzhiyun }
2022*4882a593Smuzhiyun 
snd_via686_init_misc(struct via82xx * chip)2023*4882a593Smuzhiyun static int snd_via686_init_misc(struct via82xx *chip)
2024*4882a593Smuzhiyun {
2025*4882a593Smuzhiyun 	unsigned char legacy, legacy_cfg;
2026*4882a593Smuzhiyun 	int rev_h = 0;
2027*4882a593Smuzhiyun 
2028*4882a593Smuzhiyun 	legacy = chip->old_legacy;
2029*4882a593Smuzhiyun 	legacy_cfg = chip->old_legacy_cfg;
2030*4882a593Smuzhiyun 	legacy |= VIA_FUNC_MIDI_IRQMASK;	/* FIXME: correct? (disable MIDI) */
2031*4882a593Smuzhiyun 	legacy &= ~VIA_FUNC_ENABLE_GAME;	/* disable joystick */
2032*4882a593Smuzhiyun 	if (chip->revision >= VIA_REV_686_H) {
2033*4882a593Smuzhiyun 		rev_h = 1;
2034*4882a593Smuzhiyun 		if (mpu_port >= 0x200) {	/* force MIDI */
2035*4882a593Smuzhiyun 			mpu_port &= 0xfffc;
2036*4882a593Smuzhiyun 			pci_write_config_dword(chip->pci, 0x18, mpu_port | 0x01);
2037*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
2038*4882a593Smuzhiyun 			chip->mpu_port_saved = mpu_port;
2039*4882a593Smuzhiyun #endif
2040*4882a593Smuzhiyun 		} else {
2041*4882a593Smuzhiyun 			mpu_port = pci_resource_start(chip->pci, 2);
2042*4882a593Smuzhiyun 		}
2043*4882a593Smuzhiyun 	} else {
2044*4882a593Smuzhiyun 		switch (mpu_port) {	/* force MIDI */
2045*4882a593Smuzhiyun 		case 0x300:
2046*4882a593Smuzhiyun 		case 0x310:
2047*4882a593Smuzhiyun 		case 0x320:
2048*4882a593Smuzhiyun 		case 0x330:
2049*4882a593Smuzhiyun 			legacy_cfg &= ~(3 << 2);
2050*4882a593Smuzhiyun 			legacy_cfg |= (mpu_port & 0x0030) >> 2;
2051*4882a593Smuzhiyun 			break;
2052*4882a593Smuzhiyun 		default:			/* no, use BIOS settings */
2053*4882a593Smuzhiyun 			if (legacy & VIA_FUNC_ENABLE_MIDI)
2054*4882a593Smuzhiyun 				mpu_port = 0x300 + ((legacy_cfg & 0x000c) << 2);
2055*4882a593Smuzhiyun 			break;
2056*4882a593Smuzhiyun 		}
2057*4882a593Smuzhiyun 	}
2058*4882a593Smuzhiyun 	if (mpu_port >= 0x200 &&
2059*4882a593Smuzhiyun 	    (chip->mpu_res = request_region(mpu_port, 2, "VIA82xx MPU401"))
2060*4882a593Smuzhiyun 	    != NULL) {
2061*4882a593Smuzhiyun 		if (rev_h)
2062*4882a593Smuzhiyun 			legacy |= VIA_FUNC_MIDI_PNP;	/* enable PCI I/O 2 */
2063*4882a593Smuzhiyun 		legacy |= VIA_FUNC_ENABLE_MIDI;
2064*4882a593Smuzhiyun 	} else {
2065*4882a593Smuzhiyun 		if (rev_h)
2066*4882a593Smuzhiyun 			legacy &= ~VIA_FUNC_MIDI_PNP;	/* disable PCI I/O 2 */
2067*4882a593Smuzhiyun 		legacy &= ~VIA_FUNC_ENABLE_MIDI;
2068*4882a593Smuzhiyun 		mpu_port = 0;
2069*4882a593Smuzhiyun 	}
2070*4882a593Smuzhiyun 
2071*4882a593Smuzhiyun 	pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, legacy);
2072*4882a593Smuzhiyun 	pci_write_config_byte(chip->pci, VIA_PNP_CONTROL, legacy_cfg);
2073*4882a593Smuzhiyun 	if (chip->mpu_res) {
2074*4882a593Smuzhiyun 		if (snd_mpu401_uart_new(chip->card, 0, MPU401_HW_VIA686A,
2075*4882a593Smuzhiyun 					mpu_port, MPU401_INFO_INTEGRATED |
2076*4882a593Smuzhiyun 					MPU401_INFO_IRQ_HOOK, -1,
2077*4882a593Smuzhiyun 					&chip->rmidi) < 0) {
2078*4882a593Smuzhiyun 			dev_warn(chip->card->dev,
2079*4882a593Smuzhiyun 				 "unable to initialize MPU-401 at 0x%lx, skipping\n",
2080*4882a593Smuzhiyun 				 mpu_port);
2081*4882a593Smuzhiyun 			legacy &= ~VIA_FUNC_ENABLE_MIDI;
2082*4882a593Smuzhiyun 		} else {
2083*4882a593Smuzhiyun 			legacy &= ~VIA_FUNC_MIDI_IRQMASK;	/* enable MIDI interrupt */
2084*4882a593Smuzhiyun 		}
2085*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, legacy);
2086*4882a593Smuzhiyun 	}
2087*4882a593Smuzhiyun 
2088*4882a593Smuzhiyun 	snd_via686_create_gameport(chip, &legacy);
2089*4882a593Smuzhiyun 
2090*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
2091*4882a593Smuzhiyun 	chip->legacy_saved = legacy;
2092*4882a593Smuzhiyun 	chip->legacy_cfg_saved = legacy_cfg;
2093*4882a593Smuzhiyun #endif
2094*4882a593Smuzhiyun 
2095*4882a593Smuzhiyun 	return 0;
2096*4882a593Smuzhiyun }
2097*4882a593Smuzhiyun 
2098*4882a593Smuzhiyun 
2099*4882a593Smuzhiyun /*
2100*4882a593Smuzhiyun  * proc interface
2101*4882a593Smuzhiyun  */
snd_via82xx_proc_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)2102*4882a593Smuzhiyun static void snd_via82xx_proc_read(struct snd_info_entry *entry,
2103*4882a593Smuzhiyun 				  struct snd_info_buffer *buffer)
2104*4882a593Smuzhiyun {
2105*4882a593Smuzhiyun 	struct via82xx *chip = entry->private_data;
2106*4882a593Smuzhiyun 	int i;
2107*4882a593Smuzhiyun 
2108*4882a593Smuzhiyun 	snd_iprintf(buffer, "%s\n\n", chip->card->longname);
2109*4882a593Smuzhiyun 	for (i = 0; i < 0xa0; i += 4) {
2110*4882a593Smuzhiyun 		snd_iprintf(buffer, "%02x: %08x\n", i, inl(chip->port + i));
2111*4882a593Smuzhiyun 	}
2112*4882a593Smuzhiyun }
2113*4882a593Smuzhiyun 
snd_via82xx_proc_init(struct via82xx * chip)2114*4882a593Smuzhiyun static void snd_via82xx_proc_init(struct via82xx *chip)
2115*4882a593Smuzhiyun {
2116*4882a593Smuzhiyun 	snd_card_ro_proc_new(chip->card, "via82xx", chip,
2117*4882a593Smuzhiyun 			     snd_via82xx_proc_read);
2118*4882a593Smuzhiyun }
2119*4882a593Smuzhiyun 
2120*4882a593Smuzhiyun /*
2121*4882a593Smuzhiyun  *
2122*4882a593Smuzhiyun  */
2123*4882a593Smuzhiyun 
snd_via82xx_chip_init(struct via82xx * chip)2124*4882a593Smuzhiyun static int snd_via82xx_chip_init(struct via82xx *chip)
2125*4882a593Smuzhiyun {
2126*4882a593Smuzhiyun 	unsigned int val;
2127*4882a593Smuzhiyun 	unsigned long end_time;
2128*4882a593Smuzhiyun 	unsigned char pval;
2129*4882a593Smuzhiyun 
2130*4882a593Smuzhiyun #if 0 /* broken on K7M? */
2131*4882a593Smuzhiyun 	if (chip->chip_type == TYPE_VIA686)
2132*4882a593Smuzhiyun 		/* disable all legacy ports */
2133*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, 0);
2134*4882a593Smuzhiyun #endif
2135*4882a593Smuzhiyun 	pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval);
2136*4882a593Smuzhiyun 	if (! (pval & VIA_ACLINK_C00_READY)) { /* codec not ready? */
2137*4882a593Smuzhiyun 		/* deassert ACLink reset, force SYNC */
2138*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL,
2139*4882a593Smuzhiyun 				      VIA_ACLINK_CTRL_ENABLE |
2140*4882a593Smuzhiyun 				      VIA_ACLINK_CTRL_RESET |
2141*4882a593Smuzhiyun 				      VIA_ACLINK_CTRL_SYNC);
2142*4882a593Smuzhiyun 		udelay(100);
2143*4882a593Smuzhiyun #if 1 /* FIXME: should we do full reset here for all chip models? */
2144*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, 0x00);
2145*4882a593Smuzhiyun 		udelay(100);
2146*4882a593Smuzhiyun #else
2147*4882a593Smuzhiyun 		/* deassert ACLink reset, force SYNC (warm AC'97 reset) */
2148*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL,
2149*4882a593Smuzhiyun 				      VIA_ACLINK_CTRL_RESET|VIA_ACLINK_CTRL_SYNC);
2150*4882a593Smuzhiyun 		udelay(2);
2151*4882a593Smuzhiyun #endif
2152*4882a593Smuzhiyun 		/* ACLink on, deassert ACLink reset, VSR, SGD data out */
2153*4882a593Smuzhiyun 		/* note - FM data out has trouble with non VRA codecs !! */
2154*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, VIA_ACLINK_CTRL_INIT);
2155*4882a593Smuzhiyun 		udelay(100);
2156*4882a593Smuzhiyun 	}
2157*4882a593Smuzhiyun 
2158*4882a593Smuzhiyun 	/* Make sure VRA is enabled, in case we didn't do a
2159*4882a593Smuzhiyun 	 * complete codec reset, above */
2160*4882a593Smuzhiyun 	pci_read_config_byte(chip->pci, VIA_ACLINK_CTRL, &pval);
2161*4882a593Smuzhiyun 	if ((pval & VIA_ACLINK_CTRL_INIT) != VIA_ACLINK_CTRL_INIT) {
2162*4882a593Smuzhiyun 		/* ACLink on, deassert ACLink reset, VSR, SGD data out */
2163*4882a593Smuzhiyun 		/* note - FM data out has trouble with non VRA codecs !! */
2164*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, VIA_ACLINK_CTRL_INIT);
2165*4882a593Smuzhiyun 		udelay(100);
2166*4882a593Smuzhiyun 	}
2167*4882a593Smuzhiyun 
2168*4882a593Smuzhiyun 	/* wait until codec ready */
2169*4882a593Smuzhiyun 	end_time = jiffies + msecs_to_jiffies(750);
2170*4882a593Smuzhiyun 	do {
2171*4882a593Smuzhiyun 		pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval);
2172*4882a593Smuzhiyun 		if (pval & VIA_ACLINK_C00_READY) /* primary codec ready */
2173*4882a593Smuzhiyun 			break;
2174*4882a593Smuzhiyun 		schedule_timeout_uninterruptible(1);
2175*4882a593Smuzhiyun 	} while (time_before(jiffies, end_time));
2176*4882a593Smuzhiyun 
2177*4882a593Smuzhiyun 	if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY)
2178*4882a593Smuzhiyun 		dev_err(chip->card->dev,
2179*4882a593Smuzhiyun 			"AC'97 codec is not ready [0x%x]\n", val);
2180*4882a593Smuzhiyun 
2181*4882a593Smuzhiyun #if 0 /* FIXME: we don't support the second codec yet so skip the detection now.. */
2182*4882a593Smuzhiyun 	snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
2183*4882a593Smuzhiyun 				 VIA_REG_AC97_SECONDARY_VALID |
2184*4882a593Smuzhiyun 				 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
2185*4882a593Smuzhiyun 	end_time = jiffies + msecs_to_jiffies(750);
2186*4882a593Smuzhiyun 	snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
2187*4882a593Smuzhiyun 				 VIA_REG_AC97_SECONDARY_VALID |
2188*4882a593Smuzhiyun 				 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
2189*4882a593Smuzhiyun 	do {
2190*4882a593Smuzhiyun 		if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_SECONDARY_VALID) {
2191*4882a593Smuzhiyun 			chip->ac97_secondary = 1;
2192*4882a593Smuzhiyun 			goto __ac97_ok2;
2193*4882a593Smuzhiyun 		}
2194*4882a593Smuzhiyun 		schedule_timeout_uninterruptible(1);
2195*4882a593Smuzhiyun 	} while (time_before(jiffies, end_time));
2196*4882a593Smuzhiyun 	/* This is ok, the most of motherboards have only one codec */
2197*4882a593Smuzhiyun 
2198*4882a593Smuzhiyun       __ac97_ok2:
2199*4882a593Smuzhiyun #endif
2200*4882a593Smuzhiyun 
2201*4882a593Smuzhiyun 	if (chip->chip_type == TYPE_VIA686) {
2202*4882a593Smuzhiyun 		/* route FM trap to IRQ, disable FM trap */
2203*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_FM_NMI_CTRL, 0);
2204*4882a593Smuzhiyun 		/* disable all GPI interrupts */
2205*4882a593Smuzhiyun 		outl(0, VIAREG(chip, GPI_INTR));
2206*4882a593Smuzhiyun 	}
2207*4882a593Smuzhiyun 
2208*4882a593Smuzhiyun 	if (chip->chip_type != TYPE_VIA686) {
2209*4882a593Smuzhiyun 		/* Workaround for Award BIOS bug:
2210*4882a593Smuzhiyun 		 * DXS channels don't work properly with VRA if MC97 is disabled.
2211*4882a593Smuzhiyun 		 */
2212*4882a593Smuzhiyun 		struct pci_dev *pci;
2213*4882a593Smuzhiyun 		pci = pci_get_device(0x1106, 0x3068, NULL); /* MC97 */
2214*4882a593Smuzhiyun 		if (pci) {
2215*4882a593Smuzhiyun 			unsigned char data;
2216*4882a593Smuzhiyun 			pci_read_config_byte(pci, 0x44, &data);
2217*4882a593Smuzhiyun 			pci_write_config_byte(pci, 0x44, data | 0x40);
2218*4882a593Smuzhiyun 			pci_dev_put(pci);
2219*4882a593Smuzhiyun 		}
2220*4882a593Smuzhiyun 	}
2221*4882a593Smuzhiyun 
2222*4882a593Smuzhiyun 	if (chip->chip_type != TYPE_VIA8233A) {
2223*4882a593Smuzhiyun 		int i, idx;
2224*4882a593Smuzhiyun 		for (idx = 0; idx < 4; idx++) {
2225*4882a593Smuzhiyun 			unsigned long port = chip->port + 0x10 * idx;
2226*4882a593Smuzhiyun 			for (i = 0; i < 2; i++) {
2227*4882a593Smuzhiyun 				chip->playback_volume[idx][i]=chip->playback_volume_c[i];
2228*4882a593Smuzhiyun 				outb(chip->playback_volume_c[i],
2229*4882a593Smuzhiyun 				     port + VIA_REG_OFS_PLAYBACK_VOLUME_L + i);
2230*4882a593Smuzhiyun 			}
2231*4882a593Smuzhiyun 		}
2232*4882a593Smuzhiyun 	}
2233*4882a593Smuzhiyun 
2234*4882a593Smuzhiyun 	return 0;
2235*4882a593Smuzhiyun }
2236*4882a593Smuzhiyun 
2237*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
2238*4882a593Smuzhiyun /*
2239*4882a593Smuzhiyun  * power management
2240*4882a593Smuzhiyun  */
snd_via82xx_suspend(struct device * dev)2241*4882a593Smuzhiyun static int snd_via82xx_suspend(struct device *dev)
2242*4882a593Smuzhiyun {
2243*4882a593Smuzhiyun 	struct snd_card *card = dev_get_drvdata(dev);
2244*4882a593Smuzhiyun 	struct via82xx *chip = card->private_data;
2245*4882a593Smuzhiyun 	int i;
2246*4882a593Smuzhiyun 
2247*4882a593Smuzhiyun 	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2248*4882a593Smuzhiyun 	for (i = 0; i < chip->num_devs; i++)
2249*4882a593Smuzhiyun 		snd_via82xx_channel_reset(chip, &chip->devs[i]);
2250*4882a593Smuzhiyun 	snd_ac97_suspend(chip->ac97);
2251*4882a593Smuzhiyun 
2252*4882a593Smuzhiyun 	/* save misc values */
2253*4882a593Smuzhiyun 	if (chip->chip_type != TYPE_VIA686) {
2254*4882a593Smuzhiyun 		pci_read_config_byte(chip->pci, VIA8233_SPDIF_CTRL, &chip->spdif_ctrl_saved);
2255*4882a593Smuzhiyun 		chip->capture_src_saved[0] = inb(chip->port + VIA_REG_CAPTURE_CHANNEL);
2256*4882a593Smuzhiyun 		chip->capture_src_saved[1] = inb(chip->port + VIA_REG_CAPTURE_CHANNEL + 0x10);
2257*4882a593Smuzhiyun 	}
2258*4882a593Smuzhiyun 
2259*4882a593Smuzhiyun 	return 0;
2260*4882a593Smuzhiyun }
2261*4882a593Smuzhiyun 
snd_via82xx_resume(struct device * dev)2262*4882a593Smuzhiyun static int snd_via82xx_resume(struct device *dev)
2263*4882a593Smuzhiyun {
2264*4882a593Smuzhiyun 	struct snd_card *card = dev_get_drvdata(dev);
2265*4882a593Smuzhiyun 	struct via82xx *chip = card->private_data;
2266*4882a593Smuzhiyun 	int i;
2267*4882a593Smuzhiyun 
2268*4882a593Smuzhiyun 	snd_via82xx_chip_init(chip);
2269*4882a593Smuzhiyun 
2270*4882a593Smuzhiyun 	if (chip->chip_type == TYPE_VIA686) {
2271*4882a593Smuzhiyun 		if (chip->mpu_port_saved)
2272*4882a593Smuzhiyun 			pci_write_config_dword(chip->pci, 0x18, chip->mpu_port_saved | 0x01);
2273*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, chip->legacy_saved);
2274*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_PNP_CONTROL, chip->legacy_cfg_saved);
2275*4882a593Smuzhiyun 	} else {
2276*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA8233_SPDIF_CTRL, chip->spdif_ctrl_saved);
2277*4882a593Smuzhiyun 		outb(chip->capture_src_saved[0], chip->port + VIA_REG_CAPTURE_CHANNEL);
2278*4882a593Smuzhiyun 		outb(chip->capture_src_saved[1], chip->port + VIA_REG_CAPTURE_CHANNEL + 0x10);
2279*4882a593Smuzhiyun 	}
2280*4882a593Smuzhiyun 
2281*4882a593Smuzhiyun 	snd_ac97_resume(chip->ac97);
2282*4882a593Smuzhiyun 
2283*4882a593Smuzhiyun 	for (i = 0; i < chip->num_devs; i++)
2284*4882a593Smuzhiyun 		snd_via82xx_channel_reset(chip, &chip->devs[i]);
2285*4882a593Smuzhiyun 
2286*4882a593Smuzhiyun 	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2287*4882a593Smuzhiyun 	return 0;
2288*4882a593Smuzhiyun }
2289*4882a593Smuzhiyun 
2290*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(snd_via82xx_pm, snd_via82xx_suspend, snd_via82xx_resume);
2291*4882a593Smuzhiyun #define SND_VIA82XX_PM_OPS	&snd_via82xx_pm
2292*4882a593Smuzhiyun #else
2293*4882a593Smuzhiyun #define SND_VIA82XX_PM_OPS	NULL
2294*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
2295*4882a593Smuzhiyun 
snd_via82xx_free(struct via82xx * chip)2296*4882a593Smuzhiyun static int snd_via82xx_free(struct via82xx *chip)
2297*4882a593Smuzhiyun {
2298*4882a593Smuzhiyun 	unsigned int i;
2299*4882a593Smuzhiyun 
2300*4882a593Smuzhiyun 	if (chip->irq < 0)
2301*4882a593Smuzhiyun 		goto __end_hw;
2302*4882a593Smuzhiyun 	/* disable interrupts */
2303*4882a593Smuzhiyun 	for (i = 0; i < chip->num_devs; i++)
2304*4882a593Smuzhiyun 		snd_via82xx_channel_reset(chip, &chip->devs[i]);
2305*4882a593Smuzhiyun 
2306*4882a593Smuzhiyun 	if (chip->irq >= 0)
2307*4882a593Smuzhiyun 		free_irq(chip->irq, chip);
2308*4882a593Smuzhiyun  __end_hw:
2309*4882a593Smuzhiyun 	release_and_free_resource(chip->mpu_res);
2310*4882a593Smuzhiyun 	pci_release_regions(chip->pci);
2311*4882a593Smuzhiyun 
2312*4882a593Smuzhiyun 	if (chip->chip_type == TYPE_VIA686) {
2313*4882a593Smuzhiyun 		snd_via686_free_gameport(chip);
2314*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE, chip->old_legacy);
2315*4882a593Smuzhiyun 		pci_write_config_byte(chip->pci, VIA_PNP_CONTROL, chip->old_legacy_cfg);
2316*4882a593Smuzhiyun 	}
2317*4882a593Smuzhiyun 	pci_disable_device(chip->pci);
2318*4882a593Smuzhiyun 	kfree(chip);
2319*4882a593Smuzhiyun 	return 0;
2320*4882a593Smuzhiyun }
2321*4882a593Smuzhiyun 
snd_via82xx_dev_free(struct snd_device * device)2322*4882a593Smuzhiyun static int snd_via82xx_dev_free(struct snd_device *device)
2323*4882a593Smuzhiyun {
2324*4882a593Smuzhiyun 	struct via82xx *chip = device->device_data;
2325*4882a593Smuzhiyun 	return snd_via82xx_free(chip);
2326*4882a593Smuzhiyun }
2327*4882a593Smuzhiyun 
snd_via82xx_create(struct snd_card * card,struct pci_dev * pci,int chip_type,int revision,unsigned int ac97_clock,struct via82xx ** r_via)2328*4882a593Smuzhiyun static int snd_via82xx_create(struct snd_card *card,
2329*4882a593Smuzhiyun 			      struct pci_dev *pci,
2330*4882a593Smuzhiyun 			      int chip_type,
2331*4882a593Smuzhiyun 			      int revision,
2332*4882a593Smuzhiyun 			      unsigned int ac97_clock,
2333*4882a593Smuzhiyun 			      struct via82xx **r_via)
2334*4882a593Smuzhiyun {
2335*4882a593Smuzhiyun 	struct via82xx *chip;
2336*4882a593Smuzhiyun 	int err;
2337*4882a593Smuzhiyun 	static const struct snd_device_ops ops = {
2338*4882a593Smuzhiyun 		.dev_free =	snd_via82xx_dev_free,
2339*4882a593Smuzhiyun         };
2340*4882a593Smuzhiyun 
2341*4882a593Smuzhiyun 	if ((err = pci_enable_device(pci)) < 0)
2342*4882a593Smuzhiyun 		return err;
2343*4882a593Smuzhiyun 
2344*4882a593Smuzhiyun 	if ((chip = kzalloc(sizeof(*chip), GFP_KERNEL)) == NULL) {
2345*4882a593Smuzhiyun 		pci_disable_device(pci);
2346*4882a593Smuzhiyun 		return -ENOMEM;
2347*4882a593Smuzhiyun 	}
2348*4882a593Smuzhiyun 
2349*4882a593Smuzhiyun 	chip->chip_type = chip_type;
2350*4882a593Smuzhiyun 	chip->revision = revision;
2351*4882a593Smuzhiyun 
2352*4882a593Smuzhiyun 	spin_lock_init(&chip->reg_lock);
2353*4882a593Smuzhiyun 	spin_lock_init(&chip->rates[0].lock);
2354*4882a593Smuzhiyun 	spin_lock_init(&chip->rates[1].lock);
2355*4882a593Smuzhiyun 	chip->card = card;
2356*4882a593Smuzhiyun 	chip->pci = pci;
2357*4882a593Smuzhiyun 	chip->irq = -1;
2358*4882a593Smuzhiyun 
2359*4882a593Smuzhiyun 	pci_read_config_byte(pci, VIA_FUNC_ENABLE, &chip->old_legacy);
2360*4882a593Smuzhiyun 	pci_read_config_byte(pci, VIA_PNP_CONTROL, &chip->old_legacy_cfg);
2361*4882a593Smuzhiyun 	pci_write_config_byte(chip->pci, VIA_FUNC_ENABLE,
2362*4882a593Smuzhiyun 			      chip->old_legacy & ~(VIA_FUNC_ENABLE_SB|VIA_FUNC_ENABLE_FM));
2363*4882a593Smuzhiyun 
2364*4882a593Smuzhiyun 	if ((err = pci_request_regions(pci, card->driver)) < 0) {
2365*4882a593Smuzhiyun 		kfree(chip);
2366*4882a593Smuzhiyun 		pci_disable_device(pci);
2367*4882a593Smuzhiyun 		return err;
2368*4882a593Smuzhiyun 	}
2369*4882a593Smuzhiyun 	chip->port = pci_resource_start(pci, 0);
2370*4882a593Smuzhiyun 	if (request_irq(pci->irq,
2371*4882a593Smuzhiyun 			chip_type == TYPE_VIA8233 ?
2372*4882a593Smuzhiyun 			snd_via8233_interrupt :	snd_via686_interrupt,
2373*4882a593Smuzhiyun 			IRQF_SHARED,
2374*4882a593Smuzhiyun 			KBUILD_MODNAME, chip)) {
2375*4882a593Smuzhiyun 		dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2376*4882a593Smuzhiyun 		snd_via82xx_free(chip);
2377*4882a593Smuzhiyun 		return -EBUSY;
2378*4882a593Smuzhiyun 	}
2379*4882a593Smuzhiyun 	chip->irq = pci->irq;
2380*4882a593Smuzhiyun 	card->sync_irq = chip->irq;
2381*4882a593Smuzhiyun 	if (ac97_clock >= 8000 && ac97_clock <= 48000)
2382*4882a593Smuzhiyun 		chip->ac97_clock = ac97_clock;
2383*4882a593Smuzhiyun 
2384*4882a593Smuzhiyun 	if ((err = snd_via82xx_chip_init(chip)) < 0) {
2385*4882a593Smuzhiyun 		snd_via82xx_free(chip);
2386*4882a593Smuzhiyun 		return err;
2387*4882a593Smuzhiyun 	}
2388*4882a593Smuzhiyun 
2389*4882a593Smuzhiyun 	if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2390*4882a593Smuzhiyun 		snd_via82xx_free(chip);
2391*4882a593Smuzhiyun 		return err;
2392*4882a593Smuzhiyun 	}
2393*4882a593Smuzhiyun 
2394*4882a593Smuzhiyun 	/* The 8233 ac97 controller does not implement the master bit
2395*4882a593Smuzhiyun 	 * in the pci command register. IMHO this is a violation of the PCI spec.
2396*4882a593Smuzhiyun 	 * We call pci_set_master here because it does not hurt. */
2397*4882a593Smuzhiyun 	pci_set_master(pci);
2398*4882a593Smuzhiyun 
2399*4882a593Smuzhiyun 	*r_via = chip;
2400*4882a593Smuzhiyun 	return 0;
2401*4882a593Smuzhiyun }
2402*4882a593Smuzhiyun 
2403*4882a593Smuzhiyun struct via823x_info {
2404*4882a593Smuzhiyun 	int revision;
2405*4882a593Smuzhiyun 	char *name;
2406*4882a593Smuzhiyun 	int type;
2407*4882a593Smuzhiyun };
2408*4882a593Smuzhiyun static const struct via823x_info via823x_cards[] = {
2409*4882a593Smuzhiyun 	{ VIA_REV_PRE_8233, "VIA 8233-Pre", TYPE_VIA8233 },
2410*4882a593Smuzhiyun 	{ VIA_REV_8233C, "VIA 8233C", TYPE_VIA8233 },
2411*4882a593Smuzhiyun 	{ VIA_REV_8233, "VIA 8233", TYPE_VIA8233 },
2412*4882a593Smuzhiyun 	{ VIA_REV_8233A, "VIA 8233A", TYPE_VIA8233A },
2413*4882a593Smuzhiyun 	{ VIA_REV_8235, "VIA 8235", TYPE_VIA8233 },
2414*4882a593Smuzhiyun 	{ VIA_REV_8237, "VIA 8237", TYPE_VIA8233 },
2415*4882a593Smuzhiyun 	{ VIA_REV_8251, "VIA 8251", TYPE_VIA8233 },
2416*4882a593Smuzhiyun };
2417*4882a593Smuzhiyun 
2418*4882a593Smuzhiyun /*
2419*4882a593Smuzhiyun  * auto detection of DXS channel supports.
2420*4882a593Smuzhiyun  */
2421*4882a593Smuzhiyun 
2422*4882a593Smuzhiyun static const struct snd_pci_quirk dxs_allowlist[] = {
2423*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1005, 0x4710, "Avance Logic Mobo", VIA_DXS_ENABLE),
2424*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1019, 0x0996, "ESC Mobo", VIA_DXS_48K),
2425*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1019, 0x0a81, "ECS K7VTA3 v8.0", VIA_DXS_NO_VRA),
2426*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1019, 0x0a85, "ECS L7VMM2", VIA_DXS_NO_VRA),
2427*4882a593Smuzhiyun 	SND_PCI_QUIRK_VENDOR(0x1019, "ESC K8", VIA_DXS_SRC),
2428*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1019, 0xaa01, "ESC K8T890-A", VIA_DXS_SRC),
2429*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1025, 0x0033, "Acer Inspire 1353LM", VIA_DXS_NO_VRA),
2430*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1025, 0x0046, "Acer Aspire 1524 WLMi", VIA_DXS_SRC),
2431*4882a593Smuzhiyun 	SND_PCI_QUIRK_VENDOR(0x1043, "ASUS A7/A8", VIA_DXS_NO_VRA),
2432*4882a593Smuzhiyun 	SND_PCI_QUIRK_VENDOR(0x1071, "Diverse Notebook", VIA_DXS_NO_VRA),
2433*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x10cf, 0x118e, "FSC Laptop", VIA_DXS_ENABLE),
2434*4882a593Smuzhiyun 	SND_PCI_QUIRK_VENDOR(0x1106, "ASRock", VIA_DXS_SRC),
2435*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1297, 0xa231, "Shuttle AK31v2", VIA_DXS_SRC),
2436*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1297, 0xa232, "Shuttle", VIA_DXS_SRC),
2437*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1297, 0xc160, "Shuttle Sk41G", VIA_DXS_SRC),
2438*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte GA-7VAXP", VIA_DXS_ENABLE),
2439*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1462, 0x3800, "MSI KT266", VIA_DXS_ENABLE),
2440*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1462, 0x7120, "MSI KT4V", VIA_DXS_ENABLE),
2441*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1462, 0x7142, "MSI K8MM-V", VIA_DXS_ENABLE),
2442*4882a593Smuzhiyun 	SND_PCI_QUIRK_VENDOR(0x1462, "MSI Mobo", VIA_DXS_SRC),
2443*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x147b, 0x1401, "ABIT KD7(-RAID)", VIA_DXS_ENABLE),
2444*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x147b, 0x1411, "ABIT VA-20", VIA_DXS_ENABLE),
2445*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x147b, 0x1413, "ABIT KV8 Pro", VIA_DXS_ENABLE),
2446*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x147b, 0x1415, "ABIT AV8", VIA_DXS_NO_VRA),
2447*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x14ff, 0x0403, "Twinhead mobo", VIA_DXS_ENABLE),
2448*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x14ff, 0x0408, "Twinhead laptop", VIA_DXS_SRC),
2449*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1558, 0x4701, "Clevo D470", VIA_DXS_SRC),
2450*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1584, 0x8120, "Diverse Laptop", VIA_DXS_ENABLE),
2451*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1584, 0x8123, "Targa/Uniwill", VIA_DXS_NO_VRA),
2452*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x161f, 0x202b, "Amira Notebook", VIA_DXS_NO_VRA),
2453*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x161f, 0x2032, "m680x machines", VIA_DXS_48K),
2454*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1631, 0xe004, "PB EasyNote 3174", VIA_DXS_ENABLE),
2455*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1695, 0x3005, "EPoX EP-8K9A", VIA_DXS_ENABLE),
2456*4882a593Smuzhiyun 	SND_PCI_QUIRK_VENDOR(0x1695, "EPoX mobo", VIA_DXS_SRC),
2457*4882a593Smuzhiyun 	SND_PCI_QUIRK_VENDOR(0x16f3, "Jetway K8", VIA_DXS_SRC),
2458*4882a593Smuzhiyun 	SND_PCI_QUIRK_VENDOR(0x1734, "FSC Laptop", VIA_DXS_SRC),
2459*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1849, 0x3059, "ASRock K7VM2", VIA_DXS_NO_VRA),
2460*4882a593Smuzhiyun 	SND_PCI_QUIRK_VENDOR(0x1849, "ASRock mobo", VIA_DXS_SRC),
2461*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x1919, 0x200a, "Soltek SL-K8",  VIA_DXS_NO_VRA),
2462*4882a593Smuzhiyun 	SND_PCI_QUIRK(0x4005, 0x4710, "MSI K7T266", VIA_DXS_SRC),
2463*4882a593Smuzhiyun 	{ } /* terminator */
2464*4882a593Smuzhiyun };
2465*4882a593Smuzhiyun 
check_dxs_list(struct pci_dev * pci,int revision)2466*4882a593Smuzhiyun static int check_dxs_list(struct pci_dev *pci, int revision)
2467*4882a593Smuzhiyun {
2468*4882a593Smuzhiyun 	const struct snd_pci_quirk *w;
2469*4882a593Smuzhiyun 
2470*4882a593Smuzhiyun 	w = snd_pci_quirk_lookup(pci, dxs_allowlist);
2471*4882a593Smuzhiyun 	if (w) {
2472*4882a593Smuzhiyun 		dev_dbg(&pci->dev, "DXS allow list for %s found\n",
2473*4882a593Smuzhiyun 			    snd_pci_quirk_name(w));
2474*4882a593Smuzhiyun 		return w->value;
2475*4882a593Smuzhiyun 	}
2476*4882a593Smuzhiyun 
2477*4882a593Smuzhiyun 	/* for newer revision, default to DXS_SRC */
2478*4882a593Smuzhiyun 	if (revision >= VIA_REV_8235)
2479*4882a593Smuzhiyun 		return VIA_DXS_SRC;
2480*4882a593Smuzhiyun 
2481*4882a593Smuzhiyun 	/*
2482*4882a593Smuzhiyun 	 * not detected, try 48k rate only to be sure.
2483*4882a593Smuzhiyun 	 */
2484*4882a593Smuzhiyun 	dev_info(&pci->dev, "Assuming DXS channels with 48k fixed sample rate.\n");
2485*4882a593Smuzhiyun 	dev_info(&pci->dev, "         Please try dxs_support=5 option\n");
2486*4882a593Smuzhiyun 	dev_info(&pci->dev, "         and report if it works on your machine.\n");
2487*4882a593Smuzhiyun 	dev_info(&pci->dev, "         For more details, read ALSA-Configuration.txt.\n");
2488*4882a593Smuzhiyun 	return VIA_DXS_48K;
2489*4882a593Smuzhiyun };
2490*4882a593Smuzhiyun 
snd_via82xx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2491*4882a593Smuzhiyun static int snd_via82xx_probe(struct pci_dev *pci,
2492*4882a593Smuzhiyun 			     const struct pci_device_id *pci_id)
2493*4882a593Smuzhiyun {
2494*4882a593Smuzhiyun 	struct snd_card *card;
2495*4882a593Smuzhiyun 	struct via82xx *chip;
2496*4882a593Smuzhiyun 	int chip_type = 0, card_type;
2497*4882a593Smuzhiyun 	unsigned int i;
2498*4882a593Smuzhiyun 	int err;
2499*4882a593Smuzhiyun 
2500*4882a593Smuzhiyun 	err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
2501*4882a593Smuzhiyun 	if (err < 0)
2502*4882a593Smuzhiyun 		return err;
2503*4882a593Smuzhiyun 
2504*4882a593Smuzhiyun 	card_type = pci_id->driver_data;
2505*4882a593Smuzhiyun 	switch (card_type) {
2506*4882a593Smuzhiyun 	case TYPE_CARD_VIA686:
2507*4882a593Smuzhiyun 		strcpy(card->driver, "VIA686A");
2508*4882a593Smuzhiyun 		sprintf(card->shortname, "VIA 82C686A/B rev%x", pci->revision);
2509*4882a593Smuzhiyun 		chip_type = TYPE_VIA686;
2510*4882a593Smuzhiyun 		break;
2511*4882a593Smuzhiyun 	case TYPE_CARD_VIA8233:
2512*4882a593Smuzhiyun 		chip_type = TYPE_VIA8233;
2513*4882a593Smuzhiyun 		sprintf(card->shortname, "VIA 823x rev%x", pci->revision);
2514*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(via823x_cards); i++) {
2515*4882a593Smuzhiyun 			if (pci->revision == via823x_cards[i].revision) {
2516*4882a593Smuzhiyun 				chip_type = via823x_cards[i].type;
2517*4882a593Smuzhiyun 				strcpy(card->shortname, via823x_cards[i].name);
2518*4882a593Smuzhiyun 				break;
2519*4882a593Smuzhiyun 			}
2520*4882a593Smuzhiyun 		}
2521*4882a593Smuzhiyun 		if (chip_type != TYPE_VIA8233A) {
2522*4882a593Smuzhiyun 			if (dxs_support == VIA_DXS_AUTO)
2523*4882a593Smuzhiyun 				dxs_support = check_dxs_list(pci, pci->revision);
2524*4882a593Smuzhiyun 			/* force to use VIA8233 or 8233A model according to
2525*4882a593Smuzhiyun 			 * dxs_support module option
2526*4882a593Smuzhiyun 			 */
2527*4882a593Smuzhiyun 			if (dxs_support == VIA_DXS_DISABLE)
2528*4882a593Smuzhiyun 				chip_type = TYPE_VIA8233A;
2529*4882a593Smuzhiyun 			else
2530*4882a593Smuzhiyun 				chip_type = TYPE_VIA8233;
2531*4882a593Smuzhiyun 		}
2532*4882a593Smuzhiyun 		if (chip_type == TYPE_VIA8233A)
2533*4882a593Smuzhiyun 			strcpy(card->driver, "VIA8233A");
2534*4882a593Smuzhiyun 		else if (pci->revision >= VIA_REV_8237)
2535*4882a593Smuzhiyun 			strcpy(card->driver, "VIA8237"); /* no slog assignment */
2536*4882a593Smuzhiyun 		else
2537*4882a593Smuzhiyun 			strcpy(card->driver, "VIA8233");
2538*4882a593Smuzhiyun 		break;
2539*4882a593Smuzhiyun 	default:
2540*4882a593Smuzhiyun 		dev_err(card->dev, "invalid card type %d\n", card_type);
2541*4882a593Smuzhiyun 		err = -EINVAL;
2542*4882a593Smuzhiyun 		goto __error;
2543*4882a593Smuzhiyun 	}
2544*4882a593Smuzhiyun 
2545*4882a593Smuzhiyun 	if ((err = snd_via82xx_create(card, pci, chip_type, pci->revision,
2546*4882a593Smuzhiyun 				      ac97_clock, &chip)) < 0)
2547*4882a593Smuzhiyun 		goto __error;
2548*4882a593Smuzhiyun 	card->private_data = chip;
2549*4882a593Smuzhiyun 	if ((err = snd_via82xx_mixer_new(chip, ac97_quirk)) < 0)
2550*4882a593Smuzhiyun 		goto __error;
2551*4882a593Smuzhiyun 
2552*4882a593Smuzhiyun 	if (chip_type == TYPE_VIA686) {
2553*4882a593Smuzhiyun 		if ((err = snd_via686_pcm_new(chip)) < 0 ||
2554*4882a593Smuzhiyun 		    (err = snd_via686_init_misc(chip)) < 0)
2555*4882a593Smuzhiyun 			goto __error;
2556*4882a593Smuzhiyun 	} else {
2557*4882a593Smuzhiyun 		if (chip_type == TYPE_VIA8233A) {
2558*4882a593Smuzhiyun 			if ((err = snd_via8233a_pcm_new(chip)) < 0)
2559*4882a593Smuzhiyun 				goto __error;
2560*4882a593Smuzhiyun 			// chip->dxs_fixed = 1; /* FIXME: use 48k for DXS #3? */
2561*4882a593Smuzhiyun 		} else {
2562*4882a593Smuzhiyun 			if ((err = snd_via8233_pcm_new(chip)) < 0)
2563*4882a593Smuzhiyun 				goto __error;
2564*4882a593Smuzhiyun 			if (dxs_support == VIA_DXS_48K)
2565*4882a593Smuzhiyun 				chip->dxs_fixed = 1;
2566*4882a593Smuzhiyun 			else if (dxs_support == VIA_DXS_NO_VRA)
2567*4882a593Smuzhiyun 				chip->no_vra = 1;
2568*4882a593Smuzhiyun 			else if (dxs_support == VIA_DXS_SRC) {
2569*4882a593Smuzhiyun 				chip->no_vra = 1;
2570*4882a593Smuzhiyun 				chip->dxs_src = 1;
2571*4882a593Smuzhiyun 			}
2572*4882a593Smuzhiyun 		}
2573*4882a593Smuzhiyun 		if ((err = snd_via8233_init_misc(chip)) < 0)
2574*4882a593Smuzhiyun 			goto __error;
2575*4882a593Smuzhiyun 	}
2576*4882a593Smuzhiyun 
2577*4882a593Smuzhiyun 	/* disable interrupts */
2578*4882a593Smuzhiyun 	for (i = 0; i < chip->num_devs; i++)
2579*4882a593Smuzhiyun 		snd_via82xx_channel_reset(chip, &chip->devs[i]);
2580*4882a593Smuzhiyun 
2581*4882a593Smuzhiyun 	snprintf(card->longname, sizeof(card->longname),
2582*4882a593Smuzhiyun 		 "%s with %s at %#lx, irq %d", card->shortname,
2583*4882a593Smuzhiyun 		 snd_ac97_get_short_name(chip->ac97), chip->port, chip->irq);
2584*4882a593Smuzhiyun 
2585*4882a593Smuzhiyun 	snd_via82xx_proc_init(chip);
2586*4882a593Smuzhiyun 
2587*4882a593Smuzhiyun 	if ((err = snd_card_register(card)) < 0) {
2588*4882a593Smuzhiyun 		snd_card_free(card);
2589*4882a593Smuzhiyun 		return err;
2590*4882a593Smuzhiyun 	}
2591*4882a593Smuzhiyun 	pci_set_drvdata(pci, card);
2592*4882a593Smuzhiyun 	return 0;
2593*4882a593Smuzhiyun 
2594*4882a593Smuzhiyun  __error:
2595*4882a593Smuzhiyun 	snd_card_free(card);
2596*4882a593Smuzhiyun 	return err;
2597*4882a593Smuzhiyun }
2598*4882a593Smuzhiyun 
snd_via82xx_remove(struct pci_dev * pci)2599*4882a593Smuzhiyun static void snd_via82xx_remove(struct pci_dev *pci)
2600*4882a593Smuzhiyun {
2601*4882a593Smuzhiyun 	snd_card_free(pci_get_drvdata(pci));
2602*4882a593Smuzhiyun }
2603*4882a593Smuzhiyun 
2604*4882a593Smuzhiyun static struct pci_driver via82xx_driver = {
2605*4882a593Smuzhiyun 	.name = KBUILD_MODNAME,
2606*4882a593Smuzhiyun 	.id_table = snd_via82xx_ids,
2607*4882a593Smuzhiyun 	.probe = snd_via82xx_probe,
2608*4882a593Smuzhiyun 	.remove = snd_via82xx_remove,
2609*4882a593Smuzhiyun 	.driver = {
2610*4882a593Smuzhiyun 		.pm = SND_VIA82XX_PM_OPS,
2611*4882a593Smuzhiyun 	},
2612*4882a593Smuzhiyun };
2613*4882a593Smuzhiyun 
2614*4882a593Smuzhiyun module_pci_driver(via82xx_driver);
2615