1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun #ifndef __SOUND_TRIDENT_H 3*4882a593Smuzhiyun #define __SOUND_TRIDENT_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * audio@tridentmicro.com 7*4882a593Smuzhiyun * Fri Feb 19 15:55:28 MST 1999 8*4882a593Smuzhiyun * Definitions for Trident 4DWave DX/NX chips 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <sound/pcm.h> 12*4882a593Smuzhiyun #include <sound/mpu401.h> 13*4882a593Smuzhiyun #include <sound/ac97_codec.h> 14*4882a593Smuzhiyun #include <sound/util_mem.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define TRIDENT_DEVICE_ID_DX ((PCI_VENDOR_ID_TRIDENT<<16)|PCI_DEVICE_ID_TRIDENT_4DWAVE_DX) 17*4882a593Smuzhiyun #define TRIDENT_DEVICE_ID_NX ((PCI_VENDOR_ID_TRIDENT<<16)|PCI_DEVICE_ID_TRIDENT_4DWAVE_NX) 18*4882a593Smuzhiyun #define TRIDENT_DEVICE_ID_SI7018 ((PCI_VENDOR_ID_SI<<16)|PCI_DEVICE_ID_SI_7018) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define SNDRV_TRIDENT_VOICE_TYPE_PCM 0 21*4882a593Smuzhiyun #define SNDRV_TRIDENT_VOICE_TYPE_SYNTH 1 22*4882a593Smuzhiyun #define SNDRV_TRIDENT_VOICE_TYPE_MIDI 2 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define SNDRV_TRIDENT_VFLG_RUNNING (1<<0) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* TLB code constants */ 27*4882a593Smuzhiyun #define SNDRV_TRIDENT_PAGE_SIZE 4096 28*4882a593Smuzhiyun #define SNDRV_TRIDENT_PAGE_SHIFT 12 29*4882a593Smuzhiyun #define SNDRV_TRIDENT_PAGE_MASK ((1<<SNDRV_TRIDENT_PAGE_SHIFT)-1) 30*4882a593Smuzhiyun #define SNDRV_TRIDENT_MAX_PAGES 4096 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * Direct registers 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define TRID_REG(trident, x) ((trident)->port + (x)) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define ID_4DWAVE_DX 0x2000 39*4882a593Smuzhiyun #define ID_4DWAVE_NX 0x2001 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Bank definitions */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define T4D_BANK_A 0 44*4882a593Smuzhiyun #define T4D_BANK_B 1 45*4882a593Smuzhiyun #define T4D_NUM_BANKS 2 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Register definitions */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Global registers */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun enum global_control_bits { 52*4882a593Smuzhiyun CHANNEL_IDX = 0x0000003f, 53*4882a593Smuzhiyun OVERRUN_IE = 0x00000400, /* interrupt enable: capture overrun */ 54*4882a593Smuzhiyun UNDERRUN_IE = 0x00000800, /* interrupt enable: playback underrun */ 55*4882a593Smuzhiyun ENDLP_IE = 0x00001000, /* interrupt enable: end of buffer */ 56*4882a593Smuzhiyun MIDLP_IE = 0x00002000, /* interrupt enable: middle buffer */ 57*4882a593Smuzhiyun ETOG_IE = 0x00004000, /* interrupt enable: envelope toggling */ 58*4882a593Smuzhiyun EDROP_IE = 0x00008000, /* interrupt enable: envelope drop */ 59*4882a593Smuzhiyun BANK_B_EN = 0x00010000, /* SiS: enable bank B (64 channels) */ 60*4882a593Smuzhiyun PCMIN_B_MIX = 0x00020000, /* SiS: PCM IN B mixing enable */ 61*4882a593Smuzhiyun I2S_OUT_ASSIGN = 0x00040000, /* SiS: I2S Out contains surround PCM */ 62*4882a593Smuzhiyun SPDIF_OUT_ASSIGN= 0x00080000, /* SiS: 0=S/PDIF L/R | 1=PCM Out FIFO */ 63*4882a593Smuzhiyun MAIN_OUT_ASSIGN = 0x00100000, /* SiS: 0=PCM Out FIFO | 1=MMC Out buffer */ 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun enum miscint_bits { 67*4882a593Smuzhiyun PB_UNDERRUN_IRQ = 0x00000001, REC_OVERRUN_IRQ = 0x00000002, 68*4882a593Smuzhiyun SB_IRQ = 0x00000004, MPU401_IRQ = 0x00000008, 69*4882a593Smuzhiyun OPL3_IRQ = 0x00000010, ADDRESS_IRQ = 0x00000020, 70*4882a593Smuzhiyun ENVELOPE_IRQ = 0x00000040, PB_UNDERRUN = 0x00000100, 71*4882a593Smuzhiyun REC_OVERRUN = 0x00000200, MIXER_UNDERFLOW = 0x00000400, 72*4882a593Smuzhiyun MIXER_OVERFLOW = 0x00000800, NX_SB_IRQ_DISABLE = 0x00001000, 73*4882a593Smuzhiyun ST_TARGET_REACHED = 0x00008000, 74*4882a593Smuzhiyun PB_24K_MODE = 0x00010000, ST_IRQ_EN = 0x00800000, 75*4882a593Smuzhiyun ACGPIO_IRQ = 0x01000000 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* T2 legacy dma control registers. */ 79*4882a593Smuzhiyun #define LEGACY_DMAR0 0x00 // ADR0 80*4882a593Smuzhiyun #define LEGACY_DMAR4 0x04 // CNT0 81*4882a593Smuzhiyun #define LEGACY_DMAR6 0x06 // CNT0 - High bits 82*4882a593Smuzhiyun #define LEGACY_DMAR11 0x0b // MOD 83*4882a593Smuzhiyun #define LEGACY_DMAR15 0x0f // MMR 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define T4D_START_A 0x80 86*4882a593Smuzhiyun #define T4D_STOP_A 0x84 87*4882a593Smuzhiyun #define T4D_DLY_A 0x88 88*4882a593Smuzhiyun #define T4D_SIGN_CSO_A 0x8c 89*4882a593Smuzhiyun #define T4D_CSPF_A 0x90 90*4882a593Smuzhiyun #define T4D_CSPF_B 0xbc 91*4882a593Smuzhiyun #define T4D_CEBC_A 0x94 92*4882a593Smuzhiyun #define T4D_AINT_A 0x98 93*4882a593Smuzhiyun #define T4D_AINTEN_A 0x9c 94*4882a593Smuzhiyun #define T4D_LFO_GC_CIR 0xa0 95*4882a593Smuzhiyun #define T4D_MUSICVOL_WAVEVOL 0xa8 96*4882a593Smuzhiyun #define T4D_SBDELTA_DELTA_R 0xac 97*4882a593Smuzhiyun #define T4D_MISCINT 0xb0 98*4882a593Smuzhiyun #define T4D_START_B 0xb4 99*4882a593Smuzhiyun #define T4D_STOP_B 0xb8 100*4882a593Smuzhiyun #define T4D_SBBL_SBCL 0xc0 101*4882a593Smuzhiyun #define T4D_SBCTRL_SBE2R_SBDD 0xc4 102*4882a593Smuzhiyun #define T4D_STIMER 0xc8 103*4882a593Smuzhiyun #define T4D_AINT_B 0xd8 104*4882a593Smuzhiyun #define T4D_AINTEN_B 0xdc 105*4882a593Smuzhiyun #define T4D_RCI 0x70 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* MPU-401 UART */ 108*4882a593Smuzhiyun #define T4D_MPU401_BASE 0x20 109*4882a593Smuzhiyun #define T4D_MPUR0 0x20 110*4882a593Smuzhiyun #define T4D_MPUR1 0x21 111*4882a593Smuzhiyun #define T4D_MPUR2 0x22 112*4882a593Smuzhiyun #define T4D_MPUR3 0x23 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* S/PDIF Registers */ 115*4882a593Smuzhiyun #define NX_SPCTRL_SPCSO 0x24 116*4882a593Smuzhiyun #define NX_SPLBA 0x28 117*4882a593Smuzhiyun #define NX_SPESO 0x2c 118*4882a593Smuzhiyun #define NX_SPCSTATUS 0x64 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* Joystick */ 121*4882a593Smuzhiyun #define GAMEPORT_GCR 0x30 122*4882a593Smuzhiyun #define GAMEPORT_MODE_ADC 0x80 123*4882a593Smuzhiyun #define GAMEPORT_LEGACY 0x31 124*4882a593Smuzhiyun #define GAMEPORT_AXES 0x34 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* NX Specific Registers */ 127*4882a593Smuzhiyun #define NX_TLBC 0x6c 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* Channel Registers */ 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define CH_START 0xe0 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define CH_DX_CSO_ALPHA_FMS 0xe0 134*4882a593Smuzhiyun #define CH_DX_ESO_DELTA 0xe8 135*4882a593Smuzhiyun #define CH_DX_FMC_RVOL_CVOL 0xec 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define CH_NX_DELTA_CSO 0xe0 138*4882a593Smuzhiyun #define CH_NX_DELTA_ESO 0xe8 139*4882a593Smuzhiyun #define CH_NX_ALPHA_FMS_FMC_RVOL_CVOL 0xec 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define CH_LBA 0xe4 142*4882a593Smuzhiyun #define CH_GVSEL_PAN_VOL_CTRL_EC 0xf0 143*4882a593Smuzhiyun #define CH_EBUF1 0xf4 144*4882a593Smuzhiyun #define CH_EBUF2 0xf8 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* AC-97 Registers */ 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define DX_ACR0_AC97_W 0x40 149*4882a593Smuzhiyun #define DX_ACR1_AC97_R 0x44 150*4882a593Smuzhiyun #define DX_ACR2_AC97_COM_STAT 0x48 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define NX_ACR0_AC97_COM_STAT 0x40 153*4882a593Smuzhiyun #define NX_ACR1_AC97_W 0x44 154*4882a593Smuzhiyun #define NX_ACR2_AC97_R_PRIMARY 0x48 155*4882a593Smuzhiyun #define NX_ACR3_AC97_R_SECONDARY 0x4c 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define SI_AC97_WRITE 0x40 158*4882a593Smuzhiyun #define SI_AC97_READ 0x44 159*4882a593Smuzhiyun #define SI_SERIAL_INTF_CTRL 0x48 160*4882a593Smuzhiyun #define SI_AC97_GPIO 0x4c 161*4882a593Smuzhiyun #define SI_ASR0 0x50 162*4882a593Smuzhiyun #define SI_SPDIF_CS 0x70 163*4882a593Smuzhiyun #define SI_GPIO 0x7c 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun enum trident_nx_ac97_bits { 166*4882a593Smuzhiyun /* ACR1-3 */ 167*4882a593Smuzhiyun NX_AC97_BUSY_WRITE = 0x0800, 168*4882a593Smuzhiyun NX_AC97_BUSY_READ = 0x0800, 169*4882a593Smuzhiyun NX_AC97_BUSY_DATA = 0x0400, 170*4882a593Smuzhiyun NX_AC97_WRITE_SECONDARY = 0x0100, 171*4882a593Smuzhiyun /* ACR0 */ 172*4882a593Smuzhiyun NX_AC97_SECONDARY_READY = 0x0040, 173*4882a593Smuzhiyun NX_AC97_SECONDARY_RECORD = 0x0020, 174*4882a593Smuzhiyun NX_AC97_SURROUND_OUTPUT = 0x0010, 175*4882a593Smuzhiyun NX_AC97_PRIMARY_READY = 0x0008, 176*4882a593Smuzhiyun NX_AC97_PRIMARY_RECORD = 0x0004, 177*4882a593Smuzhiyun NX_AC97_PCM_OUTPUT = 0x0002, 178*4882a593Smuzhiyun NX_AC97_WARM_RESET = 0x0001 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun enum trident_dx_ac97_bits { 182*4882a593Smuzhiyun DX_AC97_BUSY_WRITE = 0x8000, 183*4882a593Smuzhiyun DX_AC97_BUSY_READ = 0x8000, 184*4882a593Smuzhiyun DX_AC97_READY = 0x0010, 185*4882a593Smuzhiyun DX_AC97_RECORD = 0x0008, 186*4882a593Smuzhiyun DX_AC97_PLAYBACK = 0x0002 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun enum sis7018_ac97_bits { 190*4882a593Smuzhiyun SI_AC97_BUSY_WRITE = 0x00008000, 191*4882a593Smuzhiyun SI_AC97_AUDIO_BUSY = 0x00004000, 192*4882a593Smuzhiyun SI_AC97_MODEM_BUSY = 0x00002000, 193*4882a593Smuzhiyun SI_AC97_BUSY_READ = 0x00008000, 194*4882a593Smuzhiyun SI_AC97_SECONDARY = 0x00000080, 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun enum serial_intf_ctrl_bits { 198*4882a593Smuzhiyun WARM_RESET = 0x00000001, 199*4882a593Smuzhiyun COLD_RESET = 0x00000002, 200*4882a593Smuzhiyun I2S_CLOCK = 0x00000004, 201*4882a593Smuzhiyun PCM_SEC_AC97 = 0x00000008, 202*4882a593Smuzhiyun AC97_DBL_RATE = 0x00000010, 203*4882a593Smuzhiyun SPDIF_EN = 0x00000020, 204*4882a593Smuzhiyun I2S_OUTPUT_EN = 0x00000040, 205*4882a593Smuzhiyun I2S_INPUT_EN = 0x00000080, 206*4882a593Smuzhiyun PCMIN = 0x00000100, 207*4882a593Smuzhiyun LINE1IN = 0x00000200, 208*4882a593Smuzhiyun MICIN = 0x00000400, 209*4882a593Smuzhiyun LINE2IN = 0x00000800, 210*4882a593Smuzhiyun HEAD_SET_IN = 0x00001000, 211*4882a593Smuzhiyun GPIOIN = 0x00002000, 212*4882a593Smuzhiyun /* 7018 spec says id = 01 but the demo board routed to 10 213*4882a593Smuzhiyun SECONDARY_ID= 0x00004000, */ 214*4882a593Smuzhiyun SECONDARY_ID = 0x00004000, 215*4882a593Smuzhiyun PCMOUT = 0x00010000, 216*4882a593Smuzhiyun SURROUT = 0x00020000, 217*4882a593Smuzhiyun CENTEROUT = 0x00040000, 218*4882a593Smuzhiyun LFEOUT = 0x00080000, 219*4882a593Smuzhiyun LINE1OUT = 0x00100000, 220*4882a593Smuzhiyun LINE2OUT = 0x00200000, 221*4882a593Smuzhiyun GPIOOUT = 0x00400000, 222*4882a593Smuzhiyun SI_AC97_PRIMARY_READY = 0x01000000, 223*4882a593Smuzhiyun SI_AC97_SECONDARY_READY = 0x02000000, 224*4882a593Smuzhiyun SI_AC97_POWERDOWN = 0x04000000, 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun /* PCM defaults */ 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun #define T4D_DEFAULT_PCM_VOL 10 /* 0 - 255 */ 230*4882a593Smuzhiyun #define T4D_DEFAULT_PCM_PAN 0 /* 0 - 127 */ 231*4882a593Smuzhiyun #define T4D_DEFAULT_PCM_RVOL 127 /* 0 - 127 */ 232*4882a593Smuzhiyun #define T4D_DEFAULT_PCM_CVOL 127 /* 0 - 127 */ 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun struct snd_trident; 235*4882a593Smuzhiyun struct snd_trident_voice; 236*4882a593Smuzhiyun struct snd_trident_pcm_mixer; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun struct snd_trident_port { 239*4882a593Smuzhiyun struct snd_midi_channel_set * chset; 240*4882a593Smuzhiyun struct snd_trident * trident; 241*4882a593Smuzhiyun int mode; /* operation mode */ 242*4882a593Smuzhiyun int client; /* sequencer client number */ 243*4882a593Smuzhiyun int port; /* sequencer port number */ 244*4882a593Smuzhiyun unsigned int midi_has_voices: 1; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun struct snd_trident_memblk_arg { 248*4882a593Smuzhiyun short first_page, last_page; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun struct snd_trident_tlb { 252*4882a593Smuzhiyun __le32 *entries; /* 16k-aligned TLB table */ 253*4882a593Smuzhiyun dma_addr_t entries_dmaaddr; /* 16k-aligned PCI address to TLB table */ 254*4882a593Smuzhiyun unsigned long * shadow_entries; /* shadow entries with virtual addresses */ 255*4882a593Smuzhiyun struct snd_dma_buffer buffer; 256*4882a593Smuzhiyun struct snd_util_memhdr * memhdr; /* page allocation list */ 257*4882a593Smuzhiyun struct snd_dma_buffer silent_page; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun struct snd_trident_voice { 261*4882a593Smuzhiyun unsigned int number; 262*4882a593Smuzhiyun unsigned int use: 1, 263*4882a593Smuzhiyun pcm: 1, 264*4882a593Smuzhiyun synth:1, 265*4882a593Smuzhiyun midi: 1; 266*4882a593Smuzhiyun unsigned int flags; 267*4882a593Smuzhiyun unsigned char client; 268*4882a593Smuzhiyun unsigned char port; 269*4882a593Smuzhiyun unsigned char index; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun struct snd_trident_sample_ops *sample_ops; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /* channel parameters */ 274*4882a593Smuzhiyun unsigned int CSO; /* 24 bits (16 on DX) */ 275*4882a593Smuzhiyun unsigned int ESO; /* 24 bits (16 on DX) */ 276*4882a593Smuzhiyun unsigned int LBA; /* 30 bits */ 277*4882a593Smuzhiyun unsigned short EC; /* 12 bits */ 278*4882a593Smuzhiyun unsigned short Alpha; /* 12 bits */ 279*4882a593Smuzhiyun unsigned short Delta; /* 16 bits */ 280*4882a593Smuzhiyun unsigned short Attribute; /* 16 bits - SiS 7018 */ 281*4882a593Smuzhiyun unsigned short Vol; /* 12 bits (6.6) */ 282*4882a593Smuzhiyun unsigned char Pan; /* 7 bits (1.4.2) */ 283*4882a593Smuzhiyun unsigned char GVSel; /* 1 bit */ 284*4882a593Smuzhiyun unsigned char RVol; /* 7 bits (5.2) */ 285*4882a593Smuzhiyun unsigned char CVol; /* 7 bits (5.2) */ 286*4882a593Smuzhiyun unsigned char FMC; /* 2 bits */ 287*4882a593Smuzhiyun unsigned char CTRL; /* 4 bits */ 288*4882a593Smuzhiyun unsigned char FMS; /* 4 bits */ 289*4882a593Smuzhiyun unsigned char LFO; /* 8 bits */ 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun unsigned int negCSO; /* nonzero - use negative CSO */ 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun struct snd_util_memblk *memblk; /* memory block if TLB enabled */ 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun /* PCM data */ 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun struct snd_trident *trident; 298*4882a593Smuzhiyun struct snd_pcm_substream *substream; 299*4882a593Smuzhiyun struct snd_trident_voice *extra; /* extra PCM voice (acts as interrupt generator) */ 300*4882a593Smuzhiyun unsigned int running: 1, 301*4882a593Smuzhiyun capture: 1, 302*4882a593Smuzhiyun spdif: 1, 303*4882a593Smuzhiyun foldback: 1, 304*4882a593Smuzhiyun isync: 1, 305*4882a593Smuzhiyun isync2: 1, 306*4882a593Smuzhiyun isync3: 1; 307*4882a593Smuzhiyun int foldback_chan; /* foldback subdevice number */ 308*4882a593Smuzhiyun unsigned int stimer; /* global sample timer (to detect spurious interrupts) */ 309*4882a593Smuzhiyun unsigned int spurious_threshold; /* spurious threshold */ 310*4882a593Smuzhiyun unsigned int isync_mark; 311*4882a593Smuzhiyun unsigned int isync_max; 312*4882a593Smuzhiyun unsigned int isync_ESO; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* --- */ 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun void *private_data; 317*4882a593Smuzhiyun void (*private_free)(struct snd_trident_voice *voice); 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun struct snd_4dwave { 321*4882a593Smuzhiyun int seq_client; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun struct snd_trident_port seq_ports[4]; 324*4882a593Smuzhiyun struct snd_trident_voice voices[64]; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun int ChanSynthCount; /* number of allocated synth channels */ 327*4882a593Smuzhiyun int max_size; /* maximum synth memory size in bytes */ 328*4882a593Smuzhiyun int current_size; /* current allocated synth mem in bytes */ 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun struct snd_trident_pcm_mixer { 332*4882a593Smuzhiyun struct snd_trident_voice *voice; /* active voice */ 333*4882a593Smuzhiyun unsigned short vol; /* front volume */ 334*4882a593Smuzhiyun unsigned char pan; /* pan control */ 335*4882a593Smuzhiyun unsigned char rvol; /* rear volume */ 336*4882a593Smuzhiyun unsigned char cvol; /* center volume */ 337*4882a593Smuzhiyun unsigned char pad; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun struct snd_trident { 341*4882a593Smuzhiyun int irq; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun unsigned int device; /* device ID */ 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun unsigned char bDMAStart; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun unsigned long port; 348*4882a593Smuzhiyun unsigned long midi_port; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun unsigned int spurious_irq_count; 351*4882a593Smuzhiyun unsigned int spurious_irq_max_delta; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun struct snd_trident_tlb tlb; /* TLB entries for NX cards */ 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun unsigned char spdif_ctrl; 356*4882a593Smuzhiyun unsigned char spdif_pcm_ctrl; 357*4882a593Smuzhiyun unsigned int spdif_bits; 358*4882a593Smuzhiyun unsigned int spdif_pcm_bits; 359*4882a593Smuzhiyun struct snd_kcontrol *spdif_pcm_ctl; /* S/PDIF settings */ 360*4882a593Smuzhiyun unsigned int ac97_ctrl; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun unsigned int ChanMap[2]; /* allocation map for hardware channels */ 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun int ChanPCM; /* max number of PCM channels */ 365*4882a593Smuzhiyun int ChanPCMcnt; /* actual number of PCM channels */ 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun unsigned int ac97_detect: 1; /* 1 = AC97 in detection phase */ 368*4882a593Smuzhiyun unsigned int in_suspend: 1; /* 1 during suspend/resume */ 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun struct snd_4dwave synth; /* synth specific variables */ 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun spinlock_t event_lock; 373*4882a593Smuzhiyun spinlock_t voice_alloc; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun struct snd_dma_device dma_dev; 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun struct pci_dev *pci; 378*4882a593Smuzhiyun struct snd_card *card; 379*4882a593Smuzhiyun struct snd_pcm *pcm; /* ADC/DAC PCM */ 380*4882a593Smuzhiyun struct snd_pcm *foldback; /* Foldback PCM */ 381*4882a593Smuzhiyun struct snd_pcm *spdif; /* SPDIF PCM */ 382*4882a593Smuzhiyun struct snd_rawmidi *rmidi; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun struct snd_ac97_bus *ac97_bus; 385*4882a593Smuzhiyun struct snd_ac97 *ac97; 386*4882a593Smuzhiyun struct snd_ac97 *ac97_sec; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun unsigned int musicvol_wavevol; 389*4882a593Smuzhiyun struct snd_trident_pcm_mixer pcm_mixer[32]; 390*4882a593Smuzhiyun struct snd_kcontrol *ctl_vol; /* front volume */ 391*4882a593Smuzhiyun struct snd_kcontrol *ctl_pan; /* pan */ 392*4882a593Smuzhiyun struct snd_kcontrol *ctl_rvol; /* rear volume */ 393*4882a593Smuzhiyun struct snd_kcontrol *ctl_cvol; /* center volume */ 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun spinlock_t reg_lock; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun struct gameport *gameport; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun int snd_trident_create(struct snd_card *card, 401*4882a593Smuzhiyun struct pci_dev *pci, 402*4882a593Smuzhiyun int pcm_streams, 403*4882a593Smuzhiyun int pcm_spdif_device, 404*4882a593Smuzhiyun int max_wavetable_size, 405*4882a593Smuzhiyun struct snd_trident ** rtrident); 406*4882a593Smuzhiyun int snd_trident_create_gameport(struct snd_trident *trident); 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun int snd_trident_pcm(struct snd_trident *trident, int device); 409*4882a593Smuzhiyun int snd_trident_foldback_pcm(struct snd_trident *trident, int device); 410*4882a593Smuzhiyun int snd_trident_spdif_pcm(struct snd_trident *trident, int device); 411*4882a593Smuzhiyun int snd_trident_attach_synthesizer(struct snd_trident * trident); 412*4882a593Smuzhiyun struct snd_trident_voice *snd_trident_alloc_voice(struct snd_trident * trident, int type, 413*4882a593Smuzhiyun int client, int port); 414*4882a593Smuzhiyun void snd_trident_free_voice(struct snd_trident * trident, struct snd_trident_voice *voice); 415*4882a593Smuzhiyun void snd_trident_start_voice(struct snd_trident * trident, unsigned int voice); 416*4882a593Smuzhiyun void snd_trident_stop_voice(struct snd_trident * trident, unsigned int voice); 417*4882a593Smuzhiyun void snd_trident_write_voice_regs(struct snd_trident * trident, struct snd_trident_voice *voice); 418*4882a593Smuzhiyun extern const struct dev_pm_ops snd_trident_pm; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun /* TLB memory allocation */ 421*4882a593Smuzhiyun struct snd_util_memblk *snd_trident_alloc_pages(struct snd_trident *trident, 422*4882a593Smuzhiyun struct snd_pcm_substream *substream); 423*4882a593Smuzhiyun int snd_trident_free_pages(struct snd_trident *trident, struct snd_util_memblk *blk); 424*4882a593Smuzhiyun struct snd_util_memblk *snd_trident_synth_alloc(struct snd_trident *trident, unsigned int size); 425*4882a593Smuzhiyun int snd_trident_synth_free(struct snd_trident *trident, struct snd_util_memblk *blk); 426*4882a593Smuzhiyun int snd_trident_synth_copy_from_user(struct snd_trident *trident, struct snd_util_memblk *blk, 427*4882a593Smuzhiyun int offset, const char __user *data, int size); 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun #endif /* __SOUND_TRIDENT_H */ 430