1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for SiS7019 Audio Accelerator
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2004-2007, David Dillow
6*4882a593Smuzhiyun * Written by David Dillow <dave@thedillows.org>
7*4882a593Smuzhiyun * Inspired by the Trident 4D-WaveDX/NX driver.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * All rights reserved.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/pci.h>
14*4882a593Smuzhiyun #include <linux/time.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/delay.h>
19*4882a593Smuzhiyun #include <sound/core.h>
20*4882a593Smuzhiyun #include <sound/ac97_codec.h>
21*4882a593Smuzhiyun #include <sound/initval.h>
22*4882a593Smuzhiyun #include "sis7019.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
25*4882a593Smuzhiyun MODULE_DESCRIPTION("SiS7019");
26*4882a593Smuzhiyun MODULE_LICENSE("GPL");
27*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{{SiS,SiS7019 Audio Accelerator}}");
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
30*4882a593Smuzhiyun static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
31*4882a593Smuzhiyun static bool enable = 1;
32*4882a593Smuzhiyun static int codecs = 1;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun module_param(index, int, 0444);
35*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for SiS7019 Audio Accelerator.");
36*4882a593Smuzhiyun module_param(id, charp, 0444);
37*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for SiS7019 Audio Accelerator.");
38*4882a593Smuzhiyun module_param(enable, bool, 0444);
39*4882a593Smuzhiyun MODULE_PARM_DESC(enable, "Enable SiS7019 Audio Accelerator.");
40*4882a593Smuzhiyun module_param(codecs, int, 0444);
41*4882a593Smuzhiyun MODULE_PARM_DESC(codecs, "Set bit to indicate that codec number is expected to be present (default 1)");
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static const struct pci_device_id snd_sis7019_ids[] = {
44*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x7019) },
45*4882a593Smuzhiyun { 0, }
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, snd_sis7019_ids);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* There are three timing modes for the voices.
51*4882a593Smuzhiyun *
52*4882a593Smuzhiyun * For both playback and capture, when the buffer is one or two periods long,
53*4882a593Smuzhiyun * we use the hardware's built-in Mid-Loop Interrupt and End-Loop Interrupt
54*4882a593Smuzhiyun * to let us know when the periods have ended.
55*4882a593Smuzhiyun *
56*4882a593Smuzhiyun * When performing playback with more than two periods per buffer, we set
57*4882a593Smuzhiyun * the "Stop Sample Offset" and tell the hardware to interrupt us when we
58*4882a593Smuzhiyun * reach it. We then update the offset and continue on until we are
59*4882a593Smuzhiyun * interrupted for the next period.
60*4882a593Smuzhiyun *
61*4882a593Smuzhiyun * Capture channels do not have a SSO, so we allocate a playback channel to
62*4882a593Smuzhiyun * use as a timer for the capture periods. We use the SSO on the playback
63*4882a593Smuzhiyun * channel to clock out virtual periods, and adjust the virtual period length
64*4882a593Smuzhiyun * to maintain synchronization. This algorithm came from the Trident driver.
65*4882a593Smuzhiyun *
66*4882a593Smuzhiyun * FIXME: It'd be nice to make use of some of the synth features in the
67*4882a593Smuzhiyun * hardware, but a woeful lack of documentation is a significant roadblock.
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun struct voice {
70*4882a593Smuzhiyun u16 flags;
71*4882a593Smuzhiyun #define VOICE_IN_USE 1
72*4882a593Smuzhiyun #define VOICE_CAPTURE 2
73*4882a593Smuzhiyun #define VOICE_SSO_TIMING 4
74*4882a593Smuzhiyun #define VOICE_SYNC_TIMING 8
75*4882a593Smuzhiyun u16 sync_cso;
76*4882a593Smuzhiyun u16 period_size;
77*4882a593Smuzhiyun u16 buffer_size;
78*4882a593Smuzhiyun u16 sync_period_size;
79*4882a593Smuzhiyun u16 sync_buffer_size;
80*4882a593Smuzhiyun u32 sso;
81*4882a593Smuzhiyun u32 vperiod;
82*4882a593Smuzhiyun struct snd_pcm_substream *substream;
83*4882a593Smuzhiyun struct voice *timing;
84*4882a593Smuzhiyun void __iomem *ctrl_base;
85*4882a593Smuzhiyun void __iomem *wave_base;
86*4882a593Smuzhiyun void __iomem *sync_base;
87*4882a593Smuzhiyun int num;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* We need four pages to store our wave parameters during a suspend. If
91*4882a593Smuzhiyun * we're not doing power management, we still need to allocate a page
92*4882a593Smuzhiyun * for the silence buffer.
93*4882a593Smuzhiyun */
94*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
95*4882a593Smuzhiyun #define SIS_SUSPEND_PAGES 4
96*4882a593Smuzhiyun #else
97*4882a593Smuzhiyun #define SIS_SUSPEND_PAGES 1
98*4882a593Smuzhiyun #endif
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun struct sis7019 {
101*4882a593Smuzhiyun unsigned long ioport;
102*4882a593Smuzhiyun void __iomem *ioaddr;
103*4882a593Smuzhiyun int irq;
104*4882a593Smuzhiyun int codecs_present;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun struct pci_dev *pci;
107*4882a593Smuzhiyun struct snd_pcm *pcm;
108*4882a593Smuzhiyun struct snd_card *card;
109*4882a593Smuzhiyun struct snd_ac97 *ac97[3];
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Protect against more than one thread hitting the AC97
112*4882a593Smuzhiyun * registers (in a more polite manner than pounding the hardware
113*4882a593Smuzhiyun * semaphore)
114*4882a593Smuzhiyun */
115*4882a593Smuzhiyun struct mutex ac97_mutex;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* voice_lock protects allocation/freeing of the voice descriptions
118*4882a593Smuzhiyun */
119*4882a593Smuzhiyun spinlock_t voice_lock;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun struct voice voices[64];
122*4882a593Smuzhiyun struct voice capture_voice;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* Allocate pages to store the internal wave state during
125*4882a593Smuzhiyun * suspends. When we're operating, this can be used as a silence
126*4882a593Smuzhiyun * buffer for a timing channel.
127*4882a593Smuzhiyun */
128*4882a593Smuzhiyun void *suspend_state[SIS_SUSPEND_PAGES];
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun int silence_users;
131*4882a593Smuzhiyun dma_addr_t silence_dma_addr;
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* These values are also used by the module param 'codecs' to indicate
135*4882a593Smuzhiyun * which codecs should be present.
136*4882a593Smuzhiyun */
137*4882a593Smuzhiyun #define SIS_PRIMARY_CODEC_PRESENT 0x0001
138*4882a593Smuzhiyun #define SIS_SECONDARY_CODEC_PRESENT 0x0002
139*4882a593Smuzhiyun #define SIS_TERTIARY_CODEC_PRESENT 0x0004
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /* The HW offset parameters (Loop End, Stop Sample, End Sample) have a
142*4882a593Smuzhiyun * documented range of 8-0xfff8 samples. Given that they are 0-based,
143*4882a593Smuzhiyun * that places our period/buffer range at 9-0xfff9 samples. That makes the
144*4882a593Smuzhiyun * max buffer size 0xfff9 samples * 2 channels * 2 bytes per sample, and
145*4882a593Smuzhiyun * max samples / min samples gives us the max periods in a buffer.
146*4882a593Smuzhiyun *
147*4882a593Smuzhiyun * We'll add a constraint upon open that limits the period and buffer sample
148*4882a593Smuzhiyun * size to values that are legal for the hardware.
149*4882a593Smuzhiyun */
150*4882a593Smuzhiyun static const struct snd_pcm_hardware sis_playback_hw_info = {
151*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP |
152*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
153*4882a593Smuzhiyun SNDRV_PCM_INFO_INTERLEAVED |
154*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
155*4882a593Smuzhiyun SNDRV_PCM_INFO_SYNC_START |
156*4882a593Smuzhiyun SNDRV_PCM_INFO_RESUME),
157*4882a593Smuzhiyun .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
158*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE),
159*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_CONTINUOUS,
160*4882a593Smuzhiyun .rate_min = 4000,
161*4882a593Smuzhiyun .rate_max = 48000,
162*4882a593Smuzhiyun .channels_min = 1,
163*4882a593Smuzhiyun .channels_max = 2,
164*4882a593Smuzhiyun .buffer_bytes_max = (0xfff9 * 4),
165*4882a593Smuzhiyun .period_bytes_min = 9,
166*4882a593Smuzhiyun .period_bytes_max = (0xfff9 * 4),
167*4882a593Smuzhiyun .periods_min = 1,
168*4882a593Smuzhiyun .periods_max = (0xfff9 / 9),
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static const struct snd_pcm_hardware sis_capture_hw_info = {
172*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP |
173*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
174*4882a593Smuzhiyun SNDRV_PCM_INFO_INTERLEAVED |
175*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
176*4882a593Smuzhiyun SNDRV_PCM_INFO_SYNC_START |
177*4882a593Smuzhiyun SNDRV_PCM_INFO_RESUME),
178*4882a593Smuzhiyun .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
179*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE),
180*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_48000,
181*4882a593Smuzhiyun .rate_min = 4000,
182*4882a593Smuzhiyun .rate_max = 48000,
183*4882a593Smuzhiyun .channels_min = 1,
184*4882a593Smuzhiyun .channels_max = 2,
185*4882a593Smuzhiyun .buffer_bytes_max = (0xfff9 * 4),
186*4882a593Smuzhiyun .period_bytes_min = 9,
187*4882a593Smuzhiyun .period_bytes_max = (0xfff9 * 4),
188*4882a593Smuzhiyun .periods_min = 1,
189*4882a593Smuzhiyun .periods_max = (0xfff9 / 9),
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
sis_update_sso(struct voice * voice,u16 period)192*4882a593Smuzhiyun static void sis_update_sso(struct voice *voice, u16 period)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun void __iomem *base = voice->ctrl_base;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun voice->sso += period;
197*4882a593Smuzhiyun if (voice->sso >= voice->buffer_size)
198*4882a593Smuzhiyun voice->sso -= voice->buffer_size;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun /* Enforce the documented hardware minimum offset */
201*4882a593Smuzhiyun if (voice->sso < 8)
202*4882a593Smuzhiyun voice->sso = 8;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* The SSO is in the upper 16 bits of the register. */
205*4882a593Smuzhiyun writew(voice->sso & 0xffff, base + SIS_PLAY_DMA_SSO_ESO + 2);
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
sis_update_voice(struct voice * voice)208*4882a593Smuzhiyun static void sis_update_voice(struct voice *voice)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun if (voice->flags & VOICE_SSO_TIMING) {
211*4882a593Smuzhiyun sis_update_sso(voice, voice->period_size);
212*4882a593Smuzhiyun } else if (voice->flags & VOICE_SYNC_TIMING) {
213*4882a593Smuzhiyun int sync;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /* If we've not hit the end of the virtual period, update
216*4882a593Smuzhiyun * our records and keep going.
217*4882a593Smuzhiyun */
218*4882a593Smuzhiyun if (voice->vperiod > voice->period_size) {
219*4882a593Smuzhiyun voice->vperiod -= voice->period_size;
220*4882a593Smuzhiyun if (voice->vperiod < voice->period_size)
221*4882a593Smuzhiyun sis_update_sso(voice, voice->vperiod);
222*4882a593Smuzhiyun else
223*4882a593Smuzhiyun sis_update_sso(voice, voice->period_size);
224*4882a593Smuzhiyun return;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun /* Calculate our relative offset between the target and
228*4882a593Smuzhiyun * the actual CSO value. Since we're operating in a loop,
229*4882a593Smuzhiyun * if the value is more than half way around, we can
230*4882a593Smuzhiyun * consider ourselves wrapped.
231*4882a593Smuzhiyun */
232*4882a593Smuzhiyun sync = voice->sync_cso;
233*4882a593Smuzhiyun sync -= readw(voice->sync_base + SIS_CAPTURE_DMA_FORMAT_CSO);
234*4882a593Smuzhiyun if (sync > (voice->sync_buffer_size / 2))
235*4882a593Smuzhiyun sync -= voice->sync_buffer_size;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /* If sync is positive, then we interrupted too early, and
238*4882a593Smuzhiyun * we'll need to come back in a few samples and try again.
239*4882a593Smuzhiyun * There's a minimum wait, as it takes some time for the DMA
240*4882a593Smuzhiyun * engine to startup, etc...
241*4882a593Smuzhiyun */
242*4882a593Smuzhiyun if (sync > 0) {
243*4882a593Smuzhiyun if (sync < 16)
244*4882a593Smuzhiyun sync = 16;
245*4882a593Smuzhiyun sis_update_sso(voice, sync);
246*4882a593Smuzhiyun return;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /* Ok, we interrupted right on time, or (hopefully) just
250*4882a593Smuzhiyun * a bit late. We'll adjst our next waiting period based
251*4882a593Smuzhiyun * on how close we got.
252*4882a593Smuzhiyun *
253*4882a593Smuzhiyun * We need to stay just behind the actual channel to ensure
254*4882a593Smuzhiyun * it really is past a period when we get our interrupt --
255*4882a593Smuzhiyun * otherwise we'll fall into the early code above and have
256*4882a593Smuzhiyun * a minimum wait time, which makes us quite late here,
257*4882a593Smuzhiyun * eating into the user's time to refresh the buffer, esp.
258*4882a593Smuzhiyun * if using small periods.
259*4882a593Smuzhiyun *
260*4882a593Smuzhiyun * If we're less than 9 samples behind, we're on target.
261*4882a593Smuzhiyun * Otherwise, shorten the next vperiod by the amount we've
262*4882a593Smuzhiyun * been delayed.
263*4882a593Smuzhiyun */
264*4882a593Smuzhiyun if (sync > -9)
265*4882a593Smuzhiyun voice->vperiod = voice->sync_period_size + 1;
266*4882a593Smuzhiyun else
267*4882a593Smuzhiyun voice->vperiod = voice->sync_period_size + sync + 10;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun if (voice->vperiod < voice->buffer_size) {
270*4882a593Smuzhiyun sis_update_sso(voice, voice->vperiod);
271*4882a593Smuzhiyun voice->vperiod = 0;
272*4882a593Smuzhiyun } else
273*4882a593Smuzhiyun sis_update_sso(voice, voice->period_size);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun sync = voice->sync_cso + voice->sync_period_size;
276*4882a593Smuzhiyun if (sync >= voice->sync_buffer_size)
277*4882a593Smuzhiyun sync -= voice->sync_buffer_size;
278*4882a593Smuzhiyun voice->sync_cso = sync;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun snd_pcm_period_elapsed(voice->substream);
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
sis_voice_irq(u32 status,struct voice * voice)284*4882a593Smuzhiyun static void sis_voice_irq(u32 status, struct voice *voice)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun int bit;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun while (status) {
289*4882a593Smuzhiyun bit = __ffs(status);
290*4882a593Smuzhiyun status >>= bit + 1;
291*4882a593Smuzhiyun voice += bit;
292*4882a593Smuzhiyun sis_update_voice(voice);
293*4882a593Smuzhiyun voice++;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
sis_interrupt(int irq,void * dev)297*4882a593Smuzhiyun static irqreturn_t sis_interrupt(int irq, void *dev)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun struct sis7019 *sis = dev;
300*4882a593Smuzhiyun unsigned long io = sis->ioport;
301*4882a593Smuzhiyun struct voice *voice;
302*4882a593Smuzhiyun u32 intr, status;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /* We only use the DMA interrupts, and we don't enable any other
305*4882a593Smuzhiyun * source of interrupts. But, it is possible to see an interrupt
306*4882a593Smuzhiyun * status that didn't actually interrupt us, so eliminate anything
307*4882a593Smuzhiyun * we're not expecting to avoid falsely claiming an IRQ, and an
308*4882a593Smuzhiyun * ensuing endless loop.
309*4882a593Smuzhiyun */
310*4882a593Smuzhiyun intr = inl(io + SIS_GISR);
311*4882a593Smuzhiyun intr &= SIS_GISR_AUDIO_PLAY_DMA_IRQ_STATUS |
312*4882a593Smuzhiyun SIS_GISR_AUDIO_RECORD_DMA_IRQ_STATUS;
313*4882a593Smuzhiyun if (!intr)
314*4882a593Smuzhiyun return IRQ_NONE;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun do {
317*4882a593Smuzhiyun status = inl(io + SIS_PISR_A);
318*4882a593Smuzhiyun if (status) {
319*4882a593Smuzhiyun sis_voice_irq(status, sis->voices);
320*4882a593Smuzhiyun outl(status, io + SIS_PISR_A);
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun status = inl(io + SIS_PISR_B);
324*4882a593Smuzhiyun if (status) {
325*4882a593Smuzhiyun sis_voice_irq(status, &sis->voices[32]);
326*4882a593Smuzhiyun outl(status, io + SIS_PISR_B);
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun status = inl(io + SIS_RISR);
330*4882a593Smuzhiyun if (status) {
331*4882a593Smuzhiyun voice = &sis->capture_voice;
332*4882a593Smuzhiyun if (!voice->timing)
333*4882a593Smuzhiyun snd_pcm_period_elapsed(voice->substream);
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun outl(status, io + SIS_RISR);
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun outl(intr, io + SIS_GISR);
339*4882a593Smuzhiyun intr = inl(io + SIS_GISR);
340*4882a593Smuzhiyun intr &= SIS_GISR_AUDIO_PLAY_DMA_IRQ_STATUS |
341*4882a593Smuzhiyun SIS_GISR_AUDIO_RECORD_DMA_IRQ_STATUS;
342*4882a593Smuzhiyun } while (intr);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun return IRQ_HANDLED;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
sis_rate_to_delta(unsigned int rate)347*4882a593Smuzhiyun static u32 sis_rate_to_delta(unsigned int rate)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun u32 delta;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun /* This was copied from the trident driver, but it seems its gotten
352*4882a593Smuzhiyun * around a bit... nevertheless, it works well.
353*4882a593Smuzhiyun *
354*4882a593Smuzhiyun * We special case 44100 and 8000 since rounding with the equation
355*4882a593Smuzhiyun * does not give us an accurate enough value. For 11025 and 22050
356*4882a593Smuzhiyun * the equation gives us the best answer. All other frequencies will
357*4882a593Smuzhiyun * also use the equation. JDW
358*4882a593Smuzhiyun */
359*4882a593Smuzhiyun if (rate == 44100)
360*4882a593Smuzhiyun delta = 0xeb3;
361*4882a593Smuzhiyun else if (rate == 8000)
362*4882a593Smuzhiyun delta = 0x2ab;
363*4882a593Smuzhiyun else if (rate == 48000)
364*4882a593Smuzhiyun delta = 0x1000;
365*4882a593Smuzhiyun else
366*4882a593Smuzhiyun delta = (((rate << 12) + 24000) / 48000) & 0x0000ffff;
367*4882a593Smuzhiyun return delta;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
__sis_map_silence(struct sis7019 * sis)370*4882a593Smuzhiyun static void __sis_map_silence(struct sis7019 *sis)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun /* Helper function: must hold sis->voice_lock on entry */
373*4882a593Smuzhiyun if (!sis->silence_users)
374*4882a593Smuzhiyun sis->silence_dma_addr = dma_map_single(&sis->pci->dev,
375*4882a593Smuzhiyun sis->suspend_state[0],
376*4882a593Smuzhiyun 4096, DMA_TO_DEVICE);
377*4882a593Smuzhiyun sis->silence_users++;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
__sis_unmap_silence(struct sis7019 * sis)380*4882a593Smuzhiyun static void __sis_unmap_silence(struct sis7019 *sis)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun /* Helper function: must hold sis->voice_lock on entry */
383*4882a593Smuzhiyun sis->silence_users--;
384*4882a593Smuzhiyun if (!sis->silence_users)
385*4882a593Smuzhiyun dma_unmap_single(&sis->pci->dev, sis->silence_dma_addr, 4096,
386*4882a593Smuzhiyun DMA_TO_DEVICE);
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
sis_free_voice(struct sis7019 * sis,struct voice * voice)389*4882a593Smuzhiyun static void sis_free_voice(struct sis7019 *sis, struct voice *voice)
390*4882a593Smuzhiyun {
391*4882a593Smuzhiyun unsigned long flags;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun spin_lock_irqsave(&sis->voice_lock, flags);
394*4882a593Smuzhiyun if (voice->timing) {
395*4882a593Smuzhiyun __sis_unmap_silence(sis);
396*4882a593Smuzhiyun voice->timing->flags &= ~(VOICE_IN_USE | VOICE_SSO_TIMING |
397*4882a593Smuzhiyun VOICE_SYNC_TIMING);
398*4882a593Smuzhiyun voice->timing = NULL;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun voice->flags &= ~(VOICE_IN_USE | VOICE_SSO_TIMING | VOICE_SYNC_TIMING);
401*4882a593Smuzhiyun spin_unlock_irqrestore(&sis->voice_lock, flags);
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
__sis_alloc_playback_voice(struct sis7019 * sis)404*4882a593Smuzhiyun static struct voice *__sis_alloc_playback_voice(struct sis7019 *sis)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun /* Must hold the voice_lock on entry */
407*4882a593Smuzhiyun struct voice *voice;
408*4882a593Smuzhiyun int i;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun for (i = 0; i < 64; i++) {
411*4882a593Smuzhiyun voice = &sis->voices[i];
412*4882a593Smuzhiyun if (voice->flags & VOICE_IN_USE)
413*4882a593Smuzhiyun continue;
414*4882a593Smuzhiyun voice->flags |= VOICE_IN_USE;
415*4882a593Smuzhiyun goto found_one;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun voice = NULL;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun found_one:
420*4882a593Smuzhiyun return voice;
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
sis_alloc_playback_voice(struct sis7019 * sis)423*4882a593Smuzhiyun static struct voice *sis_alloc_playback_voice(struct sis7019 *sis)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun struct voice *voice;
426*4882a593Smuzhiyun unsigned long flags;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun spin_lock_irqsave(&sis->voice_lock, flags);
429*4882a593Smuzhiyun voice = __sis_alloc_playback_voice(sis);
430*4882a593Smuzhiyun spin_unlock_irqrestore(&sis->voice_lock, flags);
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun return voice;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun
sis_alloc_timing_voice(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)435*4882a593Smuzhiyun static int sis_alloc_timing_voice(struct snd_pcm_substream *substream,
436*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params)
437*4882a593Smuzhiyun {
438*4882a593Smuzhiyun struct sis7019 *sis = snd_pcm_substream_chip(substream);
439*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
440*4882a593Smuzhiyun struct voice *voice = runtime->private_data;
441*4882a593Smuzhiyun unsigned int period_size, buffer_size;
442*4882a593Smuzhiyun unsigned long flags;
443*4882a593Smuzhiyun int needed;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun /* If there are one or two periods per buffer, we don't need a
446*4882a593Smuzhiyun * timing voice, as we can use the capture channel's interrupts
447*4882a593Smuzhiyun * to clock out the periods.
448*4882a593Smuzhiyun */
449*4882a593Smuzhiyun period_size = params_period_size(hw_params);
450*4882a593Smuzhiyun buffer_size = params_buffer_size(hw_params);
451*4882a593Smuzhiyun needed = (period_size != buffer_size &&
452*4882a593Smuzhiyun period_size != (buffer_size / 2));
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun if (needed && !voice->timing) {
455*4882a593Smuzhiyun spin_lock_irqsave(&sis->voice_lock, flags);
456*4882a593Smuzhiyun voice->timing = __sis_alloc_playback_voice(sis);
457*4882a593Smuzhiyun if (voice->timing)
458*4882a593Smuzhiyun __sis_map_silence(sis);
459*4882a593Smuzhiyun spin_unlock_irqrestore(&sis->voice_lock, flags);
460*4882a593Smuzhiyun if (!voice->timing)
461*4882a593Smuzhiyun return -ENOMEM;
462*4882a593Smuzhiyun voice->timing->substream = substream;
463*4882a593Smuzhiyun } else if (!needed && voice->timing) {
464*4882a593Smuzhiyun sis_free_voice(sis, voice);
465*4882a593Smuzhiyun voice->timing = NULL;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun return 0;
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun
sis_playback_open(struct snd_pcm_substream * substream)471*4882a593Smuzhiyun static int sis_playback_open(struct snd_pcm_substream *substream)
472*4882a593Smuzhiyun {
473*4882a593Smuzhiyun struct sis7019 *sis = snd_pcm_substream_chip(substream);
474*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
475*4882a593Smuzhiyun struct voice *voice;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun voice = sis_alloc_playback_voice(sis);
478*4882a593Smuzhiyun if (!voice)
479*4882a593Smuzhiyun return -EAGAIN;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun voice->substream = substream;
482*4882a593Smuzhiyun runtime->private_data = voice;
483*4882a593Smuzhiyun runtime->hw = sis_playback_hw_info;
484*4882a593Smuzhiyun snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
485*4882a593Smuzhiyun 9, 0xfff9);
486*4882a593Smuzhiyun snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
487*4882a593Smuzhiyun 9, 0xfff9);
488*4882a593Smuzhiyun snd_pcm_set_sync(substream);
489*4882a593Smuzhiyun return 0;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun
sis_substream_close(struct snd_pcm_substream * substream)492*4882a593Smuzhiyun static int sis_substream_close(struct snd_pcm_substream *substream)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun struct sis7019 *sis = snd_pcm_substream_chip(substream);
495*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
496*4882a593Smuzhiyun struct voice *voice = runtime->private_data;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun sis_free_voice(sis, voice);
499*4882a593Smuzhiyun return 0;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
sis_pcm_playback_prepare(struct snd_pcm_substream * substream)502*4882a593Smuzhiyun static int sis_pcm_playback_prepare(struct snd_pcm_substream *substream)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
505*4882a593Smuzhiyun struct voice *voice = runtime->private_data;
506*4882a593Smuzhiyun void __iomem *ctrl_base = voice->ctrl_base;
507*4882a593Smuzhiyun void __iomem *wave_base = voice->wave_base;
508*4882a593Smuzhiyun u32 format, dma_addr, control, sso_eso, delta, reg;
509*4882a593Smuzhiyun u16 leo;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun /* We rely on the PCM core to ensure that the parameters for this
512*4882a593Smuzhiyun * substream do not change on us while we're programming the HW.
513*4882a593Smuzhiyun */
514*4882a593Smuzhiyun format = 0;
515*4882a593Smuzhiyun if (snd_pcm_format_width(runtime->format) == 8)
516*4882a593Smuzhiyun format |= SIS_PLAY_DMA_FORMAT_8BIT;
517*4882a593Smuzhiyun if (!snd_pcm_format_signed(runtime->format))
518*4882a593Smuzhiyun format |= SIS_PLAY_DMA_FORMAT_UNSIGNED;
519*4882a593Smuzhiyun if (runtime->channels == 1)
520*4882a593Smuzhiyun format |= SIS_PLAY_DMA_FORMAT_MONO;
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun /* The baseline setup is for a single period per buffer, and
523*4882a593Smuzhiyun * we add bells and whistles as needed from there.
524*4882a593Smuzhiyun */
525*4882a593Smuzhiyun dma_addr = runtime->dma_addr;
526*4882a593Smuzhiyun leo = runtime->buffer_size - 1;
527*4882a593Smuzhiyun control = leo | SIS_PLAY_DMA_LOOP | SIS_PLAY_DMA_INTR_AT_LEO;
528*4882a593Smuzhiyun sso_eso = leo;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun if (runtime->period_size == (runtime->buffer_size / 2)) {
531*4882a593Smuzhiyun control |= SIS_PLAY_DMA_INTR_AT_MLP;
532*4882a593Smuzhiyun } else if (runtime->period_size != runtime->buffer_size) {
533*4882a593Smuzhiyun voice->flags |= VOICE_SSO_TIMING;
534*4882a593Smuzhiyun voice->sso = runtime->period_size - 1;
535*4882a593Smuzhiyun voice->period_size = runtime->period_size;
536*4882a593Smuzhiyun voice->buffer_size = runtime->buffer_size;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun control &= ~SIS_PLAY_DMA_INTR_AT_LEO;
539*4882a593Smuzhiyun control |= SIS_PLAY_DMA_INTR_AT_SSO;
540*4882a593Smuzhiyun sso_eso |= (runtime->period_size - 1) << 16;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun delta = sis_rate_to_delta(runtime->rate);
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun /* Ok, we're ready to go, set up the channel.
546*4882a593Smuzhiyun */
547*4882a593Smuzhiyun writel(format, ctrl_base + SIS_PLAY_DMA_FORMAT_CSO);
548*4882a593Smuzhiyun writel(dma_addr, ctrl_base + SIS_PLAY_DMA_BASE);
549*4882a593Smuzhiyun writel(control, ctrl_base + SIS_PLAY_DMA_CONTROL);
550*4882a593Smuzhiyun writel(sso_eso, ctrl_base + SIS_PLAY_DMA_SSO_ESO);
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun for (reg = 0; reg < SIS_WAVE_SIZE; reg += 4)
553*4882a593Smuzhiyun writel(0, wave_base + reg);
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun writel(SIS_WAVE_GENERAL_WAVE_VOLUME, wave_base + SIS_WAVE_GENERAL);
556*4882a593Smuzhiyun writel(delta << 16, wave_base + SIS_WAVE_GENERAL_ARTICULATION);
557*4882a593Smuzhiyun writel(SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE |
558*4882a593Smuzhiyun SIS_WAVE_CHANNEL_CONTROL_AMP_ENABLE |
559*4882a593Smuzhiyun SIS_WAVE_CHANNEL_CONTROL_INTERPOLATE_ENABLE,
560*4882a593Smuzhiyun wave_base + SIS_WAVE_CHANNEL_CONTROL);
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun /* Force PCI writes to post. */
563*4882a593Smuzhiyun readl(ctrl_base);
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun return 0;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
sis_pcm_trigger(struct snd_pcm_substream * substream,int cmd)568*4882a593Smuzhiyun static int sis_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
569*4882a593Smuzhiyun {
570*4882a593Smuzhiyun struct sis7019 *sis = snd_pcm_substream_chip(substream);
571*4882a593Smuzhiyun unsigned long io = sis->ioport;
572*4882a593Smuzhiyun struct snd_pcm_substream *s;
573*4882a593Smuzhiyun struct voice *voice;
574*4882a593Smuzhiyun void *chip;
575*4882a593Smuzhiyun int starting;
576*4882a593Smuzhiyun u32 record = 0;
577*4882a593Smuzhiyun u32 play[2] = { 0, 0 };
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun /* No locks needed, as the PCM core will hold the locks on the
580*4882a593Smuzhiyun * substreams, and the HW will only start/stop the indicated voices
581*4882a593Smuzhiyun * without changing the state of the others.
582*4882a593Smuzhiyun */
583*4882a593Smuzhiyun switch (cmd) {
584*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
585*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
586*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
587*4882a593Smuzhiyun starting = 1;
588*4882a593Smuzhiyun break;
589*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
590*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
591*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
592*4882a593Smuzhiyun starting = 0;
593*4882a593Smuzhiyun break;
594*4882a593Smuzhiyun default:
595*4882a593Smuzhiyun return -EINVAL;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun snd_pcm_group_for_each_entry(s, substream) {
599*4882a593Smuzhiyun /* Make sure it is for us... */
600*4882a593Smuzhiyun chip = snd_pcm_substream_chip(s);
601*4882a593Smuzhiyun if (chip != sis)
602*4882a593Smuzhiyun continue;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun voice = s->runtime->private_data;
605*4882a593Smuzhiyun if (voice->flags & VOICE_CAPTURE) {
606*4882a593Smuzhiyun record |= 1 << voice->num;
607*4882a593Smuzhiyun voice = voice->timing;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun /* voice could be NULL if this a recording stream, and it
611*4882a593Smuzhiyun * doesn't have an external timing channel.
612*4882a593Smuzhiyun */
613*4882a593Smuzhiyun if (voice)
614*4882a593Smuzhiyun play[voice->num / 32] |= 1 << (voice->num & 0x1f);
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun snd_pcm_trigger_done(s, substream);
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun if (starting) {
620*4882a593Smuzhiyun if (record)
621*4882a593Smuzhiyun outl(record, io + SIS_RECORD_START_REG);
622*4882a593Smuzhiyun if (play[0])
623*4882a593Smuzhiyun outl(play[0], io + SIS_PLAY_START_A_REG);
624*4882a593Smuzhiyun if (play[1])
625*4882a593Smuzhiyun outl(play[1], io + SIS_PLAY_START_B_REG);
626*4882a593Smuzhiyun } else {
627*4882a593Smuzhiyun if (record)
628*4882a593Smuzhiyun outl(record, io + SIS_RECORD_STOP_REG);
629*4882a593Smuzhiyun if (play[0])
630*4882a593Smuzhiyun outl(play[0], io + SIS_PLAY_STOP_A_REG);
631*4882a593Smuzhiyun if (play[1])
632*4882a593Smuzhiyun outl(play[1], io + SIS_PLAY_STOP_B_REG);
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun return 0;
635*4882a593Smuzhiyun }
636*4882a593Smuzhiyun
sis_pcm_pointer(struct snd_pcm_substream * substream)637*4882a593Smuzhiyun static snd_pcm_uframes_t sis_pcm_pointer(struct snd_pcm_substream *substream)
638*4882a593Smuzhiyun {
639*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
640*4882a593Smuzhiyun struct voice *voice = runtime->private_data;
641*4882a593Smuzhiyun u32 cso;
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun cso = readl(voice->ctrl_base + SIS_PLAY_DMA_FORMAT_CSO);
644*4882a593Smuzhiyun cso &= 0xffff;
645*4882a593Smuzhiyun return cso;
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun
sis_capture_open(struct snd_pcm_substream * substream)648*4882a593Smuzhiyun static int sis_capture_open(struct snd_pcm_substream *substream)
649*4882a593Smuzhiyun {
650*4882a593Smuzhiyun struct sis7019 *sis = snd_pcm_substream_chip(substream);
651*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
652*4882a593Smuzhiyun struct voice *voice = &sis->capture_voice;
653*4882a593Smuzhiyun unsigned long flags;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun /* FIXME: The driver only supports recording from one channel
656*4882a593Smuzhiyun * at the moment, but it could support more.
657*4882a593Smuzhiyun */
658*4882a593Smuzhiyun spin_lock_irqsave(&sis->voice_lock, flags);
659*4882a593Smuzhiyun if (voice->flags & VOICE_IN_USE)
660*4882a593Smuzhiyun voice = NULL;
661*4882a593Smuzhiyun else
662*4882a593Smuzhiyun voice->flags |= VOICE_IN_USE;
663*4882a593Smuzhiyun spin_unlock_irqrestore(&sis->voice_lock, flags);
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun if (!voice)
666*4882a593Smuzhiyun return -EAGAIN;
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun voice->substream = substream;
669*4882a593Smuzhiyun runtime->private_data = voice;
670*4882a593Smuzhiyun runtime->hw = sis_capture_hw_info;
671*4882a593Smuzhiyun runtime->hw.rates = sis->ac97[0]->rates[AC97_RATES_ADC];
672*4882a593Smuzhiyun snd_pcm_limit_hw_rates(runtime);
673*4882a593Smuzhiyun snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
674*4882a593Smuzhiyun 9, 0xfff9);
675*4882a593Smuzhiyun snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
676*4882a593Smuzhiyun 9, 0xfff9);
677*4882a593Smuzhiyun snd_pcm_set_sync(substream);
678*4882a593Smuzhiyun return 0;
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun
sis_capture_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)681*4882a593Smuzhiyun static int sis_capture_hw_params(struct snd_pcm_substream *substream,
682*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params)
683*4882a593Smuzhiyun {
684*4882a593Smuzhiyun struct sis7019 *sis = snd_pcm_substream_chip(substream);
685*4882a593Smuzhiyun int rc;
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun rc = snd_ac97_set_rate(sis->ac97[0], AC97_PCM_LR_ADC_RATE,
688*4882a593Smuzhiyun params_rate(hw_params));
689*4882a593Smuzhiyun if (rc)
690*4882a593Smuzhiyun goto out;
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun rc = sis_alloc_timing_voice(substream, hw_params);
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun out:
695*4882a593Smuzhiyun return rc;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
sis_prepare_timing_voice(struct voice * voice,struct snd_pcm_substream * substream)698*4882a593Smuzhiyun static void sis_prepare_timing_voice(struct voice *voice,
699*4882a593Smuzhiyun struct snd_pcm_substream *substream)
700*4882a593Smuzhiyun {
701*4882a593Smuzhiyun struct sis7019 *sis = snd_pcm_substream_chip(substream);
702*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
703*4882a593Smuzhiyun struct voice *timing = voice->timing;
704*4882a593Smuzhiyun void __iomem *play_base = timing->ctrl_base;
705*4882a593Smuzhiyun void __iomem *wave_base = timing->wave_base;
706*4882a593Smuzhiyun u16 buffer_size, period_size;
707*4882a593Smuzhiyun u32 format, control, sso_eso, delta;
708*4882a593Smuzhiyun u32 vperiod, sso, reg;
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun /* Set our initial buffer and period as large as we can given a
711*4882a593Smuzhiyun * single page of silence.
712*4882a593Smuzhiyun */
713*4882a593Smuzhiyun buffer_size = 4096 / runtime->channels;
714*4882a593Smuzhiyun buffer_size /= snd_pcm_format_size(runtime->format, 1);
715*4882a593Smuzhiyun period_size = buffer_size;
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun /* Initially, we want to interrupt just a bit behind the end of
718*4882a593Smuzhiyun * the period we're clocking out. 12 samples seems to give a good
719*4882a593Smuzhiyun * delay.
720*4882a593Smuzhiyun *
721*4882a593Smuzhiyun * We want to spread our interrupts throughout the virtual period,
722*4882a593Smuzhiyun * so that we don't end up with two interrupts back to back at the
723*4882a593Smuzhiyun * end -- this helps minimize the effects of any jitter. Adjust our
724*4882a593Smuzhiyun * clocking period size so that the last period is at least a fourth
725*4882a593Smuzhiyun * of a full period.
726*4882a593Smuzhiyun *
727*4882a593Smuzhiyun * This is all moot if we don't need to use virtual periods.
728*4882a593Smuzhiyun */
729*4882a593Smuzhiyun vperiod = runtime->period_size + 12;
730*4882a593Smuzhiyun if (vperiod > period_size) {
731*4882a593Smuzhiyun u16 tail = vperiod % period_size;
732*4882a593Smuzhiyun u16 quarter_period = period_size / 4;
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun if (tail && tail < quarter_period) {
735*4882a593Smuzhiyun u16 loops = vperiod / period_size;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun tail = quarter_period - tail;
738*4882a593Smuzhiyun tail += loops - 1;
739*4882a593Smuzhiyun tail /= loops;
740*4882a593Smuzhiyun period_size -= tail;
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun sso = period_size - 1;
744*4882a593Smuzhiyun } else {
745*4882a593Smuzhiyun /* The initial period will fit inside the buffer, so we
746*4882a593Smuzhiyun * don't need to use virtual periods -- disable them.
747*4882a593Smuzhiyun */
748*4882a593Smuzhiyun period_size = runtime->period_size;
749*4882a593Smuzhiyun sso = vperiod - 1;
750*4882a593Smuzhiyun vperiod = 0;
751*4882a593Smuzhiyun }
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun /* The interrupt handler implements the timing synchronization, so
754*4882a593Smuzhiyun * setup its state.
755*4882a593Smuzhiyun */
756*4882a593Smuzhiyun timing->flags |= VOICE_SYNC_TIMING;
757*4882a593Smuzhiyun timing->sync_base = voice->ctrl_base;
758*4882a593Smuzhiyun timing->sync_cso = runtime->period_size;
759*4882a593Smuzhiyun timing->sync_period_size = runtime->period_size;
760*4882a593Smuzhiyun timing->sync_buffer_size = runtime->buffer_size;
761*4882a593Smuzhiyun timing->period_size = period_size;
762*4882a593Smuzhiyun timing->buffer_size = buffer_size;
763*4882a593Smuzhiyun timing->sso = sso;
764*4882a593Smuzhiyun timing->vperiod = vperiod;
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun /* Using unsigned samples with the all-zero silence buffer
767*4882a593Smuzhiyun * forces the output to the lower rail, killing playback.
768*4882a593Smuzhiyun * So ignore unsigned vs signed -- it doesn't change the timing.
769*4882a593Smuzhiyun */
770*4882a593Smuzhiyun format = 0;
771*4882a593Smuzhiyun if (snd_pcm_format_width(runtime->format) == 8)
772*4882a593Smuzhiyun format = SIS_CAPTURE_DMA_FORMAT_8BIT;
773*4882a593Smuzhiyun if (runtime->channels == 1)
774*4882a593Smuzhiyun format |= SIS_CAPTURE_DMA_FORMAT_MONO;
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun control = timing->buffer_size - 1;
777*4882a593Smuzhiyun control |= SIS_PLAY_DMA_LOOP | SIS_PLAY_DMA_INTR_AT_SSO;
778*4882a593Smuzhiyun sso_eso = timing->buffer_size - 1;
779*4882a593Smuzhiyun sso_eso |= timing->sso << 16;
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun delta = sis_rate_to_delta(runtime->rate);
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun /* We've done the math, now configure the channel.
784*4882a593Smuzhiyun */
785*4882a593Smuzhiyun writel(format, play_base + SIS_PLAY_DMA_FORMAT_CSO);
786*4882a593Smuzhiyun writel(sis->silence_dma_addr, play_base + SIS_PLAY_DMA_BASE);
787*4882a593Smuzhiyun writel(control, play_base + SIS_PLAY_DMA_CONTROL);
788*4882a593Smuzhiyun writel(sso_eso, play_base + SIS_PLAY_DMA_SSO_ESO);
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun for (reg = 0; reg < SIS_WAVE_SIZE; reg += 4)
791*4882a593Smuzhiyun writel(0, wave_base + reg);
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun writel(SIS_WAVE_GENERAL_WAVE_VOLUME, wave_base + SIS_WAVE_GENERAL);
794*4882a593Smuzhiyun writel(delta << 16, wave_base + SIS_WAVE_GENERAL_ARTICULATION);
795*4882a593Smuzhiyun writel(SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE |
796*4882a593Smuzhiyun SIS_WAVE_CHANNEL_CONTROL_AMP_ENABLE |
797*4882a593Smuzhiyun SIS_WAVE_CHANNEL_CONTROL_INTERPOLATE_ENABLE,
798*4882a593Smuzhiyun wave_base + SIS_WAVE_CHANNEL_CONTROL);
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun
sis_pcm_capture_prepare(struct snd_pcm_substream * substream)801*4882a593Smuzhiyun static int sis_pcm_capture_prepare(struct snd_pcm_substream *substream)
802*4882a593Smuzhiyun {
803*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
804*4882a593Smuzhiyun struct voice *voice = runtime->private_data;
805*4882a593Smuzhiyun void __iomem *rec_base = voice->ctrl_base;
806*4882a593Smuzhiyun u32 format, dma_addr, control;
807*4882a593Smuzhiyun u16 leo;
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun /* We rely on the PCM core to ensure that the parameters for this
810*4882a593Smuzhiyun * substream do not change on us while we're programming the HW.
811*4882a593Smuzhiyun */
812*4882a593Smuzhiyun format = 0;
813*4882a593Smuzhiyun if (snd_pcm_format_width(runtime->format) == 8)
814*4882a593Smuzhiyun format = SIS_CAPTURE_DMA_FORMAT_8BIT;
815*4882a593Smuzhiyun if (!snd_pcm_format_signed(runtime->format))
816*4882a593Smuzhiyun format |= SIS_CAPTURE_DMA_FORMAT_UNSIGNED;
817*4882a593Smuzhiyun if (runtime->channels == 1)
818*4882a593Smuzhiyun format |= SIS_CAPTURE_DMA_FORMAT_MONO;
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun dma_addr = runtime->dma_addr;
821*4882a593Smuzhiyun leo = runtime->buffer_size - 1;
822*4882a593Smuzhiyun control = leo | SIS_CAPTURE_DMA_LOOP;
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun /* If we've got more than two periods per buffer, then we have
825*4882a593Smuzhiyun * use a timing voice to clock out the periods. Otherwise, we can
826*4882a593Smuzhiyun * use the capture channel's interrupts.
827*4882a593Smuzhiyun */
828*4882a593Smuzhiyun if (voice->timing) {
829*4882a593Smuzhiyun sis_prepare_timing_voice(voice, substream);
830*4882a593Smuzhiyun } else {
831*4882a593Smuzhiyun control |= SIS_CAPTURE_DMA_INTR_AT_LEO;
832*4882a593Smuzhiyun if (runtime->period_size != runtime->buffer_size)
833*4882a593Smuzhiyun control |= SIS_CAPTURE_DMA_INTR_AT_MLP;
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun writel(format, rec_base + SIS_CAPTURE_DMA_FORMAT_CSO);
837*4882a593Smuzhiyun writel(dma_addr, rec_base + SIS_CAPTURE_DMA_BASE);
838*4882a593Smuzhiyun writel(control, rec_base + SIS_CAPTURE_DMA_CONTROL);
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun /* Force the writes to post. */
841*4882a593Smuzhiyun readl(rec_base);
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun return 0;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun static const struct snd_pcm_ops sis_playback_ops = {
847*4882a593Smuzhiyun .open = sis_playback_open,
848*4882a593Smuzhiyun .close = sis_substream_close,
849*4882a593Smuzhiyun .prepare = sis_pcm_playback_prepare,
850*4882a593Smuzhiyun .trigger = sis_pcm_trigger,
851*4882a593Smuzhiyun .pointer = sis_pcm_pointer,
852*4882a593Smuzhiyun };
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun static const struct snd_pcm_ops sis_capture_ops = {
855*4882a593Smuzhiyun .open = sis_capture_open,
856*4882a593Smuzhiyun .close = sis_substream_close,
857*4882a593Smuzhiyun .hw_params = sis_capture_hw_params,
858*4882a593Smuzhiyun .prepare = sis_pcm_capture_prepare,
859*4882a593Smuzhiyun .trigger = sis_pcm_trigger,
860*4882a593Smuzhiyun .pointer = sis_pcm_pointer,
861*4882a593Smuzhiyun };
862*4882a593Smuzhiyun
sis_pcm_create(struct sis7019 * sis)863*4882a593Smuzhiyun static int sis_pcm_create(struct sis7019 *sis)
864*4882a593Smuzhiyun {
865*4882a593Smuzhiyun struct snd_pcm *pcm;
866*4882a593Smuzhiyun int rc;
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun /* We have 64 voices, and the driver currently records from
869*4882a593Smuzhiyun * only one channel, though that could change in the future.
870*4882a593Smuzhiyun */
871*4882a593Smuzhiyun rc = snd_pcm_new(sis->card, "SiS7019", 0, 64, 1, &pcm);
872*4882a593Smuzhiyun if (rc)
873*4882a593Smuzhiyun return rc;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun pcm->private_data = sis;
876*4882a593Smuzhiyun strcpy(pcm->name, "SiS7019");
877*4882a593Smuzhiyun sis->pcm = pcm;
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &sis_playback_ops);
880*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &sis_capture_ops);
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun /* Try to preallocate some memory, but it's not the end of the
883*4882a593Smuzhiyun * world if this fails.
884*4882a593Smuzhiyun */
885*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
886*4882a593Smuzhiyun &sis->pci->dev, 64*1024, 128*1024);
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun return 0;
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun
sis_ac97_rw(struct sis7019 * sis,int codec,u32 cmd)891*4882a593Smuzhiyun static unsigned short sis_ac97_rw(struct sis7019 *sis, int codec, u32 cmd)
892*4882a593Smuzhiyun {
893*4882a593Smuzhiyun unsigned long io = sis->ioport;
894*4882a593Smuzhiyun unsigned short val = 0xffff;
895*4882a593Smuzhiyun u16 status;
896*4882a593Smuzhiyun u16 rdy;
897*4882a593Smuzhiyun int count;
898*4882a593Smuzhiyun static const u16 codec_ready[3] = {
899*4882a593Smuzhiyun SIS_AC97_STATUS_CODEC_READY,
900*4882a593Smuzhiyun SIS_AC97_STATUS_CODEC2_READY,
901*4882a593Smuzhiyun SIS_AC97_STATUS_CODEC3_READY,
902*4882a593Smuzhiyun };
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun rdy = codec_ready[codec];
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun /* Get the AC97 semaphore -- software first, so we don't spin
908*4882a593Smuzhiyun * pounding out IO reads on the hardware semaphore...
909*4882a593Smuzhiyun */
910*4882a593Smuzhiyun mutex_lock(&sis->ac97_mutex);
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun count = 0xffff;
913*4882a593Smuzhiyun while ((inw(io + SIS_AC97_SEMA) & SIS_AC97_SEMA_BUSY) && --count)
914*4882a593Smuzhiyun udelay(1);
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun if (!count)
917*4882a593Smuzhiyun goto timeout;
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun /* ... and wait for any outstanding commands to complete ...
920*4882a593Smuzhiyun */
921*4882a593Smuzhiyun count = 0xffff;
922*4882a593Smuzhiyun do {
923*4882a593Smuzhiyun status = inw(io + SIS_AC97_STATUS);
924*4882a593Smuzhiyun if ((status & rdy) && !(status & SIS_AC97_STATUS_BUSY))
925*4882a593Smuzhiyun break;
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun udelay(1);
928*4882a593Smuzhiyun } while (--count);
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun if (!count)
931*4882a593Smuzhiyun goto timeout_sema;
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun /* ... before sending our command and waiting for it to finish ...
934*4882a593Smuzhiyun */
935*4882a593Smuzhiyun outl(cmd, io + SIS_AC97_CMD);
936*4882a593Smuzhiyun udelay(10);
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun count = 0xffff;
939*4882a593Smuzhiyun while ((inw(io + SIS_AC97_STATUS) & SIS_AC97_STATUS_BUSY) && --count)
940*4882a593Smuzhiyun udelay(1);
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun /* ... and reading the results (if any).
943*4882a593Smuzhiyun */
944*4882a593Smuzhiyun val = inl(io + SIS_AC97_CMD) >> 16;
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun timeout_sema:
947*4882a593Smuzhiyun outl(SIS_AC97_SEMA_RELEASE, io + SIS_AC97_SEMA);
948*4882a593Smuzhiyun timeout:
949*4882a593Smuzhiyun mutex_unlock(&sis->ac97_mutex);
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun if (!count) {
952*4882a593Smuzhiyun dev_err(&sis->pci->dev, "ac97 codec %d timeout cmd 0x%08x\n",
953*4882a593Smuzhiyun codec, cmd);
954*4882a593Smuzhiyun }
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun return val;
957*4882a593Smuzhiyun }
958*4882a593Smuzhiyun
sis_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)959*4882a593Smuzhiyun static void sis_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
960*4882a593Smuzhiyun unsigned short val)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun static const u32 cmd[3] = {
963*4882a593Smuzhiyun SIS_AC97_CMD_CODEC_WRITE,
964*4882a593Smuzhiyun SIS_AC97_CMD_CODEC2_WRITE,
965*4882a593Smuzhiyun SIS_AC97_CMD_CODEC3_WRITE,
966*4882a593Smuzhiyun };
967*4882a593Smuzhiyun sis_ac97_rw(ac97->private_data, ac97->num,
968*4882a593Smuzhiyun (val << 16) | (reg << 8) | cmd[ac97->num]);
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun
sis_ac97_read(struct snd_ac97 * ac97,unsigned short reg)971*4882a593Smuzhiyun static unsigned short sis_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun static const u32 cmd[3] = {
974*4882a593Smuzhiyun SIS_AC97_CMD_CODEC_READ,
975*4882a593Smuzhiyun SIS_AC97_CMD_CODEC2_READ,
976*4882a593Smuzhiyun SIS_AC97_CMD_CODEC3_READ,
977*4882a593Smuzhiyun };
978*4882a593Smuzhiyun return sis_ac97_rw(ac97->private_data, ac97->num,
979*4882a593Smuzhiyun (reg << 8) | cmd[ac97->num]);
980*4882a593Smuzhiyun }
981*4882a593Smuzhiyun
sis_mixer_create(struct sis7019 * sis)982*4882a593Smuzhiyun static int sis_mixer_create(struct sis7019 *sis)
983*4882a593Smuzhiyun {
984*4882a593Smuzhiyun struct snd_ac97_bus *bus;
985*4882a593Smuzhiyun struct snd_ac97_template ac97;
986*4882a593Smuzhiyun static const struct snd_ac97_bus_ops ops = {
987*4882a593Smuzhiyun .write = sis_ac97_write,
988*4882a593Smuzhiyun .read = sis_ac97_read,
989*4882a593Smuzhiyun };
990*4882a593Smuzhiyun int rc;
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun memset(&ac97, 0, sizeof(ac97));
993*4882a593Smuzhiyun ac97.private_data = sis;
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun rc = snd_ac97_bus(sis->card, 0, &ops, NULL, &bus);
996*4882a593Smuzhiyun if (!rc && sis->codecs_present & SIS_PRIMARY_CODEC_PRESENT)
997*4882a593Smuzhiyun rc = snd_ac97_mixer(bus, &ac97, &sis->ac97[0]);
998*4882a593Smuzhiyun ac97.num = 1;
999*4882a593Smuzhiyun if (!rc && (sis->codecs_present & SIS_SECONDARY_CODEC_PRESENT))
1000*4882a593Smuzhiyun rc = snd_ac97_mixer(bus, &ac97, &sis->ac97[1]);
1001*4882a593Smuzhiyun ac97.num = 2;
1002*4882a593Smuzhiyun if (!rc && (sis->codecs_present & SIS_TERTIARY_CODEC_PRESENT))
1003*4882a593Smuzhiyun rc = snd_ac97_mixer(bus, &ac97, &sis->ac97[2]);
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun /* If we return an error here, then snd_card_free() should
1006*4882a593Smuzhiyun * free up any ac97 codecs that got created, as well as the bus.
1007*4882a593Smuzhiyun */
1008*4882a593Smuzhiyun return rc;
1009*4882a593Smuzhiyun }
1010*4882a593Smuzhiyun
sis_free_suspend(struct sis7019 * sis)1011*4882a593Smuzhiyun static void sis_free_suspend(struct sis7019 *sis)
1012*4882a593Smuzhiyun {
1013*4882a593Smuzhiyun int i;
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun for (i = 0; i < SIS_SUSPEND_PAGES; i++)
1016*4882a593Smuzhiyun kfree(sis->suspend_state[i]);
1017*4882a593Smuzhiyun }
1018*4882a593Smuzhiyun
sis_chip_free(struct sis7019 * sis)1019*4882a593Smuzhiyun static int sis_chip_free(struct sis7019 *sis)
1020*4882a593Smuzhiyun {
1021*4882a593Smuzhiyun /* Reset the chip, and disable all interrputs.
1022*4882a593Smuzhiyun */
1023*4882a593Smuzhiyun outl(SIS_GCR_SOFTWARE_RESET, sis->ioport + SIS_GCR);
1024*4882a593Smuzhiyun udelay(25);
1025*4882a593Smuzhiyun outl(0, sis->ioport + SIS_GCR);
1026*4882a593Smuzhiyun outl(0, sis->ioport + SIS_GIER);
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun /* Now, free everything we allocated.
1029*4882a593Smuzhiyun */
1030*4882a593Smuzhiyun if (sis->irq >= 0)
1031*4882a593Smuzhiyun free_irq(sis->irq, sis);
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun iounmap(sis->ioaddr);
1034*4882a593Smuzhiyun pci_release_regions(sis->pci);
1035*4882a593Smuzhiyun pci_disable_device(sis->pci);
1036*4882a593Smuzhiyun sis_free_suspend(sis);
1037*4882a593Smuzhiyun return 0;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun
sis_dev_free(struct snd_device * dev)1040*4882a593Smuzhiyun static int sis_dev_free(struct snd_device *dev)
1041*4882a593Smuzhiyun {
1042*4882a593Smuzhiyun struct sis7019 *sis = dev->device_data;
1043*4882a593Smuzhiyun return sis_chip_free(sis);
1044*4882a593Smuzhiyun }
1045*4882a593Smuzhiyun
sis_chip_init(struct sis7019 * sis)1046*4882a593Smuzhiyun static int sis_chip_init(struct sis7019 *sis)
1047*4882a593Smuzhiyun {
1048*4882a593Smuzhiyun unsigned long io = sis->ioport;
1049*4882a593Smuzhiyun void __iomem *ioaddr = sis->ioaddr;
1050*4882a593Smuzhiyun unsigned long timeout;
1051*4882a593Smuzhiyun u16 status;
1052*4882a593Smuzhiyun int count;
1053*4882a593Smuzhiyun int i;
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun /* Reset the audio controller
1056*4882a593Smuzhiyun */
1057*4882a593Smuzhiyun outl(SIS_GCR_SOFTWARE_RESET, io + SIS_GCR);
1058*4882a593Smuzhiyun udelay(25);
1059*4882a593Smuzhiyun outl(0, io + SIS_GCR);
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun /* Get the AC-link semaphore, and reset the codecs
1062*4882a593Smuzhiyun */
1063*4882a593Smuzhiyun count = 0xffff;
1064*4882a593Smuzhiyun while ((inw(io + SIS_AC97_SEMA) & SIS_AC97_SEMA_BUSY) && --count)
1065*4882a593Smuzhiyun udelay(1);
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun if (!count)
1068*4882a593Smuzhiyun return -EIO;
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun outl(SIS_AC97_CMD_CODEC_COLD_RESET, io + SIS_AC97_CMD);
1071*4882a593Smuzhiyun udelay(250);
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun count = 0xffff;
1074*4882a593Smuzhiyun while ((inw(io + SIS_AC97_STATUS) & SIS_AC97_STATUS_BUSY) && --count)
1075*4882a593Smuzhiyun udelay(1);
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun /* Command complete, we can let go of the semaphore now.
1078*4882a593Smuzhiyun */
1079*4882a593Smuzhiyun outl(SIS_AC97_SEMA_RELEASE, io + SIS_AC97_SEMA);
1080*4882a593Smuzhiyun if (!count)
1081*4882a593Smuzhiyun return -EIO;
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun /* Now that we've finished the reset, find out what's attached.
1084*4882a593Smuzhiyun * There are some codec/board combinations that take an extremely
1085*4882a593Smuzhiyun * long time to come up. 350+ ms has been observed in the field,
1086*4882a593Smuzhiyun * so we'll give them up to 500ms.
1087*4882a593Smuzhiyun */
1088*4882a593Smuzhiyun sis->codecs_present = 0;
1089*4882a593Smuzhiyun timeout = msecs_to_jiffies(500) + jiffies;
1090*4882a593Smuzhiyun while (time_before_eq(jiffies, timeout)) {
1091*4882a593Smuzhiyun status = inl(io + SIS_AC97_STATUS);
1092*4882a593Smuzhiyun if (status & SIS_AC97_STATUS_CODEC_READY)
1093*4882a593Smuzhiyun sis->codecs_present |= SIS_PRIMARY_CODEC_PRESENT;
1094*4882a593Smuzhiyun if (status & SIS_AC97_STATUS_CODEC2_READY)
1095*4882a593Smuzhiyun sis->codecs_present |= SIS_SECONDARY_CODEC_PRESENT;
1096*4882a593Smuzhiyun if (status & SIS_AC97_STATUS_CODEC3_READY)
1097*4882a593Smuzhiyun sis->codecs_present |= SIS_TERTIARY_CODEC_PRESENT;
1098*4882a593Smuzhiyun
1099*4882a593Smuzhiyun if (sis->codecs_present == codecs)
1100*4882a593Smuzhiyun break;
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun msleep(1);
1103*4882a593Smuzhiyun }
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun /* All done, check for errors.
1106*4882a593Smuzhiyun */
1107*4882a593Smuzhiyun if (!sis->codecs_present) {
1108*4882a593Smuzhiyun dev_err(&sis->pci->dev, "could not find any codecs\n");
1109*4882a593Smuzhiyun return -EIO;
1110*4882a593Smuzhiyun }
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun if (sis->codecs_present != codecs) {
1113*4882a593Smuzhiyun dev_warn(&sis->pci->dev, "missing codecs, found %0x, expected %0x\n",
1114*4882a593Smuzhiyun sis->codecs_present, codecs);
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun /* Let the hardware know that the audio driver is alive,
1118*4882a593Smuzhiyun * and enable PCM slots on the AC-link for L/R playback (3 & 4) and
1119*4882a593Smuzhiyun * record channels. We're going to want to use Variable Rate Audio
1120*4882a593Smuzhiyun * for recording, to avoid needlessly resampling from 48kHZ.
1121*4882a593Smuzhiyun */
1122*4882a593Smuzhiyun outl(SIS_AC97_CONF_AUDIO_ALIVE, io + SIS_AC97_CONF);
1123*4882a593Smuzhiyun outl(SIS_AC97_CONF_AUDIO_ALIVE | SIS_AC97_CONF_PCM_LR_ENABLE |
1124*4882a593Smuzhiyun SIS_AC97_CONF_PCM_CAP_MIC_ENABLE |
1125*4882a593Smuzhiyun SIS_AC97_CONF_PCM_CAP_LR_ENABLE |
1126*4882a593Smuzhiyun SIS_AC97_CONF_CODEC_VRA_ENABLE, io + SIS_AC97_CONF);
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun /* All AC97 PCM slots should be sourced from sub-mixer 0.
1129*4882a593Smuzhiyun */
1130*4882a593Smuzhiyun outl(0, io + SIS_AC97_PSR);
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun /* There is only one valid DMA setup for a PCI environment.
1133*4882a593Smuzhiyun */
1134*4882a593Smuzhiyun outl(SIS_DMA_CSR_PCI_SETTINGS, io + SIS_DMA_CSR);
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun /* Reset the synchronization groups for all of the channels
1137*4882a593Smuzhiyun * to be asynchronous. If we start doing SPDIF or 5.1 sound, etc.
1138*4882a593Smuzhiyun * we'll need to change how we handle these. Until then, we just
1139*4882a593Smuzhiyun * assign sub-mixer 0 to all playback channels, and avoid any
1140*4882a593Smuzhiyun * attenuation on the audio.
1141*4882a593Smuzhiyun */
1142*4882a593Smuzhiyun outl(0, io + SIS_PLAY_SYNC_GROUP_A);
1143*4882a593Smuzhiyun outl(0, io + SIS_PLAY_SYNC_GROUP_B);
1144*4882a593Smuzhiyun outl(0, io + SIS_PLAY_SYNC_GROUP_C);
1145*4882a593Smuzhiyun outl(0, io + SIS_PLAY_SYNC_GROUP_D);
1146*4882a593Smuzhiyun outl(0, io + SIS_MIXER_SYNC_GROUP);
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun for (i = 0; i < 64; i++) {
1149*4882a593Smuzhiyun writel(i, SIS_MIXER_START_ADDR(ioaddr, i));
1150*4882a593Smuzhiyun writel(SIS_MIXER_RIGHT_NO_ATTEN | SIS_MIXER_LEFT_NO_ATTEN |
1151*4882a593Smuzhiyun SIS_MIXER_DEST_0, SIS_MIXER_ADDR(ioaddr, i));
1152*4882a593Smuzhiyun }
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun /* Don't attenuate any audio set for the wave amplifier.
1155*4882a593Smuzhiyun *
1156*4882a593Smuzhiyun * FIXME: Maximum attenuation is set for the music amp, which will
1157*4882a593Smuzhiyun * need to change if we start using the synth engine.
1158*4882a593Smuzhiyun */
1159*4882a593Smuzhiyun outl(0xffff0000, io + SIS_WEVCR);
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun /* Ensure that the wave engine is in normal operating mode.
1162*4882a593Smuzhiyun */
1163*4882a593Smuzhiyun outl(0, io + SIS_WECCR);
1164*4882a593Smuzhiyun
1165*4882a593Smuzhiyun /* Go ahead and enable the DMA interrupts. They won't go live
1166*4882a593Smuzhiyun * until we start a channel.
1167*4882a593Smuzhiyun */
1168*4882a593Smuzhiyun outl(SIS_GIER_AUDIO_PLAY_DMA_IRQ_ENABLE |
1169*4882a593Smuzhiyun SIS_GIER_AUDIO_RECORD_DMA_IRQ_ENABLE, io + SIS_GIER);
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun return 0;
1172*4882a593Smuzhiyun }
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
sis_suspend(struct device * dev)1175*4882a593Smuzhiyun static int sis_suspend(struct device *dev)
1176*4882a593Smuzhiyun {
1177*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
1178*4882a593Smuzhiyun struct sis7019 *sis = card->private_data;
1179*4882a593Smuzhiyun void __iomem *ioaddr = sis->ioaddr;
1180*4882a593Smuzhiyun int i;
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1183*4882a593Smuzhiyun if (sis->codecs_present & SIS_PRIMARY_CODEC_PRESENT)
1184*4882a593Smuzhiyun snd_ac97_suspend(sis->ac97[0]);
1185*4882a593Smuzhiyun if (sis->codecs_present & SIS_SECONDARY_CODEC_PRESENT)
1186*4882a593Smuzhiyun snd_ac97_suspend(sis->ac97[1]);
1187*4882a593Smuzhiyun if (sis->codecs_present & SIS_TERTIARY_CODEC_PRESENT)
1188*4882a593Smuzhiyun snd_ac97_suspend(sis->ac97[2]);
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun /* snd_pcm_suspend_all() stopped all channels, so we're quiescent.
1191*4882a593Smuzhiyun */
1192*4882a593Smuzhiyun if (sis->irq >= 0) {
1193*4882a593Smuzhiyun free_irq(sis->irq, sis);
1194*4882a593Smuzhiyun sis->irq = -1;
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun /* Save the internal state away
1198*4882a593Smuzhiyun */
1199*4882a593Smuzhiyun for (i = 0; i < 4; i++) {
1200*4882a593Smuzhiyun memcpy_fromio(sis->suspend_state[i], ioaddr, 4096);
1201*4882a593Smuzhiyun ioaddr += 4096;
1202*4882a593Smuzhiyun }
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun return 0;
1205*4882a593Smuzhiyun }
1206*4882a593Smuzhiyun
sis_resume(struct device * dev)1207*4882a593Smuzhiyun static int sis_resume(struct device *dev)
1208*4882a593Smuzhiyun {
1209*4882a593Smuzhiyun struct pci_dev *pci = to_pci_dev(dev);
1210*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
1211*4882a593Smuzhiyun struct sis7019 *sis = card->private_data;
1212*4882a593Smuzhiyun void __iomem *ioaddr = sis->ioaddr;
1213*4882a593Smuzhiyun int i;
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun if (sis_chip_init(sis)) {
1216*4882a593Smuzhiyun dev_err(&pci->dev, "unable to re-init controller\n");
1217*4882a593Smuzhiyun goto error;
1218*4882a593Smuzhiyun }
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun if (request_irq(pci->irq, sis_interrupt, IRQF_SHARED,
1221*4882a593Smuzhiyun KBUILD_MODNAME, sis)) {
1222*4882a593Smuzhiyun dev_err(&pci->dev, "unable to regain IRQ %d\n", pci->irq);
1223*4882a593Smuzhiyun goto error;
1224*4882a593Smuzhiyun }
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun /* Restore saved state, then clear out the page we use for the
1227*4882a593Smuzhiyun * silence buffer.
1228*4882a593Smuzhiyun */
1229*4882a593Smuzhiyun for (i = 0; i < 4; i++) {
1230*4882a593Smuzhiyun memcpy_toio(ioaddr, sis->suspend_state[i], 4096);
1231*4882a593Smuzhiyun ioaddr += 4096;
1232*4882a593Smuzhiyun }
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun memset(sis->suspend_state[0], 0, 4096);
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun sis->irq = pci->irq;
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun if (sis->codecs_present & SIS_PRIMARY_CODEC_PRESENT)
1239*4882a593Smuzhiyun snd_ac97_resume(sis->ac97[0]);
1240*4882a593Smuzhiyun if (sis->codecs_present & SIS_SECONDARY_CODEC_PRESENT)
1241*4882a593Smuzhiyun snd_ac97_resume(sis->ac97[1]);
1242*4882a593Smuzhiyun if (sis->codecs_present & SIS_TERTIARY_CODEC_PRESENT)
1243*4882a593Smuzhiyun snd_ac97_resume(sis->ac97[2]);
1244*4882a593Smuzhiyun
1245*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1246*4882a593Smuzhiyun return 0;
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun error:
1249*4882a593Smuzhiyun snd_card_disconnect(card);
1250*4882a593Smuzhiyun return -EIO;
1251*4882a593Smuzhiyun }
1252*4882a593Smuzhiyun
1253*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(sis_pm, sis_suspend, sis_resume);
1254*4882a593Smuzhiyun #define SIS_PM_OPS &sis_pm
1255*4882a593Smuzhiyun #else
1256*4882a593Smuzhiyun #define SIS_PM_OPS NULL
1257*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
1258*4882a593Smuzhiyun
sis_alloc_suspend(struct sis7019 * sis)1259*4882a593Smuzhiyun static int sis_alloc_suspend(struct sis7019 *sis)
1260*4882a593Smuzhiyun {
1261*4882a593Smuzhiyun int i;
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun /* We need 16K to store the internal wave engine state during a
1264*4882a593Smuzhiyun * suspend, but we don't need it to be contiguous, so play nice
1265*4882a593Smuzhiyun * with the memory system. We'll also use this area for a silence
1266*4882a593Smuzhiyun * buffer.
1267*4882a593Smuzhiyun */
1268*4882a593Smuzhiyun for (i = 0; i < SIS_SUSPEND_PAGES; i++) {
1269*4882a593Smuzhiyun sis->suspend_state[i] = kmalloc(4096, GFP_KERNEL);
1270*4882a593Smuzhiyun if (!sis->suspend_state[i])
1271*4882a593Smuzhiyun return -ENOMEM;
1272*4882a593Smuzhiyun }
1273*4882a593Smuzhiyun memset(sis->suspend_state[0], 0, 4096);
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun return 0;
1276*4882a593Smuzhiyun }
1277*4882a593Smuzhiyun
sis_chip_create(struct snd_card * card,struct pci_dev * pci)1278*4882a593Smuzhiyun static int sis_chip_create(struct snd_card *card,
1279*4882a593Smuzhiyun struct pci_dev *pci)
1280*4882a593Smuzhiyun {
1281*4882a593Smuzhiyun struct sis7019 *sis = card->private_data;
1282*4882a593Smuzhiyun struct voice *voice;
1283*4882a593Smuzhiyun static const struct snd_device_ops ops = {
1284*4882a593Smuzhiyun .dev_free = sis_dev_free,
1285*4882a593Smuzhiyun };
1286*4882a593Smuzhiyun int rc;
1287*4882a593Smuzhiyun int i;
1288*4882a593Smuzhiyun
1289*4882a593Smuzhiyun rc = pci_enable_device(pci);
1290*4882a593Smuzhiyun if (rc)
1291*4882a593Smuzhiyun goto error_out;
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun rc = dma_set_mask(&pci->dev, DMA_BIT_MASK(30));
1294*4882a593Smuzhiyun if (rc < 0) {
1295*4882a593Smuzhiyun dev_err(&pci->dev, "architecture does not support 30-bit PCI busmaster DMA");
1296*4882a593Smuzhiyun goto error_out_enabled;
1297*4882a593Smuzhiyun }
1298*4882a593Smuzhiyun
1299*4882a593Smuzhiyun memset(sis, 0, sizeof(*sis));
1300*4882a593Smuzhiyun mutex_init(&sis->ac97_mutex);
1301*4882a593Smuzhiyun spin_lock_init(&sis->voice_lock);
1302*4882a593Smuzhiyun sis->card = card;
1303*4882a593Smuzhiyun sis->pci = pci;
1304*4882a593Smuzhiyun sis->irq = -1;
1305*4882a593Smuzhiyun sis->ioport = pci_resource_start(pci, 0);
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun rc = pci_request_regions(pci, "SiS7019");
1308*4882a593Smuzhiyun if (rc) {
1309*4882a593Smuzhiyun dev_err(&pci->dev, "unable request regions\n");
1310*4882a593Smuzhiyun goto error_out_enabled;
1311*4882a593Smuzhiyun }
1312*4882a593Smuzhiyun
1313*4882a593Smuzhiyun rc = -EIO;
1314*4882a593Smuzhiyun sis->ioaddr = ioremap(pci_resource_start(pci, 1), 0x4000);
1315*4882a593Smuzhiyun if (!sis->ioaddr) {
1316*4882a593Smuzhiyun dev_err(&pci->dev, "unable to remap MMIO, aborting\n");
1317*4882a593Smuzhiyun goto error_out_cleanup;
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun rc = sis_alloc_suspend(sis);
1321*4882a593Smuzhiyun if (rc < 0) {
1322*4882a593Smuzhiyun dev_err(&pci->dev, "unable to allocate state storage\n");
1323*4882a593Smuzhiyun goto error_out_cleanup;
1324*4882a593Smuzhiyun }
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun rc = sis_chip_init(sis);
1327*4882a593Smuzhiyun if (rc)
1328*4882a593Smuzhiyun goto error_out_cleanup;
1329*4882a593Smuzhiyun
1330*4882a593Smuzhiyun rc = request_irq(pci->irq, sis_interrupt, IRQF_SHARED, KBUILD_MODNAME,
1331*4882a593Smuzhiyun sis);
1332*4882a593Smuzhiyun if (rc) {
1333*4882a593Smuzhiyun dev_err(&pci->dev, "unable to allocate irq %d\n", sis->irq);
1334*4882a593Smuzhiyun goto error_out_cleanup;
1335*4882a593Smuzhiyun }
1336*4882a593Smuzhiyun
1337*4882a593Smuzhiyun sis->irq = pci->irq;
1338*4882a593Smuzhiyun card->sync_irq = sis->irq;
1339*4882a593Smuzhiyun pci_set_master(pci);
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun for (i = 0; i < 64; i++) {
1342*4882a593Smuzhiyun voice = &sis->voices[i];
1343*4882a593Smuzhiyun voice->num = i;
1344*4882a593Smuzhiyun voice->ctrl_base = SIS_PLAY_DMA_ADDR(sis->ioaddr, i);
1345*4882a593Smuzhiyun voice->wave_base = SIS_WAVE_ADDR(sis->ioaddr, i);
1346*4882a593Smuzhiyun }
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun voice = &sis->capture_voice;
1349*4882a593Smuzhiyun voice->flags = VOICE_CAPTURE;
1350*4882a593Smuzhiyun voice->num = SIS_CAPTURE_CHAN_AC97_PCM_IN;
1351*4882a593Smuzhiyun voice->ctrl_base = SIS_CAPTURE_DMA_ADDR(sis->ioaddr, voice->num);
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun rc = snd_device_new(card, SNDRV_DEV_LOWLEVEL, sis, &ops);
1354*4882a593Smuzhiyun if (rc)
1355*4882a593Smuzhiyun goto error_out_cleanup;
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun return 0;
1358*4882a593Smuzhiyun
1359*4882a593Smuzhiyun error_out_cleanup:
1360*4882a593Smuzhiyun sis_chip_free(sis);
1361*4882a593Smuzhiyun
1362*4882a593Smuzhiyun error_out_enabled:
1363*4882a593Smuzhiyun pci_disable_device(pci);
1364*4882a593Smuzhiyun
1365*4882a593Smuzhiyun error_out:
1366*4882a593Smuzhiyun return rc;
1367*4882a593Smuzhiyun }
1368*4882a593Smuzhiyun
snd_sis7019_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1369*4882a593Smuzhiyun static int snd_sis7019_probe(struct pci_dev *pci,
1370*4882a593Smuzhiyun const struct pci_device_id *pci_id)
1371*4882a593Smuzhiyun {
1372*4882a593Smuzhiyun struct snd_card *card;
1373*4882a593Smuzhiyun struct sis7019 *sis;
1374*4882a593Smuzhiyun int rc;
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun rc = -ENOENT;
1377*4882a593Smuzhiyun if (!enable)
1378*4882a593Smuzhiyun goto error_out;
1379*4882a593Smuzhiyun
1380*4882a593Smuzhiyun /* The user can specify which codecs should be present so that we
1381*4882a593Smuzhiyun * can wait for them to show up if they are slow to recover from
1382*4882a593Smuzhiyun * the AC97 cold reset. We default to a single codec, the primary.
1383*4882a593Smuzhiyun *
1384*4882a593Smuzhiyun * We assume that SIS_PRIMARY_*_PRESENT matches bits 0-2.
1385*4882a593Smuzhiyun */
1386*4882a593Smuzhiyun codecs &= SIS_PRIMARY_CODEC_PRESENT | SIS_SECONDARY_CODEC_PRESENT |
1387*4882a593Smuzhiyun SIS_TERTIARY_CODEC_PRESENT;
1388*4882a593Smuzhiyun if (!codecs)
1389*4882a593Smuzhiyun codecs = SIS_PRIMARY_CODEC_PRESENT;
1390*4882a593Smuzhiyun
1391*4882a593Smuzhiyun rc = snd_card_new(&pci->dev, index, id, THIS_MODULE,
1392*4882a593Smuzhiyun sizeof(*sis), &card);
1393*4882a593Smuzhiyun if (rc < 0)
1394*4882a593Smuzhiyun goto error_out;
1395*4882a593Smuzhiyun
1396*4882a593Smuzhiyun strcpy(card->driver, "SiS7019");
1397*4882a593Smuzhiyun strcpy(card->shortname, "SiS7019");
1398*4882a593Smuzhiyun rc = sis_chip_create(card, pci);
1399*4882a593Smuzhiyun if (rc)
1400*4882a593Smuzhiyun goto card_error_out;
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun sis = card->private_data;
1403*4882a593Smuzhiyun
1404*4882a593Smuzhiyun rc = sis_mixer_create(sis);
1405*4882a593Smuzhiyun if (rc)
1406*4882a593Smuzhiyun goto card_error_out;
1407*4882a593Smuzhiyun
1408*4882a593Smuzhiyun rc = sis_pcm_create(sis);
1409*4882a593Smuzhiyun if (rc)
1410*4882a593Smuzhiyun goto card_error_out;
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun snprintf(card->longname, sizeof(card->longname),
1413*4882a593Smuzhiyun "%s Audio Accelerator with %s at 0x%lx, irq %d",
1414*4882a593Smuzhiyun card->shortname, snd_ac97_get_short_name(sis->ac97[0]),
1415*4882a593Smuzhiyun sis->ioport, sis->irq);
1416*4882a593Smuzhiyun
1417*4882a593Smuzhiyun rc = snd_card_register(card);
1418*4882a593Smuzhiyun if (rc)
1419*4882a593Smuzhiyun goto card_error_out;
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun pci_set_drvdata(pci, card);
1422*4882a593Smuzhiyun return 0;
1423*4882a593Smuzhiyun
1424*4882a593Smuzhiyun card_error_out:
1425*4882a593Smuzhiyun snd_card_free(card);
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun error_out:
1428*4882a593Smuzhiyun return rc;
1429*4882a593Smuzhiyun }
1430*4882a593Smuzhiyun
snd_sis7019_remove(struct pci_dev * pci)1431*4882a593Smuzhiyun static void snd_sis7019_remove(struct pci_dev *pci)
1432*4882a593Smuzhiyun {
1433*4882a593Smuzhiyun snd_card_free(pci_get_drvdata(pci));
1434*4882a593Smuzhiyun }
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun static struct pci_driver sis7019_driver = {
1437*4882a593Smuzhiyun .name = KBUILD_MODNAME,
1438*4882a593Smuzhiyun .id_table = snd_sis7019_ids,
1439*4882a593Smuzhiyun .probe = snd_sis7019_probe,
1440*4882a593Smuzhiyun .remove = snd_sis7019_remove,
1441*4882a593Smuzhiyun .driver = {
1442*4882a593Smuzhiyun .pm = SIS_PM_OPS,
1443*4882a593Smuzhiyun },
1444*4882a593Smuzhiyun };
1445*4882a593Smuzhiyun
1446*4882a593Smuzhiyun module_pci_driver(sis7019_driver);
1447