1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for Digigram pcxhr compatible soundcards
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * hwdep device manager
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2004 by Digigram <alsa@digigram.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/vmalloc.h>
12*4882a593Smuzhiyun #include <linux/firmware.h>
13*4882a593Smuzhiyun #include <linux/pci.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <sound/core.h>
17*4882a593Smuzhiyun #include <sound/hwdep.h>
18*4882a593Smuzhiyun #include "pcxhr.h"
19*4882a593Smuzhiyun #include "pcxhr_mixer.h"
20*4882a593Smuzhiyun #include "pcxhr_hwdep.h"
21*4882a593Smuzhiyun #include "pcxhr_core.h"
22*4882a593Smuzhiyun #include "pcxhr_mix22.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static int pcxhr_sub_init(struct pcxhr_mgr *mgr);
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * get basic information and init pcxhr card
28*4882a593Smuzhiyun */
pcxhr_init_board(struct pcxhr_mgr * mgr)29*4882a593Smuzhiyun static int pcxhr_init_board(struct pcxhr_mgr *mgr)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun int err;
32*4882a593Smuzhiyun struct pcxhr_rmh rmh;
33*4882a593Smuzhiyun int card_streams;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* calc the number of all streams used */
36*4882a593Smuzhiyun if (mgr->mono_capture)
37*4882a593Smuzhiyun card_streams = mgr->capture_chips * 2;
38*4882a593Smuzhiyun else
39*4882a593Smuzhiyun card_streams = mgr->capture_chips;
40*4882a593Smuzhiyun card_streams += mgr->playback_chips * PCXHR_PLAYBACK_STREAMS;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* enable interrupts */
43*4882a593Smuzhiyun pcxhr_enable_dsp(mgr);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun pcxhr_init_rmh(&rmh, CMD_SUPPORTED);
46*4882a593Smuzhiyun err = pcxhr_send_msg(mgr, &rmh);
47*4882a593Smuzhiyun if (err)
48*4882a593Smuzhiyun return err;
49*4882a593Smuzhiyun /* test 4, 8 or 12 phys out */
50*4882a593Smuzhiyun if ((rmh.stat[0] & MASK_FIRST_FIELD) < mgr->playback_chips * 2)
51*4882a593Smuzhiyun return -EINVAL;
52*4882a593Smuzhiyun /* test 4, 8 or 2 phys in */
53*4882a593Smuzhiyun if (((rmh.stat[0] >> (2 * FIELD_SIZE)) & MASK_FIRST_FIELD) <
54*4882a593Smuzhiyun mgr->capture_chips * 2)
55*4882a593Smuzhiyun return -EINVAL;
56*4882a593Smuzhiyun /* test max nb substream per board */
57*4882a593Smuzhiyun if ((rmh.stat[1] & 0x5F) < card_streams)
58*4882a593Smuzhiyun return -EINVAL;
59*4882a593Smuzhiyun /* test max nb substream per pipe */
60*4882a593Smuzhiyun if (((rmh.stat[1] >> 7) & 0x5F) < PCXHR_PLAYBACK_STREAMS)
61*4882a593Smuzhiyun return -EINVAL;
62*4882a593Smuzhiyun dev_dbg(&mgr->pci->dev,
63*4882a593Smuzhiyun "supported formats : playback=%x capture=%x\n",
64*4882a593Smuzhiyun rmh.stat[2], rmh.stat[3]);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun pcxhr_init_rmh(&rmh, CMD_VERSION);
67*4882a593Smuzhiyun /* firmware num for DSP */
68*4882a593Smuzhiyun rmh.cmd[0] |= mgr->firmware_num;
69*4882a593Smuzhiyun /* transfer granularity in samples (should be multiple of 48) */
70*4882a593Smuzhiyun rmh.cmd[1] = (1<<23) + mgr->granularity;
71*4882a593Smuzhiyun rmh.cmd_len = 2;
72*4882a593Smuzhiyun err = pcxhr_send_msg(mgr, &rmh);
73*4882a593Smuzhiyun if (err)
74*4882a593Smuzhiyun return err;
75*4882a593Smuzhiyun dev_dbg(&mgr->pci->dev,
76*4882a593Smuzhiyun "PCXHR DSP version is %d.%d.%d\n", (rmh.stat[0]>>16)&0xff,
77*4882a593Smuzhiyun (rmh.stat[0]>>8)&0xff, rmh.stat[0]&0xff);
78*4882a593Smuzhiyun mgr->dsp_version = rmh.stat[0];
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (mgr->is_hr_stereo)
81*4882a593Smuzhiyun err = hr222_sub_init(mgr);
82*4882a593Smuzhiyun else
83*4882a593Smuzhiyun err = pcxhr_sub_init(mgr);
84*4882a593Smuzhiyun return err;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
pcxhr_sub_init(struct pcxhr_mgr * mgr)87*4882a593Smuzhiyun static int pcxhr_sub_init(struct pcxhr_mgr *mgr)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun int err;
90*4882a593Smuzhiyun struct pcxhr_rmh rmh;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* get options */
93*4882a593Smuzhiyun pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
94*4882a593Smuzhiyun rmh.cmd[0] |= IO_NUM_REG_STATUS;
95*4882a593Smuzhiyun rmh.cmd[1] = REG_STATUS_OPTIONS;
96*4882a593Smuzhiyun rmh.cmd_len = 2;
97*4882a593Smuzhiyun err = pcxhr_send_msg(mgr, &rmh);
98*4882a593Smuzhiyun if (err)
99*4882a593Smuzhiyun return err;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if ((rmh.stat[1] & REG_STATUS_OPT_DAUGHTER_MASK) ==
102*4882a593Smuzhiyun REG_STATUS_OPT_ANALOG_BOARD)
103*4882a593Smuzhiyun mgr->board_has_analog = 1; /* analog addon board found */
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* unmute inputs */
106*4882a593Smuzhiyun err = pcxhr_write_io_num_reg_cont(mgr, REG_CONT_UNMUTE_INPUTS,
107*4882a593Smuzhiyun REG_CONT_UNMUTE_INPUTS, NULL);
108*4882a593Smuzhiyun if (err)
109*4882a593Smuzhiyun return err;
110*4882a593Smuzhiyun /* unmute outputs (a write to IO_NUM_REG_MUTE_OUT mutes!) */
111*4882a593Smuzhiyun pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
112*4882a593Smuzhiyun rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
113*4882a593Smuzhiyun if (DSP_EXT_CMD_SET(mgr)) {
114*4882a593Smuzhiyun rmh.cmd[1] = 1; /* unmute digital plugs */
115*4882a593Smuzhiyun rmh.cmd_len = 2;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun err = pcxhr_send_msg(mgr, &rmh);
118*4882a593Smuzhiyun return err;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
pcxhr_reset_board(struct pcxhr_mgr * mgr)121*4882a593Smuzhiyun void pcxhr_reset_board(struct pcxhr_mgr *mgr)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct pcxhr_rmh rmh;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
126*4882a593Smuzhiyun /* mute outputs */
127*4882a593Smuzhiyun if (!mgr->is_hr_stereo) {
128*4882a593Smuzhiyun /* a read to IO_NUM_REG_MUTE_OUT register unmutes! */
129*4882a593Smuzhiyun pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
130*4882a593Smuzhiyun rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
131*4882a593Smuzhiyun pcxhr_send_msg(mgr, &rmh);
132*4882a593Smuzhiyun /* mute inputs */
133*4882a593Smuzhiyun pcxhr_write_io_num_reg_cont(mgr, REG_CONT_UNMUTE_INPUTS,
134*4882a593Smuzhiyun 0, NULL);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun /* stereo cards mute with reset of dsp */
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun /* reset pcxhr dsp */
139*4882a593Smuzhiyun if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_EPRM_INDEX))
140*4882a593Smuzhiyun pcxhr_reset_dsp(mgr);
141*4882a593Smuzhiyun /* reset second xilinx */
142*4882a593Smuzhiyun if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_XLX_COM_INDEX)) {
143*4882a593Smuzhiyun pcxhr_reset_xilinx_com(mgr);
144*4882a593Smuzhiyun mgr->dsp_loaded = 1;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun return;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /*
151*4882a593Smuzhiyun * allocate a playback/capture pipe (pcmp0/pcmc0)
152*4882a593Smuzhiyun */
pcxhr_dsp_allocate_pipe(struct pcxhr_mgr * mgr,struct pcxhr_pipe * pipe,int is_capture,int pin)153*4882a593Smuzhiyun static int pcxhr_dsp_allocate_pipe(struct pcxhr_mgr *mgr,
154*4882a593Smuzhiyun struct pcxhr_pipe *pipe,
155*4882a593Smuzhiyun int is_capture, int pin)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun int stream_count, audio_count;
158*4882a593Smuzhiyun int err;
159*4882a593Smuzhiyun struct pcxhr_rmh rmh;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun if (is_capture) {
162*4882a593Smuzhiyun stream_count = 1;
163*4882a593Smuzhiyun if (mgr->mono_capture)
164*4882a593Smuzhiyun audio_count = 1;
165*4882a593Smuzhiyun else
166*4882a593Smuzhiyun audio_count = 2;
167*4882a593Smuzhiyun } else {
168*4882a593Smuzhiyun stream_count = PCXHR_PLAYBACK_STREAMS;
169*4882a593Smuzhiyun audio_count = 2; /* always stereo */
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun dev_dbg(&mgr->pci->dev, "snd_add_ref_pipe pin(%d) pcm%c0\n",
172*4882a593Smuzhiyun pin, is_capture ? 'c' : 'p');
173*4882a593Smuzhiyun pipe->is_capture = is_capture;
174*4882a593Smuzhiyun pipe->first_audio = pin;
175*4882a593Smuzhiyun /* define pipe (P_PCM_ONLY_MASK (0x020000) is not necessary) */
176*4882a593Smuzhiyun pcxhr_init_rmh(&rmh, CMD_RES_PIPE);
177*4882a593Smuzhiyun pcxhr_set_pipe_cmd_params(&rmh, is_capture, pin,
178*4882a593Smuzhiyun audio_count, stream_count);
179*4882a593Smuzhiyun rmh.cmd[1] |= 0x020000; /* add P_PCM_ONLY_MASK */
180*4882a593Smuzhiyun if (DSP_EXT_CMD_SET(mgr)) {
181*4882a593Smuzhiyun /* add channel mask to command */
182*4882a593Smuzhiyun rmh.cmd[rmh.cmd_len++] = (audio_count == 1) ? 0x01 : 0x03;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun err = pcxhr_send_msg(mgr, &rmh);
185*4882a593Smuzhiyun if (err < 0) {
186*4882a593Smuzhiyun dev_err(&mgr->pci->dev, "error pipe allocation "
187*4882a593Smuzhiyun "(CMD_RES_PIPE) err=%x!\n", err);
188*4882a593Smuzhiyun return err;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun pipe->status = PCXHR_PIPE_DEFINED;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun return 0;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /*
196*4882a593Smuzhiyun * free playback/capture pipe (pcmp0/pcmc0)
197*4882a593Smuzhiyun */
198*4882a593Smuzhiyun #if 0
199*4882a593Smuzhiyun static int pcxhr_dsp_free_pipe( struct pcxhr_mgr *mgr, struct pcxhr_pipe *pipe)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun struct pcxhr_rmh rmh;
202*4882a593Smuzhiyun int capture_mask = 0;
203*4882a593Smuzhiyun int playback_mask = 0;
204*4882a593Smuzhiyun int err = 0;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun if (pipe->is_capture)
207*4882a593Smuzhiyun capture_mask = (1 << pipe->first_audio);
208*4882a593Smuzhiyun else
209*4882a593Smuzhiyun playback_mask = (1 << pipe->first_audio);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /* stop one pipe */
212*4882a593Smuzhiyun err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
213*4882a593Smuzhiyun if (err < 0)
214*4882a593Smuzhiyun dev_err(&mgr->pci->dev, "error stopping pipe!\n");
215*4882a593Smuzhiyun /* release the pipe */
216*4882a593Smuzhiyun pcxhr_init_rmh(&rmh, CMD_FREE_PIPE);
217*4882a593Smuzhiyun pcxhr_set_pipe_cmd_params(&rmh, pipe->is_capture, pipe->first_audio,
218*4882a593Smuzhiyun 0, 0);
219*4882a593Smuzhiyun err = pcxhr_send_msg(mgr, &rmh);
220*4882a593Smuzhiyun if (err < 0)
221*4882a593Smuzhiyun dev_err(&mgr->pci->dev, "error pipe release "
222*4882a593Smuzhiyun "(CMD_FREE_PIPE) err(%x)\n", err);
223*4882a593Smuzhiyun pipe->status = PCXHR_PIPE_UNDEFINED;
224*4882a593Smuzhiyun return err;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun #endif
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun
pcxhr_config_pipes(struct pcxhr_mgr * mgr)229*4882a593Smuzhiyun static int pcxhr_config_pipes(struct pcxhr_mgr *mgr)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun int err, i, j;
232*4882a593Smuzhiyun struct snd_pcxhr *chip;
233*4882a593Smuzhiyun struct pcxhr_pipe *pipe;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun /* allocate the pipes on the dsp */
236*4882a593Smuzhiyun for (i = 0; i < mgr->num_cards; i++) {
237*4882a593Smuzhiyun chip = mgr->chip[i];
238*4882a593Smuzhiyun if (chip->nb_streams_play) {
239*4882a593Smuzhiyun pipe = &chip->playback_pipe;
240*4882a593Smuzhiyun err = pcxhr_dsp_allocate_pipe( mgr, pipe, 0, i*2);
241*4882a593Smuzhiyun if (err)
242*4882a593Smuzhiyun return err;
243*4882a593Smuzhiyun for(j = 0; j < chip->nb_streams_play; j++)
244*4882a593Smuzhiyun chip->playback_stream[j].pipe = pipe;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun for (j = 0; j < chip->nb_streams_capt; j++) {
247*4882a593Smuzhiyun pipe = &chip->capture_pipe[j];
248*4882a593Smuzhiyun err = pcxhr_dsp_allocate_pipe(mgr, pipe, 1, i*2 + j);
249*4882a593Smuzhiyun if (err)
250*4882a593Smuzhiyun return err;
251*4882a593Smuzhiyun chip->capture_stream[j].pipe = pipe;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun return 0;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
pcxhr_start_pipes(struct pcxhr_mgr * mgr)257*4882a593Smuzhiyun static int pcxhr_start_pipes(struct pcxhr_mgr *mgr)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun int i, j;
260*4882a593Smuzhiyun struct snd_pcxhr *chip;
261*4882a593Smuzhiyun int playback_mask = 0;
262*4882a593Smuzhiyun int capture_mask = 0;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* start all the pipes on the dsp */
265*4882a593Smuzhiyun for (i = 0; i < mgr->num_cards; i++) {
266*4882a593Smuzhiyun chip = mgr->chip[i];
267*4882a593Smuzhiyun if (chip->nb_streams_play)
268*4882a593Smuzhiyun playback_mask |= 1 << chip->playback_pipe.first_audio;
269*4882a593Smuzhiyun for (j = 0; j < chip->nb_streams_capt; j++)
270*4882a593Smuzhiyun capture_mask |= 1 << chip->capture_pipe[j].first_audio;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun return pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun
pcxhr_dsp_load(struct pcxhr_mgr * mgr,int index,const struct firmware * dsp)276*4882a593Smuzhiyun static int pcxhr_dsp_load(struct pcxhr_mgr *mgr, int index,
277*4882a593Smuzhiyun const struct firmware *dsp)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun int err, card_index;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun dev_dbg(&mgr->pci->dev,
282*4882a593Smuzhiyun "loading dsp [%d] size = %zd\n", index, dsp->size);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun switch (index) {
285*4882a593Smuzhiyun case PCXHR_FIRMWARE_XLX_INT_INDEX:
286*4882a593Smuzhiyun pcxhr_reset_xilinx_com(mgr);
287*4882a593Smuzhiyun return pcxhr_load_xilinx_binary(mgr, dsp, 0);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun case PCXHR_FIRMWARE_XLX_COM_INDEX:
290*4882a593Smuzhiyun pcxhr_reset_xilinx_com(mgr);
291*4882a593Smuzhiyun return pcxhr_load_xilinx_binary(mgr, dsp, 1);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun case PCXHR_FIRMWARE_DSP_EPRM_INDEX:
294*4882a593Smuzhiyun pcxhr_reset_dsp(mgr);
295*4882a593Smuzhiyun return pcxhr_load_eeprom_binary(mgr, dsp);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun case PCXHR_FIRMWARE_DSP_BOOT_INDEX:
298*4882a593Smuzhiyun return pcxhr_load_boot_binary(mgr, dsp);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun case PCXHR_FIRMWARE_DSP_MAIN_INDEX:
301*4882a593Smuzhiyun err = pcxhr_load_dsp_binary(mgr, dsp);
302*4882a593Smuzhiyun if (err)
303*4882a593Smuzhiyun return err;
304*4882a593Smuzhiyun break; /* continue with first init */
305*4882a593Smuzhiyun default:
306*4882a593Smuzhiyun dev_err(&mgr->pci->dev, "wrong file index\n");
307*4882a593Smuzhiyun return -EFAULT;
308*4882a593Smuzhiyun } /* end of switch file index*/
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun /* first communication with embedded */
311*4882a593Smuzhiyun err = pcxhr_init_board(mgr);
312*4882a593Smuzhiyun if (err < 0) {
313*4882a593Smuzhiyun dev_err(&mgr->pci->dev, "pcxhr could not be set up\n");
314*4882a593Smuzhiyun return err;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun err = pcxhr_config_pipes(mgr);
317*4882a593Smuzhiyun if (err < 0) {
318*4882a593Smuzhiyun dev_err(&mgr->pci->dev, "pcxhr pipes could not be set up\n");
319*4882a593Smuzhiyun return err;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun /* create devices and mixer in accordance with HW options*/
322*4882a593Smuzhiyun for (card_index = 0; card_index < mgr->num_cards; card_index++) {
323*4882a593Smuzhiyun struct snd_pcxhr *chip = mgr->chip[card_index];
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun if ((err = pcxhr_create_pcm(chip)) < 0)
326*4882a593Smuzhiyun return err;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun if (card_index == 0) {
329*4882a593Smuzhiyun if ((err = pcxhr_create_mixer(chip->mgr)) < 0)
330*4882a593Smuzhiyun return err;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun if ((err = snd_card_register(chip->card)) < 0)
333*4882a593Smuzhiyun return err;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun err = pcxhr_start_pipes(mgr);
336*4882a593Smuzhiyun if (err < 0) {
337*4882a593Smuzhiyun dev_err(&mgr->pci->dev, "pcxhr pipes could not be started\n");
338*4882a593Smuzhiyun return err;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun dev_dbg(&mgr->pci->dev,
341*4882a593Smuzhiyun "pcxhr firmware downloaded and successfully set up\n");
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun return 0;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun /*
347*4882a593Smuzhiyun * fw loader entry
348*4882a593Smuzhiyun */
pcxhr_setup_firmware(struct pcxhr_mgr * mgr)349*4882a593Smuzhiyun int pcxhr_setup_firmware(struct pcxhr_mgr *mgr)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun static const char * const fw_files[][5] = {
352*4882a593Smuzhiyun [0] = { "xlxint.dat", "xlxc882hr.dat",
353*4882a593Smuzhiyun "dspe882.e56", "dspb882hr.b56", "dspd882.d56" },
354*4882a593Smuzhiyun [1] = { "xlxint.dat", "xlxc882e.dat",
355*4882a593Smuzhiyun "dspe882.e56", "dspb882e.b56", "dspd882.d56" },
356*4882a593Smuzhiyun [2] = { "xlxint.dat", "xlxc1222hr.dat",
357*4882a593Smuzhiyun "dspe882.e56", "dspb1222hr.b56", "dspd1222.d56" },
358*4882a593Smuzhiyun [3] = { "xlxint.dat", "xlxc1222e.dat",
359*4882a593Smuzhiyun "dspe882.e56", "dspb1222e.b56", "dspd1222.d56" },
360*4882a593Smuzhiyun [4] = { NULL, "xlxc222.dat",
361*4882a593Smuzhiyun "dspe924.e56", "dspb924.b56", "dspd222.d56" },
362*4882a593Smuzhiyun [5] = { NULL, "xlxc924.dat",
363*4882a593Smuzhiyun "dspe924.e56", "dspb924.b56", "dspd222.d56" },
364*4882a593Smuzhiyun };
365*4882a593Smuzhiyun char path[32];
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun const struct firmware *fw_entry;
368*4882a593Smuzhiyun int i, err;
369*4882a593Smuzhiyun int fw_set = mgr->fw_file_set;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun for (i = 0; i < 5; i++) {
372*4882a593Smuzhiyun if (!fw_files[fw_set][i])
373*4882a593Smuzhiyun continue;
374*4882a593Smuzhiyun sprintf(path, "pcxhr/%s", fw_files[fw_set][i]);
375*4882a593Smuzhiyun if (request_firmware(&fw_entry, path, &mgr->pci->dev)) {
376*4882a593Smuzhiyun dev_err(&mgr->pci->dev,
377*4882a593Smuzhiyun "pcxhr: can't load firmware %s\n",
378*4882a593Smuzhiyun path);
379*4882a593Smuzhiyun return -ENOENT;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun /* fake hwdep dsp record */
382*4882a593Smuzhiyun err = pcxhr_dsp_load(mgr, i, fw_entry);
383*4882a593Smuzhiyun release_firmware(fw_entry);
384*4882a593Smuzhiyun if (err < 0)
385*4882a593Smuzhiyun return err;
386*4882a593Smuzhiyun mgr->dsp_loaded |= 1 << i;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun return 0;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/xlxint.dat");
392*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/xlxc882hr.dat");
393*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/xlxc882e.dat");
394*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/dspe882.e56");
395*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/dspb882hr.b56");
396*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/dspb882e.b56");
397*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/dspd882.d56");
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/xlxc1222hr.dat");
400*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/xlxc1222e.dat");
401*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/dspb1222hr.b56");
402*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/dspb1222e.b56");
403*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/dspd1222.d56");
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/xlxc222.dat");
406*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/xlxc924.dat");
407*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/dspe924.e56");
408*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/dspb924.b56");
409*4882a593Smuzhiyun MODULE_FIRMWARE("pcxhr/dspd222.d56");
410