xref: /OK3568_Linux_fs/kernel/sound/pci/oxygen/xonar_wm87x6.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * card driver for models with WM8776/WM8766 DACs (Xonar DS/HDAV1.3 Slim)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun  * Xonar DS
10*4882a593Smuzhiyun  * --------
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * CMI8788:
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *   SPI 0 -> WM8766 (surround, center/LFE, back)
15*4882a593Smuzhiyun  *   SPI 1 -> WM8776 (front, input)
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  *   GPIO 4 <- headphone detect, 0 = plugged
18*4882a593Smuzhiyun  *   GPIO 6 -> route input jack to mic-in (0) or line-in (1)
19*4882a593Smuzhiyun  *   GPIO 7 -> enable output to front L/R speaker channels
20*4882a593Smuzhiyun  *   GPIO 8 -> enable output to other speaker channels and front panel headphone
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  * WM8776:
23*4882a593Smuzhiyun  *
24*4882a593Smuzhiyun  *   input 1 <- line
25*4882a593Smuzhiyun  *   input 2 <- mic
26*4882a593Smuzhiyun  *   input 3 <- front mic
27*4882a593Smuzhiyun  *   input 4 <- aux
28*4882a593Smuzhiyun  */
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun  * Xonar HDAV1.3 Slim
32*4882a593Smuzhiyun  * ------------------
33*4882a593Smuzhiyun  *
34*4882a593Smuzhiyun  * CMI8788:
35*4882a593Smuzhiyun  *
36*4882a593Smuzhiyun  *   I²C <-> WM8776 (addr 0011010)
37*4882a593Smuzhiyun  *
38*4882a593Smuzhiyun  *   GPIO 0  -> disable HDMI output
39*4882a593Smuzhiyun  *   GPIO 1  -> enable HP output
40*4882a593Smuzhiyun  *   GPIO 6  -> firmware EEPROM I²C clock
41*4882a593Smuzhiyun  *   GPIO 7 <-> firmware EEPROM I²C data
42*4882a593Smuzhiyun  *
43*4882a593Smuzhiyun  *   UART <-> HDMI controller
44*4882a593Smuzhiyun  *
45*4882a593Smuzhiyun  * WM8776:
46*4882a593Smuzhiyun  *
47*4882a593Smuzhiyun  *   input 1 <- mic
48*4882a593Smuzhiyun  *   input 2 <- aux
49*4882a593Smuzhiyun  */
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #include <linux/pci.h>
52*4882a593Smuzhiyun #include <linux/delay.h>
53*4882a593Smuzhiyun #include <sound/control.h>
54*4882a593Smuzhiyun #include <sound/core.h>
55*4882a593Smuzhiyun #include <sound/info.h>
56*4882a593Smuzhiyun #include <sound/jack.h>
57*4882a593Smuzhiyun #include <sound/pcm.h>
58*4882a593Smuzhiyun #include <sound/pcm_params.h>
59*4882a593Smuzhiyun #include <sound/tlv.h>
60*4882a593Smuzhiyun #include "xonar.h"
61*4882a593Smuzhiyun #include "wm8776.h"
62*4882a593Smuzhiyun #include "wm8766.h"
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define GPIO_DS_HP_DETECT	0x0010
65*4882a593Smuzhiyun #define GPIO_DS_INPUT_ROUTE	0x0040
66*4882a593Smuzhiyun #define GPIO_DS_OUTPUT_FRONTLR	0x0080
67*4882a593Smuzhiyun #define GPIO_DS_OUTPUT_ENABLE	0x0100
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define GPIO_SLIM_HDMI_DISABLE	0x0001
70*4882a593Smuzhiyun #define GPIO_SLIM_OUTPUT_ENABLE	0x0002
71*4882a593Smuzhiyun #define GPIO_SLIM_FIRMWARE_CLK	0x0040
72*4882a593Smuzhiyun #define GPIO_SLIM_FIRMWARE_DATA	0x0080
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define I2C_DEVICE_WM8776	0x34	/* 001101, 0, /W=0 */
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define LC_CONTROL_LIMITER	0x40000000
77*4882a593Smuzhiyun #define LC_CONTROL_ALC		0x20000000
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun struct xonar_wm87x6 {
80*4882a593Smuzhiyun 	struct xonar_generic generic;
81*4882a593Smuzhiyun 	u16 wm8776_regs[0x17];
82*4882a593Smuzhiyun 	u16 wm8766_regs[0x10];
83*4882a593Smuzhiyun 	struct snd_kcontrol *line_adcmux_control;
84*4882a593Smuzhiyun 	struct snd_kcontrol *mic_adcmux_control;
85*4882a593Smuzhiyun 	struct snd_kcontrol *lc_controls[13];
86*4882a593Smuzhiyun 	struct snd_jack *hp_jack;
87*4882a593Smuzhiyun 	struct xonar_hdmi hdmi;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
wm8776_write_spi(struct oxygen * chip,unsigned int reg,unsigned int value)90*4882a593Smuzhiyun static void wm8776_write_spi(struct oxygen *chip,
91*4882a593Smuzhiyun 			     unsigned int reg, unsigned int value)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
94*4882a593Smuzhiyun 			 OXYGEN_SPI_DATA_LENGTH_2 |
95*4882a593Smuzhiyun 			 OXYGEN_SPI_CLOCK_160 |
96*4882a593Smuzhiyun 			 (1 << OXYGEN_SPI_CODEC_SHIFT) |
97*4882a593Smuzhiyun 			 OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
98*4882a593Smuzhiyun 			 (reg << 9) | value);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
wm8776_write_i2c(struct oxygen * chip,unsigned int reg,unsigned int value)101*4882a593Smuzhiyun static void wm8776_write_i2c(struct oxygen *chip,
102*4882a593Smuzhiyun 			     unsigned int reg, unsigned int value)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	oxygen_write_i2c(chip, I2C_DEVICE_WM8776,
105*4882a593Smuzhiyun 			 (reg << 1) | (value >> 8), value);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun 
wm8776_write(struct oxygen * chip,unsigned int reg,unsigned int value)108*4882a593Smuzhiyun static void wm8776_write(struct oxygen *chip,
109*4882a593Smuzhiyun 			 unsigned int reg, unsigned int value)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	if ((chip->model.function_flags & OXYGEN_FUNCTION_2WIRE_SPI_MASK) ==
114*4882a593Smuzhiyun 	    OXYGEN_FUNCTION_SPI)
115*4882a593Smuzhiyun 		wm8776_write_spi(chip, reg, value);
116*4882a593Smuzhiyun 	else
117*4882a593Smuzhiyun 		wm8776_write_i2c(chip, reg, value);
118*4882a593Smuzhiyun 	if (reg < ARRAY_SIZE(data->wm8776_regs)) {
119*4882a593Smuzhiyun 		/* reg >= WM8776_HPLVOL is always true */
120*4882a593Smuzhiyun 		if (reg <= WM8776_DACMASTER)
121*4882a593Smuzhiyun 			value &= ~WM8776_UPDATE;
122*4882a593Smuzhiyun 		data->wm8776_regs[reg] = value;
123*4882a593Smuzhiyun 	}
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
wm8776_write_cached(struct oxygen * chip,unsigned int reg,unsigned int value)126*4882a593Smuzhiyun static void wm8776_write_cached(struct oxygen *chip,
127*4882a593Smuzhiyun 				unsigned int reg, unsigned int value)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	if (reg >= ARRAY_SIZE(data->wm8776_regs) ||
132*4882a593Smuzhiyun 	    value != data->wm8776_regs[reg])
133*4882a593Smuzhiyun 		wm8776_write(chip, reg, value);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
wm8766_write(struct oxygen * chip,unsigned int reg,unsigned int value)136*4882a593Smuzhiyun static void wm8766_write(struct oxygen *chip,
137*4882a593Smuzhiyun 			 unsigned int reg, unsigned int value)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
142*4882a593Smuzhiyun 			 OXYGEN_SPI_DATA_LENGTH_2 |
143*4882a593Smuzhiyun 			 OXYGEN_SPI_CLOCK_160 |
144*4882a593Smuzhiyun 			 (0 << OXYGEN_SPI_CODEC_SHIFT) |
145*4882a593Smuzhiyun 			 OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
146*4882a593Smuzhiyun 			 (reg << 9) | value);
147*4882a593Smuzhiyun 	if (reg < ARRAY_SIZE(data->wm8766_regs)) {
148*4882a593Smuzhiyun 		/* reg >= WM8766_LDA1 is always true */
149*4882a593Smuzhiyun 		if (reg <= WM8766_RDA1 ||
150*4882a593Smuzhiyun 		    (reg >= WM8766_LDA2 && reg <= WM8766_MASTDA))
151*4882a593Smuzhiyun 			value &= ~WM8766_UPDATE;
152*4882a593Smuzhiyun 		data->wm8766_regs[reg] = value;
153*4882a593Smuzhiyun 	}
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
wm8766_write_cached(struct oxygen * chip,unsigned int reg,unsigned int value)156*4882a593Smuzhiyun static void wm8766_write_cached(struct oxygen *chip,
157*4882a593Smuzhiyun 				unsigned int reg, unsigned int value)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	if (reg >= ARRAY_SIZE(data->wm8766_regs) ||
162*4882a593Smuzhiyun 	    value != data->wm8766_regs[reg])
163*4882a593Smuzhiyun 		wm8766_write(chip, reg, value);
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
wm8776_registers_init(struct oxygen * chip)166*4882a593Smuzhiyun static void wm8776_registers_init(struct oxygen *chip)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_RESET, 0);
171*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_PHASESWAP, WM8776_PH_MASK);
172*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_DACCTRL1, WM8776_DZCEN |
173*4882a593Smuzhiyun 		     WM8776_PL_LEFT_LEFT | WM8776_PL_RIGHT_RIGHT);
174*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_DACMUTE, chip->dac_mute ? WM8776_DMUTE : 0);
175*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_DACIFCTRL,
176*4882a593Smuzhiyun 		     WM8776_DACFMT_LJUST | WM8776_DACWL_24);
177*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_ADCIFCTRL,
178*4882a593Smuzhiyun 		     data->wm8776_regs[WM8776_ADCIFCTRL]);
179*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_MSTRCTRL, data->wm8776_regs[WM8776_MSTRCTRL]);
180*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_PWRDOWN, data->wm8776_regs[WM8776_PWRDOWN]);
181*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_HPLVOL, data->wm8776_regs[WM8776_HPLVOL]);
182*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_HPRVOL, data->wm8776_regs[WM8776_HPRVOL] |
183*4882a593Smuzhiyun 		     WM8776_UPDATE);
184*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_ADCLVOL, data->wm8776_regs[WM8776_ADCLVOL]);
185*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_ADCRVOL, data->wm8776_regs[WM8776_ADCRVOL]);
186*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_ADCMUX, data->wm8776_regs[WM8776_ADCMUX]);
187*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_DACLVOL, chip->dac_volume[0]);
188*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_DACRVOL, chip->dac_volume[1] | WM8776_UPDATE);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
wm8766_registers_init(struct oxygen * chip)191*4882a593Smuzhiyun static void wm8766_registers_init(struct oxygen *chip)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	wm8766_write(chip, WM8766_RESET, 0);
196*4882a593Smuzhiyun 	wm8766_write(chip, WM8766_DAC_CTRL, data->wm8766_regs[WM8766_DAC_CTRL]);
197*4882a593Smuzhiyun 	wm8766_write(chip, WM8766_INT_CTRL, WM8766_FMT_LJUST | WM8766_IWL_24);
198*4882a593Smuzhiyun 	wm8766_write(chip, WM8766_DAC_CTRL2,
199*4882a593Smuzhiyun 		     WM8766_ZCD | (chip->dac_mute ? WM8766_DMUTE_MASK : 0));
200*4882a593Smuzhiyun 	wm8766_write(chip, WM8766_LDA1, chip->dac_volume[2]);
201*4882a593Smuzhiyun 	wm8766_write(chip, WM8766_RDA1, chip->dac_volume[3]);
202*4882a593Smuzhiyun 	wm8766_write(chip, WM8766_LDA2, chip->dac_volume[4]);
203*4882a593Smuzhiyun 	wm8766_write(chip, WM8766_RDA2, chip->dac_volume[5]);
204*4882a593Smuzhiyun 	wm8766_write(chip, WM8766_LDA3, chip->dac_volume[6]);
205*4882a593Smuzhiyun 	wm8766_write(chip, WM8766_RDA3, chip->dac_volume[7] | WM8766_UPDATE);
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
wm8776_init(struct oxygen * chip)208*4882a593Smuzhiyun static void wm8776_init(struct oxygen *chip)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	data->wm8776_regs[WM8776_HPLVOL] = (0x79 - 60) | WM8776_HPZCEN;
213*4882a593Smuzhiyun 	data->wm8776_regs[WM8776_HPRVOL] = (0x79 - 60) | WM8776_HPZCEN;
214*4882a593Smuzhiyun 	data->wm8776_regs[WM8776_ADCIFCTRL] =
215*4882a593Smuzhiyun 		WM8776_ADCFMT_LJUST | WM8776_ADCWL_24 | WM8776_ADCMCLK;
216*4882a593Smuzhiyun 	data->wm8776_regs[WM8776_MSTRCTRL] =
217*4882a593Smuzhiyun 		WM8776_ADCRATE_256 | WM8776_DACRATE_256;
218*4882a593Smuzhiyun 	data->wm8776_regs[WM8776_PWRDOWN] = WM8776_HPPD;
219*4882a593Smuzhiyun 	data->wm8776_regs[WM8776_ADCLVOL] = 0xa5 | WM8776_ZCA;
220*4882a593Smuzhiyun 	data->wm8776_regs[WM8776_ADCRVOL] = 0xa5 | WM8776_ZCA;
221*4882a593Smuzhiyun 	data->wm8776_regs[WM8776_ADCMUX] = 0x001;
222*4882a593Smuzhiyun 	wm8776_registers_init(chip);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun 
wm8766_init(struct oxygen * chip)225*4882a593Smuzhiyun static void wm8766_init(struct oxygen *chip)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	data->wm8766_regs[WM8766_DAC_CTRL] =
230*4882a593Smuzhiyun 		WM8766_PL_LEFT_LEFT | WM8766_PL_RIGHT_RIGHT;
231*4882a593Smuzhiyun 	wm8766_registers_init(chip);
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun 
xonar_ds_handle_hp_jack(struct oxygen * chip)234*4882a593Smuzhiyun static void xonar_ds_handle_hp_jack(struct oxygen *chip)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
237*4882a593Smuzhiyun 	bool hp_plugged;
238*4882a593Smuzhiyun 	unsigned int reg;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	mutex_lock(&chip->mutex);
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	hp_plugged = !(oxygen_read16(chip, OXYGEN_GPIO_DATA) &
243*4882a593Smuzhiyun 		       GPIO_DS_HP_DETECT);
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
246*4882a593Smuzhiyun 			      hp_plugged ? 0 : GPIO_DS_OUTPUT_FRONTLR,
247*4882a593Smuzhiyun 			      GPIO_DS_OUTPUT_FRONTLR);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	reg = data->wm8766_regs[WM8766_DAC_CTRL] & ~WM8766_MUTEALL;
250*4882a593Smuzhiyun 	if (hp_plugged)
251*4882a593Smuzhiyun 		reg |= WM8766_MUTEALL;
252*4882a593Smuzhiyun 	wm8766_write_cached(chip, WM8766_DAC_CTRL, reg);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	snd_jack_report(data->hp_jack, hp_plugged ? SND_JACK_HEADPHONE : 0);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	mutex_unlock(&chip->mutex);
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun 
xonar_ds_init(struct oxygen * chip)259*4882a593Smuzhiyun static void xonar_ds_init(struct oxygen *chip)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	data->generic.anti_pop_delay = 300;
264*4882a593Smuzhiyun 	data->generic.output_enable_bit = GPIO_DS_OUTPUT_ENABLE;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	wm8776_init(chip);
267*4882a593Smuzhiyun 	wm8766_init(chip);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
270*4882a593Smuzhiyun 			  GPIO_DS_INPUT_ROUTE | GPIO_DS_OUTPUT_FRONTLR);
271*4882a593Smuzhiyun 	oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL,
272*4882a593Smuzhiyun 			    GPIO_DS_HP_DETECT);
273*4882a593Smuzhiyun 	oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_DS_INPUT_ROUTE);
274*4882a593Smuzhiyun 	oxygen_set_bits16(chip, OXYGEN_GPIO_INTERRUPT_MASK, GPIO_DS_HP_DETECT);
275*4882a593Smuzhiyun 	chip->interrupt_mask |= OXYGEN_INT_GPIO;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	xonar_enable_output(chip);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	snd_jack_new(chip->card, "Headphone",
280*4882a593Smuzhiyun 		     SND_JACK_HEADPHONE, &data->hp_jack, false, false);
281*4882a593Smuzhiyun 	xonar_ds_handle_hp_jack(chip);
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	snd_component_add(chip->card, "WM8776");
284*4882a593Smuzhiyun 	snd_component_add(chip->card, "WM8766");
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun 
xonar_hdav_slim_init(struct oxygen * chip)287*4882a593Smuzhiyun static void xonar_hdav_slim_init(struct oxygen *chip)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	data->generic.anti_pop_delay = 300;
292*4882a593Smuzhiyun 	data->generic.output_enable_bit = GPIO_SLIM_OUTPUT_ENABLE;
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	wm8776_init(chip);
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
297*4882a593Smuzhiyun 			  GPIO_SLIM_HDMI_DISABLE |
298*4882a593Smuzhiyun 			  GPIO_SLIM_FIRMWARE_CLK |
299*4882a593Smuzhiyun 			  GPIO_SLIM_FIRMWARE_DATA);
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	xonar_hdmi_init(chip, &data->hdmi);
302*4882a593Smuzhiyun 	xonar_enable_output(chip);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	snd_component_add(chip->card, "WM8776");
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun 
xonar_ds_cleanup(struct oxygen * chip)307*4882a593Smuzhiyun static void xonar_ds_cleanup(struct oxygen *chip)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun 	xonar_disable_output(chip);
310*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_RESET, 0);
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun 
xonar_hdav_slim_cleanup(struct oxygen * chip)313*4882a593Smuzhiyun static void xonar_hdav_slim_cleanup(struct oxygen *chip)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun 	xonar_hdmi_cleanup(chip);
316*4882a593Smuzhiyun 	xonar_disable_output(chip);
317*4882a593Smuzhiyun 	wm8776_write(chip, WM8776_RESET, 0);
318*4882a593Smuzhiyun 	msleep(2);
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun 
xonar_ds_suspend(struct oxygen * chip)321*4882a593Smuzhiyun static void xonar_ds_suspend(struct oxygen *chip)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun 	xonar_ds_cleanup(chip);
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun 
xonar_hdav_slim_suspend(struct oxygen * chip)326*4882a593Smuzhiyun static void xonar_hdav_slim_suspend(struct oxygen *chip)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun 	xonar_hdav_slim_cleanup(chip);
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun 
xonar_ds_resume(struct oxygen * chip)331*4882a593Smuzhiyun static void xonar_ds_resume(struct oxygen *chip)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun 	wm8776_registers_init(chip);
334*4882a593Smuzhiyun 	wm8766_registers_init(chip);
335*4882a593Smuzhiyun 	xonar_enable_output(chip);
336*4882a593Smuzhiyun 	xonar_ds_handle_hp_jack(chip);
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun 
xonar_hdav_slim_resume(struct oxygen * chip)339*4882a593Smuzhiyun static void xonar_hdav_slim_resume(struct oxygen *chip)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	wm8776_registers_init(chip);
344*4882a593Smuzhiyun 	xonar_hdmi_resume(chip, &data->hdmi);
345*4882a593Smuzhiyun 	xonar_enable_output(chip);
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun 
wm8776_adc_hardware_filter(unsigned int channel,struct snd_pcm_hardware * hardware)348*4882a593Smuzhiyun static void wm8776_adc_hardware_filter(unsigned int channel,
349*4882a593Smuzhiyun 				       struct snd_pcm_hardware *hardware)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun 	if (channel == PCM_A) {
352*4882a593Smuzhiyun 		hardware->rates = SNDRV_PCM_RATE_32000 |
353*4882a593Smuzhiyun 				  SNDRV_PCM_RATE_44100 |
354*4882a593Smuzhiyun 				  SNDRV_PCM_RATE_48000 |
355*4882a593Smuzhiyun 				  SNDRV_PCM_RATE_64000 |
356*4882a593Smuzhiyun 				  SNDRV_PCM_RATE_88200 |
357*4882a593Smuzhiyun 				  SNDRV_PCM_RATE_96000;
358*4882a593Smuzhiyun 		hardware->rate_max = 96000;
359*4882a593Smuzhiyun 	}
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun 
xonar_hdav_slim_hardware_filter(unsigned int channel,struct snd_pcm_hardware * hardware)362*4882a593Smuzhiyun static void xonar_hdav_slim_hardware_filter(unsigned int channel,
363*4882a593Smuzhiyun 					    struct snd_pcm_hardware *hardware)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun 	wm8776_adc_hardware_filter(channel, hardware);
366*4882a593Smuzhiyun 	xonar_hdmi_pcm_hardware_filter(channel, hardware);
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun 
set_wm87x6_dac_params(struct oxygen * chip,struct snd_pcm_hw_params * params)369*4882a593Smuzhiyun static void set_wm87x6_dac_params(struct oxygen *chip,
370*4882a593Smuzhiyun 				  struct snd_pcm_hw_params *params)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun 
set_wm8776_adc_params(struct oxygen * chip,struct snd_pcm_hw_params * params)374*4882a593Smuzhiyun static void set_wm8776_adc_params(struct oxygen *chip,
375*4882a593Smuzhiyun 				  struct snd_pcm_hw_params *params)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun 	u16 reg;
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	reg = WM8776_ADCRATE_256 | WM8776_DACRATE_256;
380*4882a593Smuzhiyun 	if (params_rate(params) > 48000)
381*4882a593Smuzhiyun 		reg |= WM8776_ADCOSR;
382*4882a593Smuzhiyun 	wm8776_write_cached(chip, WM8776_MSTRCTRL, reg);
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun 
set_hdav_slim_dac_params(struct oxygen * chip,struct snd_pcm_hw_params * params)385*4882a593Smuzhiyun static void set_hdav_slim_dac_params(struct oxygen *chip,
386*4882a593Smuzhiyun 				     struct snd_pcm_hw_params *params)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	xonar_set_hdmi_params(chip, &data->hdmi, params);
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun 
update_wm8776_volume(struct oxygen * chip)393*4882a593Smuzhiyun static void update_wm8776_volume(struct oxygen *chip)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
396*4882a593Smuzhiyun 	u8 to_change;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	if (chip->dac_volume[0] == chip->dac_volume[1]) {
399*4882a593Smuzhiyun 		if (chip->dac_volume[0] != data->wm8776_regs[WM8776_DACLVOL] ||
400*4882a593Smuzhiyun 		    chip->dac_volume[1] != data->wm8776_regs[WM8776_DACRVOL]) {
401*4882a593Smuzhiyun 			wm8776_write(chip, WM8776_DACMASTER,
402*4882a593Smuzhiyun 				     chip->dac_volume[0] | WM8776_UPDATE);
403*4882a593Smuzhiyun 			data->wm8776_regs[WM8776_DACLVOL] = chip->dac_volume[0];
404*4882a593Smuzhiyun 			data->wm8776_regs[WM8776_DACRVOL] = chip->dac_volume[0];
405*4882a593Smuzhiyun 		}
406*4882a593Smuzhiyun 	} else {
407*4882a593Smuzhiyun 		to_change = (chip->dac_volume[0] !=
408*4882a593Smuzhiyun 			     data->wm8776_regs[WM8776_DACLVOL]) << 0;
409*4882a593Smuzhiyun 		to_change |= (chip->dac_volume[1] !=
410*4882a593Smuzhiyun 			      data->wm8776_regs[WM8776_DACLVOL]) << 1;
411*4882a593Smuzhiyun 		if (to_change & 1)
412*4882a593Smuzhiyun 			wm8776_write(chip, WM8776_DACLVOL, chip->dac_volume[0] |
413*4882a593Smuzhiyun 				     ((to_change & 2) ? 0 : WM8776_UPDATE));
414*4882a593Smuzhiyun 		if (to_change & 2)
415*4882a593Smuzhiyun 			wm8776_write(chip, WM8776_DACRVOL,
416*4882a593Smuzhiyun 				     chip->dac_volume[1] | WM8776_UPDATE);
417*4882a593Smuzhiyun 	}
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun 
update_wm87x6_volume(struct oxygen * chip)420*4882a593Smuzhiyun static void update_wm87x6_volume(struct oxygen *chip)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun 	static const u8 wm8766_regs[6] = {
423*4882a593Smuzhiyun 		WM8766_LDA1, WM8766_RDA1,
424*4882a593Smuzhiyun 		WM8766_LDA2, WM8766_RDA2,
425*4882a593Smuzhiyun 		WM8766_LDA3, WM8766_RDA3,
426*4882a593Smuzhiyun 	};
427*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
428*4882a593Smuzhiyun 	unsigned int i;
429*4882a593Smuzhiyun 	u8 to_change;
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	update_wm8776_volume(chip);
432*4882a593Smuzhiyun 	if (chip->dac_volume[2] == chip->dac_volume[3] &&
433*4882a593Smuzhiyun 	    chip->dac_volume[2] == chip->dac_volume[4] &&
434*4882a593Smuzhiyun 	    chip->dac_volume[2] == chip->dac_volume[5] &&
435*4882a593Smuzhiyun 	    chip->dac_volume[2] == chip->dac_volume[6] &&
436*4882a593Smuzhiyun 	    chip->dac_volume[2] == chip->dac_volume[7]) {
437*4882a593Smuzhiyun 		to_change = 0;
438*4882a593Smuzhiyun 		for (i = 0; i < 6; ++i)
439*4882a593Smuzhiyun 			if (chip->dac_volume[2] !=
440*4882a593Smuzhiyun 			    data->wm8766_regs[wm8766_regs[i]])
441*4882a593Smuzhiyun 				to_change = 1;
442*4882a593Smuzhiyun 		if (to_change) {
443*4882a593Smuzhiyun 			wm8766_write(chip, WM8766_MASTDA,
444*4882a593Smuzhiyun 				     chip->dac_volume[2] | WM8766_UPDATE);
445*4882a593Smuzhiyun 			for (i = 0; i < 6; ++i)
446*4882a593Smuzhiyun 				data->wm8766_regs[wm8766_regs[i]] =
447*4882a593Smuzhiyun 					chip->dac_volume[2];
448*4882a593Smuzhiyun 		}
449*4882a593Smuzhiyun 	} else {
450*4882a593Smuzhiyun 		to_change = 0;
451*4882a593Smuzhiyun 		for (i = 0; i < 6; ++i)
452*4882a593Smuzhiyun 			to_change |= (chip->dac_volume[2 + i] !=
453*4882a593Smuzhiyun 				      data->wm8766_regs[wm8766_regs[i]]) << i;
454*4882a593Smuzhiyun 		for (i = 0; i < 6; ++i)
455*4882a593Smuzhiyun 			if (to_change & (1 << i))
456*4882a593Smuzhiyun 				wm8766_write(chip, wm8766_regs[i],
457*4882a593Smuzhiyun 					     chip->dac_volume[2 + i] |
458*4882a593Smuzhiyun 					     ((to_change & (0x3e << i))
459*4882a593Smuzhiyun 					      ? 0 : WM8766_UPDATE));
460*4882a593Smuzhiyun 	}
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun 
update_wm8776_mute(struct oxygen * chip)463*4882a593Smuzhiyun static void update_wm8776_mute(struct oxygen *chip)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun 	wm8776_write_cached(chip, WM8776_DACMUTE,
466*4882a593Smuzhiyun 			    chip->dac_mute ? WM8776_DMUTE : 0);
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun 
update_wm87x6_mute(struct oxygen * chip)469*4882a593Smuzhiyun static void update_wm87x6_mute(struct oxygen *chip)
470*4882a593Smuzhiyun {
471*4882a593Smuzhiyun 	update_wm8776_mute(chip);
472*4882a593Smuzhiyun 	wm8766_write_cached(chip, WM8766_DAC_CTRL2, WM8766_ZCD |
473*4882a593Smuzhiyun 			    (chip->dac_mute ? WM8766_DMUTE_MASK : 0));
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun 
update_wm8766_center_lfe_mix(struct oxygen * chip,bool mixed)476*4882a593Smuzhiyun static void update_wm8766_center_lfe_mix(struct oxygen *chip, bool mixed)
477*4882a593Smuzhiyun {
478*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
479*4882a593Smuzhiyun 	unsigned int reg;
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	/*
482*4882a593Smuzhiyun 	 * The WM8766 can mix left and right channels, but this setting
483*4882a593Smuzhiyun 	 * applies to all three stereo pairs.
484*4882a593Smuzhiyun 	 */
485*4882a593Smuzhiyun 	reg = data->wm8766_regs[WM8766_DAC_CTRL] &
486*4882a593Smuzhiyun 		~(WM8766_PL_LEFT_MASK | WM8766_PL_RIGHT_MASK);
487*4882a593Smuzhiyun 	if (mixed)
488*4882a593Smuzhiyun 		reg |= WM8766_PL_LEFT_LRMIX | WM8766_PL_RIGHT_LRMIX;
489*4882a593Smuzhiyun 	else
490*4882a593Smuzhiyun 		reg |= WM8766_PL_LEFT_LEFT | WM8766_PL_RIGHT_RIGHT;
491*4882a593Smuzhiyun 	wm8766_write_cached(chip, WM8766_DAC_CTRL, reg);
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun 
xonar_ds_gpio_changed(struct oxygen * chip)494*4882a593Smuzhiyun static void xonar_ds_gpio_changed(struct oxygen *chip)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun 	xonar_ds_handle_hp_jack(chip);
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun 
wm8776_bit_switch_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)499*4882a593Smuzhiyun static int wm8776_bit_switch_get(struct snd_kcontrol *ctl,
500*4882a593Smuzhiyun 				 struct snd_ctl_elem_value *value)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
503*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
504*4882a593Smuzhiyun 	u16 bit = ctl->private_value & 0xffff;
505*4882a593Smuzhiyun 	unsigned int reg_index = (ctl->private_value >> 16) & 0xff;
506*4882a593Smuzhiyun 	bool invert = (ctl->private_value >> 24) & 1;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	value->value.integer.value[0] =
509*4882a593Smuzhiyun 		((data->wm8776_regs[reg_index] & bit) != 0) ^ invert;
510*4882a593Smuzhiyun 	return 0;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun 
wm8776_bit_switch_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)513*4882a593Smuzhiyun static int wm8776_bit_switch_put(struct snd_kcontrol *ctl,
514*4882a593Smuzhiyun 				 struct snd_ctl_elem_value *value)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
517*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
518*4882a593Smuzhiyun 	u16 bit = ctl->private_value & 0xffff;
519*4882a593Smuzhiyun 	u16 reg_value;
520*4882a593Smuzhiyun 	unsigned int reg_index = (ctl->private_value >> 16) & 0xff;
521*4882a593Smuzhiyun 	bool invert = (ctl->private_value >> 24) & 1;
522*4882a593Smuzhiyun 	int changed;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	mutex_lock(&chip->mutex);
525*4882a593Smuzhiyun 	reg_value = data->wm8776_regs[reg_index] & ~bit;
526*4882a593Smuzhiyun 	if (value->value.integer.value[0] ^ invert)
527*4882a593Smuzhiyun 		reg_value |= bit;
528*4882a593Smuzhiyun 	changed = reg_value != data->wm8776_regs[reg_index];
529*4882a593Smuzhiyun 	if (changed)
530*4882a593Smuzhiyun 		wm8776_write(chip, reg_index, reg_value);
531*4882a593Smuzhiyun 	mutex_unlock(&chip->mutex);
532*4882a593Smuzhiyun 	return changed;
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun 
wm8776_field_enum_info(struct snd_kcontrol * ctl,struct snd_ctl_elem_info * info)535*4882a593Smuzhiyun static int wm8776_field_enum_info(struct snd_kcontrol *ctl,
536*4882a593Smuzhiyun 				  struct snd_ctl_elem_info *info)
537*4882a593Smuzhiyun {
538*4882a593Smuzhiyun 	static const char *const hld[16] = {
539*4882a593Smuzhiyun 		"0 ms", "2.67 ms", "5.33 ms", "10.6 ms",
540*4882a593Smuzhiyun 		"21.3 ms", "42.7 ms", "85.3 ms", "171 ms",
541*4882a593Smuzhiyun 		"341 ms", "683 ms", "1.37 s", "2.73 s",
542*4882a593Smuzhiyun 		"5.46 s", "10.9 s", "21.8 s", "43.7 s",
543*4882a593Smuzhiyun 	};
544*4882a593Smuzhiyun 	static const char *const atk_lim[11] = {
545*4882a593Smuzhiyun 		"0.25 ms", "0.5 ms", "1 ms", "2 ms",
546*4882a593Smuzhiyun 		"4 ms", "8 ms", "16 ms", "32 ms",
547*4882a593Smuzhiyun 		"64 ms", "128 ms", "256 ms",
548*4882a593Smuzhiyun 	};
549*4882a593Smuzhiyun 	static const char *const atk_alc[11] = {
550*4882a593Smuzhiyun 		"8.40 ms", "16.8 ms", "33.6 ms", "67.2 ms",
551*4882a593Smuzhiyun 		"134 ms", "269 ms", "538 ms", "1.08 s",
552*4882a593Smuzhiyun 		"2.15 s", "4.3 s", "8.6 s",
553*4882a593Smuzhiyun 	};
554*4882a593Smuzhiyun 	static const char *const dcy_lim[11] = {
555*4882a593Smuzhiyun 		"1.2 ms", "2.4 ms", "4.8 ms", "9.6 ms",
556*4882a593Smuzhiyun 		"19.2 ms", "38.4 ms", "76.8 ms", "154 ms",
557*4882a593Smuzhiyun 		"307 ms", "614 ms", "1.23 s",
558*4882a593Smuzhiyun 	};
559*4882a593Smuzhiyun 	static const char *const dcy_alc[11] = {
560*4882a593Smuzhiyun 		"33.5 ms", "67.0 ms", "134 ms", "268 ms",
561*4882a593Smuzhiyun 		"536 ms", "1.07 s", "2.14 s", "4.29 s",
562*4882a593Smuzhiyun 		"8.58 s", "17.2 s", "34.3 s",
563*4882a593Smuzhiyun 	};
564*4882a593Smuzhiyun 	static const char *const tranwin[8] = {
565*4882a593Smuzhiyun 		"0 us", "62.5 us", "125 us", "250 us",
566*4882a593Smuzhiyun 		"500 us", "1 ms", "2 ms", "4 ms",
567*4882a593Smuzhiyun 	};
568*4882a593Smuzhiyun 	u8 max;
569*4882a593Smuzhiyun 	const char *const *names;
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	max = (ctl->private_value >> 12) & 0xf;
572*4882a593Smuzhiyun 	switch ((ctl->private_value >> 24) & 0x1f) {
573*4882a593Smuzhiyun 	case WM8776_ALCCTRL2:
574*4882a593Smuzhiyun 		names = hld;
575*4882a593Smuzhiyun 		break;
576*4882a593Smuzhiyun 	case WM8776_ALCCTRL3:
577*4882a593Smuzhiyun 		if (((ctl->private_value >> 20) & 0xf) == 0) {
578*4882a593Smuzhiyun 			if (ctl->private_value & LC_CONTROL_LIMITER)
579*4882a593Smuzhiyun 				names = atk_lim;
580*4882a593Smuzhiyun 			else
581*4882a593Smuzhiyun 				names = atk_alc;
582*4882a593Smuzhiyun 		} else {
583*4882a593Smuzhiyun 			if (ctl->private_value & LC_CONTROL_LIMITER)
584*4882a593Smuzhiyun 				names = dcy_lim;
585*4882a593Smuzhiyun 			else
586*4882a593Smuzhiyun 				names = dcy_alc;
587*4882a593Smuzhiyun 		}
588*4882a593Smuzhiyun 		break;
589*4882a593Smuzhiyun 	case WM8776_LIMITER:
590*4882a593Smuzhiyun 		names = tranwin;
591*4882a593Smuzhiyun 		break;
592*4882a593Smuzhiyun 	default:
593*4882a593Smuzhiyun 		return -ENXIO;
594*4882a593Smuzhiyun 	}
595*4882a593Smuzhiyun 	return snd_ctl_enum_info(info, 1, max + 1, names);
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun 
wm8776_field_volume_info(struct snd_kcontrol * ctl,struct snd_ctl_elem_info * info)598*4882a593Smuzhiyun static int wm8776_field_volume_info(struct snd_kcontrol *ctl,
599*4882a593Smuzhiyun 				    struct snd_ctl_elem_info *info)
600*4882a593Smuzhiyun {
601*4882a593Smuzhiyun 	info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
602*4882a593Smuzhiyun 	info->count = 1;
603*4882a593Smuzhiyun 	info->value.integer.min = (ctl->private_value >> 8) & 0xf;
604*4882a593Smuzhiyun 	info->value.integer.max = (ctl->private_value >> 12) & 0xf;
605*4882a593Smuzhiyun 	return 0;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun 
wm8776_field_set_from_ctl(struct snd_kcontrol * ctl)608*4882a593Smuzhiyun static void wm8776_field_set_from_ctl(struct snd_kcontrol *ctl)
609*4882a593Smuzhiyun {
610*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
611*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
612*4882a593Smuzhiyun 	unsigned int value, reg_index, mode;
613*4882a593Smuzhiyun 	u8 min, max, shift;
614*4882a593Smuzhiyun 	u16 mask, reg_value;
615*4882a593Smuzhiyun 	bool invert;
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun 	if ((data->wm8776_regs[WM8776_ALCCTRL1] & WM8776_LCSEL_MASK) ==
618*4882a593Smuzhiyun 	    WM8776_LCSEL_LIMITER)
619*4882a593Smuzhiyun 		mode = LC_CONTROL_LIMITER;
620*4882a593Smuzhiyun 	else
621*4882a593Smuzhiyun 		mode = LC_CONTROL_ALC;
622*4882a593Smuzhiyun 	if (!(ctl->private_value & mode))
623*4882a593Smuzhiyun 		return;
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	value = ctl->private_value & 0xf;
626*4882a593Smuzhiyun 	min = (ctl->private_value >> 8) & 0xf;
627*4882a593Smuzhiyun 	max = (ctl->private_value >> 12) & 0xf;
628*4882a593Smuzhiyun 	mask = (ctl->private_value >> 16) & 0xf;
629*4882a593Smuzhiyun 	shift = (ctl->private_value >> 20) & 0xf;
630*4882a593Smuzhiyun 	reg_index = (ctl->private_value >> 24) & 0x1f;
631*4882a593Smuzhiyun 	invert = (ctl->private_value >> 29) & 0x1;
632*4882a593Smuzhiyun 
633*4882a593Smuzhiyun 	if (invert)
634*4882a593Smuzhiyun 		value = max - (value - min);
635*4882a593Smuzhiyun 	reg_value = data->wm8776_regs[reg_index];
636*4882a593Smuzhiyun 	reg_value &= ~(mask << shift);
637*4882a593Smuzhiyun 	reg_value |= value << shift;
638*4882a593Smuzhiyun 	wm8776_write_cached(chip, reg_index, reg_value);
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun 
wm8776_field_set(struct snd_kcontrol * ctl,unsigned int value)641*4882a593Smuzhiyun static int wm8776_field_set(struct snd_kcontrol *ctl, unsigned int value)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
644*4882a593Smuzhiyun 	u8 min, max;
645*4882a593Smuzhiyun 	int changed;
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	min = (ctl->private_value >> 8) & 0xf;
648*4882a593Smuzhiyun 	max = (ctl->private_value >> 12) & 0xf;
649*4882a593Smuzhiyun 	if (value < min || value > max)
650*4882a593Smuzhiyun 		return -EINVAL;
651*4882a593Smuzhiyun 	mutex_lock(&chip->mutex);
652*4882a593Smuzhiyun 	changed = value != (ctl->private_value & 0xf);
653*4882a593Smuzhiyun 	if (changed) {
654*4882a593Smuzhiyun 		ctl->private_value = (ctl->private_value & ~0xf) | value;
655*4882a593Smuzhiyun 		wm8776_field_set_from_ctl(ctl);
656*4882a593Smuzhiyun 	}
657*4882a593Smuzhiyun 	mutex_unlock(&chip->mutex);
658*4882a593Smuzhiyun 	return changed;
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun 
wm8776_field_enum_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)661*4882a593Smuzhiyun static int wm8776_field_enum_get(struct snd_kcontrol *ctl,
662*4882a593Smuzhiyun 				 struct snd_ctl_elem_value *value)
663*4882a593Smuzhiyun {
664*4882a593Smuzhiyun 	value->value.enumerated.item[0] = ctl->private_value & 0xf;
665*4882a593Smuzhiyun 	return 0;
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun 
wm8776_field_volume_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)668*4882a593Smuzhiyun static int wm8776_field_volume_get(struct snd_kcontrol *ctl,
669*4882a593Smuzhiyun 				   struct snd_ctl_elem_value *value)
670*4882a593Smuzhiyun {
671*4882a593Smuzhiyun 	value->value.integer.value[0] = ctl->private_value & 0xf;
672*4882a593Smuzhiyun 	return 0;
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun 
wm8776_field_enum_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)675*4882a593Smuzhiyun static int wm8776_field_enum_put(struct snd_kcontrol *ctl,
676*4882a593Smuzhiyun 				 struct snd_ctl_elem_value *value)
677*4882a593Smuzhiyun {
678*4882a593Smuzhiyun 	return wm8776_field_set(ctl, value->value.enumerated.item[0]);
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun 
wm8776_field_volume_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)681*4882a593Smuzhiyun static int wm8776_field_volume_put(struct snd_kcontrol *ctl,
682*4882a593Smuzhiyun 				   struct snd_ctl_elem_value *value)
683*4882a593Smuzhiyun {
684*4882a593Smuzhiyun 	return wm8776_field_set(ctl, value->value.integer.value[0]);
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun 
wm8776_hp_vol_info(struct snd_kcontrol * ctl,struct snd_ctl_elem_info * info)687*4882a593Smuzhiyun static int wm8776_hp_vol_info(struct snd_kcontrol *ctl,
688*4882a593Smuzhiyun 			      struct snd_ctl_elem_info *info)
689*4882a593Smuzhiyun {
690*4882a593Smuzhiyun 	info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
691*4882a593Smuzhiyun 	info->count = 2;
692*4882a593Smuzhiyun 	info->value.integer.min = 0x79 - 60;
693*4882a593Smuzhiyun 	info->value.integer.max = 0x7f;
694*4882a593Smuzhiyun 	return 0;
695*4882a593Smuzhiyun }
696*4882a593Smuzhiyun 
wm8776_hp_vol_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)697*4882a593Smuzhiyun static int wm8776_hp_vol_get(struct snd_kcontrol *ctl,
698*4882a593Smuzhiyun 			     struct snd_ctl_elem_value *value)
699*4882a593Smuzhiyun {
700*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
701*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	mutex_lock(&chip->mutex);
704*4882a593Smuzhiyun 	value->value.integer.value[0] =
705*4882a593Smuzhiyun 		data->wm8776_regs[WM8776_HPLVOL] & WM8776_HPATT_MASK;
706*4882a593Smuzhiyun 	value->value.integer.value[1] =
707*4882a593Smuzhiyun 		data->wm8776_regs[WM8776_HPRVOL] & WM8776_HPATT_MASK;
708*4882a593Smuzhiyun 	mutex_unlock(&chip->mutex);
709*4882a593Smuzhiyun 	return 0;
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun 
wm8776_hp_vol_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)712*4882a593Smuzhiyun static int wm8776_hp_vol_put(struct snd_kcontrol *ctl,
713*4882a593Smuzhiyun 			     struct snd_ctl_elem_value *value)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
716*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
717*4882a593Smuzhiyun 	u8 to_update;
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun 	mutex_lock(&chip->mutex);
720*4882a593Smuzhiyun 	to_update = (value->value.integer.value[0] !=
721*4882a593Smuzhiyun 		     (data->wm8776_regs[WM8776_HPLVOL] & WM8776_HPATT_MASK))
722*4882a593Smuzhiyun 		<< 0;
723*4882a593Smuzhiyun 	to_update |= (value->value.integer.value[1] !=
724*4882a593Smuzhiyun 		      (data->wm8776_regs[WM8776_HPRVOL] & WM8776_HPATT_MASK))
725*4882a593Smuzhiyun 		<< 1;
726*4882a593Smuzhiyun 	if (value->value.integer.value[0] == value->value.integer.value[1]) {
727*4882a593Smuzhiyun 		if (to_update) {
728*4882a593Smuzhiyun 			wm8776_write(chip, WM8776_HPMASTER,
729*4882a593Smuzhiyun 				     value->value.integer.value[0] |
730*4882a593Smuzhiyun 				     WM8776_HPZCEN | WM8776_UPDATE);
731*4882a593Smuzhiyun 			data->wm8776_regs[WM8776_HPLVOL] =
732*4882a593Smuzhiyun 				value->value.integer.value[0] | WM8776_HPZCEN;
733*4882a593Smuzhiyun 			data->wm8776_regs[WM8776_HPRVOL] =
734*4882a593Smuzhiyun 				value->value.integer.value[0] | WM8776_HPZCEN;
735*4882a593Smuzhiyun 		}
736*4882a593Smuzhiyun 	} else {
737*4882a593Smuzhiyun 		if (to_update & 1)
738*4882a593Smuzhiyun 			wm8776_write(chip, WM8776_HPLVOL,
739*4882a593Smuzhiyun 				     value->value.integer.value[0] |
740*4882a593Smuzhiyun 				     WM8776_HPZCEN |
741*4882a593Smuzhiyun 				     ((to_update & 2) ? 0 : WM8776_UPDATE));
742*4882a593Smuzhiyun 		if (to_update & 2)
743*4882a593Smuzhiyun 			wm8776_write(chip, WM8776_HPRVOL,
744*4882a593Smuzhiyun 				     value->value.integer.value[1] |
745*4882a593Smuzhiyun 				     WM8776_HPZCEN | WM8776_UPDATE);
746*4882a593Smuzhiyun 	}
747*4882a593Smuzhiyun 	mutex_unlock(&chip->mutex);
748*4882a593Smuzhiyun 	return to_update != 0;
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun 
wm8776_input_mux_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)751*4882a593Smuzhiyun static int wm8776_input_mux_get(struct snd_kcontrol *ctl,
752*4882a593Smuzhiyun 				struct snd_ctl_elem_value *value)
753*4882a593Smuzhiyun {
754*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
755*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
756*4882a593Smuzhiyun 	unsigned int mux_bit = ctl->private_value;
757*4882a593Smuzhiyun 
758*4882a593Smuzhiyun 	value->value.integer.value[0] =
759*4882a593Smuzhiyun 		!!(data->wm8776_regs[WM8776_ADCMUX] & mux_bit);
760*4882a593Smuzhiyun 	return 0;
761*4882a593Smuzhiyun }
762*4882a593Smuzhiyun 
wm8776_input_mux_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)763*4882a593Smuzhiyun static int wm8776_input_mux_put(struct snd_kcontrol *ctl,
764*4882a593Smuzhiyun 				struct snd_ctl_elem_value *value)
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
767*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
768*4882a593Smuzhiyun 	struct snd_kcontrol *other_ctl;
769*4882a593Smuzhiyun 	unsigned int mux_bit = ctl->private_value;
770*4882a593Smuzhiyun 	u16 reg;
771*4882a593Smuzhiyun 	int changed;
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	mutex_lock(&chip->mutex);
774*4882a593Smuzhiyun 	reg = data->wm8776_regs[WM8776_ADCMUX];
775*4882a593Smuzhiyun 	if (value->value.integer.value[0]) {
776*4882a593Smuzhiyun 		reg |= mux_bit;
777*4882a593Smuzhiyun 		/* line-in and mic-in are exclusive */
778*4882a593Smuzhiyun 		mux_bit ^= 3;
779*4882a593Smuzhiyun 		if (reg & mux_bit) {
780*4882a593Smuzhiyun 			reg &= ~mux_bit;
781*4882a593Smuzhiyun 			if (mux_bit == 1)
782*4882a593Smuzhiyun 				other_ctl = data->line_adcmux_control;
783*4882a593Smuzhiyun 			else
784*4882a593Smuzhiyun 				other_ctl = data->mic_adcmux_control;
785*4882a593Smuzhiyun 			snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
786*4882a593Smuzhiyun 				       &other_ctl->id);
787*4882a593Smuzhiyun 		}
788*4882a593Smuzhiyun 	} else
789*4882a593Smuzhiyun 		reg &= ~mux_bit;
790*4882a593Smuzhiyun 	changed = reg != data->wm8776_regs[WM8776_ADCMUX];
791*4882a593Smuzhiyun 	if (changed) {
792*4882a593Smuzhiyun 		oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
793*4882a593Smuzhiyun 				      reg & 1 ? GPIO_DS_INPUT_ROUTE : 0,
794*4882a593Smuzhiyun 				      GPIO_DS_INPUT_ROUTE);
795*4882a593Smuzhiyun 		wm8776_write(chip, WM8776_ADCMUX, reg);
796*4882a593Smuzhiyun 	}
797*4882a593Smuzhiyun 	mutex_unlock(&chip->mutex);
798*4882a593Smuzhiyun 	return changed;
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun 
wm8776_input_vol_info(struct snd_kcontrol * ctl,struct snd_ctl_elem_info * info)801*4882a593Smuzhiyun static int wm8776_input_vol_info(struct snd_kcontrol *ctl,
802*4882a593Smuzhiyun 				 struct snd_ctl_elem_info *info)
803*4882a593Smuzhiyun {
804*4882a593Smuzhiyun 	info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
805*4882a593Smuzhiyun 	info->count = 2;
806*4882a593Smuzhiyun 	info->value.integer.min = 0xa5;
807*4882a593Smuzhiyun 	info->value.integer.max = 0xff;
808*4882a593Smuzhiyun 	return 0;
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun 
wm8776_input_vol_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)811*4882a593Smuzhiyun static int wm8776_input_vol_get(struct snd_kcontrol *ctl,
812*4882a593Smuzhiyun 				struct snd_ctl_elem_value *value)
813*4882a593Smuzhiyun {
814*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
815*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun 	mutex_lock(&chip->mutex);
818*4882a593Smuzhiyun 	value->value.integer.value[0] =
819*4882a593Smuzhiyun 		data->wm8776_regs[WM8776_ADCLVOL] & WM8776_AGMASK;
820*4882a593Smuzhiyun 	value->value.integer.value[1] =
821*4882a593Smuzhiyun 		data->wm8776_regs[WM8776_ADCRVOL] & WM8776_AGMASK;
822*4882a593Smuzhiyun 	mutex_unlock(&chip->mutex);
823*4882a593Smuzhiyun 	return 0;
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun 
wm8776_input_vol_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)826*4882a593Smuzhiyun static int wm8776_input_vol_put(struct snd_kcontrol *ctl,
827*4882a593Smuzhiyun 				struct snd_ctl_elem_value *value)
828*4882a593Smuzhiyun {
829*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
830*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
831*4882a593Smuzhiyun 	int changed = 0;
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 	mutex_lock(&chip->mutex);
834*4882a593Smuzhiyun 	changed = (value->value.integer.value[0] !=
835*4882a593Smuzhiyun 		   (data->wm8776_regs[WM8776_ADCLVOL] & WM8776_AGMASK)) ||
836*4882a593Smuzhiyun 		  (value->value.integer.value[1] !=
837*4882a593Smuzhiyun 		   (data->wm8776_regs[WM8776_ADCRVOL] & WM8776_AGMASK));
838*4882a593Smuzhiyun 	wm8776_write_cached(chip, WM8776_ADCLVOL,
839*4882a593Smuzhiyun 			    value->value.integer.value[0] | WM8776_ZCA);
840*4882a593Smuzhiyun 	wm8776_write_cached(chip, WM8776_ADCRVOL,
841*4882a593Smuzhiyun 			    value->value.integer.value[1] | WM8776_ZCA);
842*4882a593Smuzhiyun 	mutex_unlock(&chip->mutex);
843*4882a593Smuzhiyun 	return changed;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun 
wm8776_level_control_info(struct snd_kcontrol * ctl,struct snd_ctl_elem_info * info)846*4882a593Smuzhiyun static int wm8776_level_control_info(struct snd_kcontrol *ctl,
847*4882a593Smuzhiyun 				     struct snd_ctl_elem_info *info)
848*4882a593Smuzhiyun {
849*4882a593Smuzhiyun 	static const char *const names[3] = {
850*4882a593Smuzhiyun 		"None", "Peak Limiter", "Automatic Level Control"
851*4882a593Smuzhiyun 	};
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun 	return snd_ctl_enum_info(info, 1, 3, names);
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun 
wm8776_level_control_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)856*4882a593Smuzhiyun static int wm8776_level_control_get(struct snd_kcontrol *ctl,
857*4882a593Smuzhiyun 				    struct snd_ctl_elem_value *value)
858*4882a593Smuzhiyun {
859*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
860*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
861*4882a593Smuzhiyun 
862*4882a593Smuzhiyun 	if (!(data->wm8776_regs[WM8776_ALCCTRL2] & WM8776_LCEN))
863*4882a593Smuzhiyun 		value->value.enumerated.item[0] = 0;
864*4882a593Smuzhiyun 	else if ((data->wm8776_regs[WM8776_ALCCTRL1] & WM8776_LCSEL_MASK) ==
865*4882a593Smuzhiyun 		 WM8776_LCSEL_LIMITER)
866*4882a593Smuzhiyun 		value->value.enumerated.item[0] = 1;
867*4882a593Smuzhiyun 	else
868*4882a593Smuzhiyun 		value->value.enumerated.item[0] = 2;
869*4882a593Smuzhiyun 	return 0;
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun 
activate_control(struct oxygen * chip,struct snd_kcontrol * ctl,unsigned int mode)872*4882a593Smuzhiyun static void activate_control(struct oxygen *chip,
873*4882a593Smuzhiyun 			     struct snd_kcontrol *ctl, unsigned int mode)
874*4882a593Smuzhiyun {
875*4882a593Smuzhiyun 	unsigned int access;
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	if (ctl->private_value & mode)
878*4882a593Smuzhiyun 		access = 0;
879*4882a593Smuzhiyun 	else
880*4882a593Smuzhiyun 		access = SNDRV_CTL_ELEM_ACCESS_INACTIVE;
881*4882a593Smuzhiyun 	if ((ctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_INACTIVE) != access) {
882*4882a593Smuzhiyun 		ctl->vd[0].access ^= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
883*4882a593Smuzhiyun 		snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &ctl->id);
884*4882a593Smuzhiyun 	}
885*4882a593Smuzhiyun }
886*4882a593Smuzhiyun 
wm8776_level_control_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)887*4882a593Smuzhiyun static int wm8776_level_control_put(struct snd_kcontrol *ctl,
888*4882a593Smuzhiyun 				    struct snd_ctl_elem_value *value)
889*4882a593Smuzhiyun {
890*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
891*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
892*4882a593Smuzhiyun 	unsigned int mode = 0, i;
893*4882a593Smuzhiyun 	u16 ctrl1, ctrl2;
894*4882a593Smuzhiyun 	int changed;
895*4882a593Smuzhiyun 
896*4882a593Smuzhiyun 	if (value->value.enumerated.item[0] >= 3)
897*4882a593Smuzhiyun 		return -EINVAL;
898*4882a593Smuzhiyun 	mutex_lock(&chip->mutex);
899*4882a593Smuzhiyun 	changed = value->value.enumerated.item[0] != ctl->private_value;
900*4882a593Smuzhiyun 	if (changed) {
901*4882a593Smuzhiyun 		ctl->private_value = value->value.enumerated.item[0];
902*4882a593Smuzhiyun 		ctrl1 = data->wm8776_regs[WM8776_ALCCTRL1];
903*4882a593Smuzhiyun 		ctrl2 = data->wm8776_regs[WM8776_ALCCTRL2];
904*4882a593Smuzhiyun 		switch (value->value.enumerated.item[0]) {
905*4882a593Smuzhiyun 		default:
906*4882a593Smuzhiyun 			wm8776_write_cached(chip, WM8776_ALCCTRL2,
907*4882a593Smuzhiyun 					    ctrl2 & ~WM8776_LCEN);
908*4882a593Smuzhiyun 			break;
909*4882a593Smuzhiyun 		case 1:
910*4882a593Smuzhiyun 			wm8776_write_cached(chip, WM8776_ALCCTRL1,
911*4882a593Smuzhiyun 					    (ctrl1 & ~WM8776_LCSEL_MASK) |
912*4882a593Smuzhiyun 					    WM8776_LCSEL_LIMITER);
913*4882a593Smuzhiyun 			wm8776_write_cached(chip, WM8776_ALCCTRL2,
914*4882a593Smuzhiyun 					    ctrl2 | WM8776_LCEN);
915*4882a593Smuzhiyun 			mode = LC_CONTROL_LIMITER;
916*4882a593Smuzhiyun 			break;
917*4882a593Smuzhiyun 		case 2:
918*4882a593Smuzhiyun 			wm8776_write_cached(chip, WM8776_ALCCTRL1,
919*4882a593Smuzhiyun 					    (ctrl1 & ~WM8776_LCSEL_MASK) |
920*4882a593Smuzhiyun 					    WM8776_LCSEL_ALC_STEREO);
921*4882a593Smuzhiyun 			wm8776_write_cached(chip, WM8776_ALCCTRL2,
922*4882a593Smuzhiyun 					    ctrl2 | WM8776_LCEN);
923*4882a593Smuzhiyun 			mode = LC_CONTROL_ALC;
924*4882a593Smuzhiyun 			break;
925*4882a593Smuzhiyun 		}
926*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(data->lc_controls); ++i)
927*4882a593Smuzhiyun 			activate_control(chip, data->lc_controls[i], mode);
928*4882a593Smuzhiyun 	}
929*4882a593Smuzhiyun 	mutex_unlock(&chip->mutex);
930*4882a593Smuzhiyun 	return changed;
931*4882a593Smuzhiyun }
932*4882a593Smuzhiyun 
hpf_info(struct snd_kcontrol * ctl,struct snd_ctl_elem_info * info)933*4882a593Smuzhiyun static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info)
934*4882a593Smuzhiyun {
935*4882a593Smuzhiyun 	static const char *const names[2] = {
936*4882a593Smuzhiyun 		"None", "High-pass Filter"
937*4882a593Smuzhiyun 	};
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun 	return snd_ctl_enum_info(info, 1, 2, names);
940*4882a593Smuzhiyun }
941*4882a593Smuzhiyun 
hpf_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)942*4882a593Smuzhiyun static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
943*4882a593Smuzhiyun {
944*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
945*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
946*4882a593Smuzhiyun 
947*4882a593Smuzhiyun 	value->value.enumerated.item[0] =
948*4882a593Smuzhiyun 		!(data->wm8776_regs[WM8776_ADCIFCTRL] & WM8776_ADCHPD);
949*4882a593Smuzhiyun 	return 0;
950*4882a593Smuzhiyun }
951*4882a593Smuzhiyun 
hpf_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)952*4882a593Smuzhiyun static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
953*4882a593Smuzhiyun {
954*4882a593Smuzhiyun 	struct oxygen *chip = ctl->private_data;
955*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
956*4882a593Smuzhiyun 	unsigned int reg;
957*4882a593Smuzhiyun 	int changed;
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun 	mutex_lock(&chip->mutex);
960*4882a593Smuzhiyun 	reg = data->wm8776_regs[WM8776_ADCIFCTRL] & ~WM8776_ADCHPD;
961*4882a593Smuzhiyun 	if (!value->value.enumerated.item[0])
962*4882a593Smuzhiyun 		reg |= WM8776_ADCHPD;
963*4882a593Smuzhiyun 	changed = reg != data->wm8776_regs[WM8776_ADCIFCTRL];
964*4882a593Smuzhiyun 	if (changed)
965*4882a593Smuzhiyun 		wm8776_write(chip, WM8776_ADCIFCTRL, reg);
966*4882a593Smuzhiyun 	mutex_unlock(&chip->mutex);
967*4882a593Smuzhiyun 	return changed;
968*4882a593Smuzhiyun }
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun #define WM8776_BIT_SWITCH(xname, reg, bit, invert, flags) { \
971*4882a593Smuzhiyun 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
972*4882a593Smuzhiyun 	.name = xname, \
973*4882a593Smuzhiyun 	.info = snd_ctl_boolean_mono_info, \
974*4882a593Smuzhiyun 	.get = wm8776_bit_switch_get, \
975*4882a593Smuzhiyun 	.put = wm8776_bit_switch_put, \
976*4882a593Smuzhiyun 	.private_value = ((reg) << 16) | (bit) | ((invert) << 24) | (flags), \
977*4882a593Smuzhiyun }
978*4882a593Smuzhiyun #define _WM8776_FIELD_CTL(xname, reg, shift, initval, min, max, mask, flags) \
979*4882a593Smuzhiyun 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
980*4882a593Smuzhiyun 	.name = xname, \
981*4882a593Smuzhiyun 	.private_value = (initval) | ((min) << 8) | ((max) << 12) | \
982*4882a593Smuzhiyun 	((mask) << 16) | ((shift) << 20) | ((reg) << 24) | (flags)
983*4882a593Smuzhiyun #define WM8776_FIELD_CTL_ENUM(xname, reg, shift, init, min, max, mask, flags) {\
984*4882a593Smuzhiyun 	_WM8776_FIELD_CTL(xname " Capture Enum", \
985*4882a593Smuzhiyun 			  reg, shift, init, min, max, mask, flags), \
986*4882a593Smuzhiyun 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
987*4882a593Smuzhiyun 		  SNDRV_CTL_ELEM_ACCESS_INACTIVE, \
988*4882a593Smuzhiyun 	.info = wm8776_field_enum_info, \
989*4882a593Smuzhiyun 	.get = wm8776_field_enum_get, \
990*4882a593Smuzhiyun 	.put = wm8776_field_enum_put, \
991*4882a593Smuzhiyun }
992*4882a593Smuzhiyun #define WM8776_FIELD_CTL_VOLUME(a, b, c, d, e, f, g, h, tlv_p) { \
993*4882a593Smuzhiyun 	_WM8776_FIELD_CTL(a " Capture Volume", b, c, d, e, f, g, h), \
994*4882a593Smuzhiyun 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
995*4882a593Smuzhiyun 		  SNDRV_CTL_ELEM_ACCESS_INACTIVE | \
996*4882a593Smuzhiyun 		  SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
997*4882a593Smuzhiyun 	.info = wm8776_field_volume_info, \
998*4882a593Smuzhiyun 	.get = wm8776_field_volume_get, \
999*4882a593Smuzhiyun 	.put = wm8776_field_volume_put, \
1000*4882a593Smuzhiyun 	.tlv = { .p = tlv_p }, \
1001*4882a593Smuzhiyun }
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(wm87x6_dac_db_scale, -6000, 50, 0);
1004*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(wm8776_adc_db_scale, -2100, 50, 0);
1005*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(wm8776_hp_db_scale, -6000, 100, 0);
1006*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(wm8776_lct_db_scale, -1600, 100, 0);
1007*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(wm8776_maxgain_db_scale, 0, 400, 0);
1008*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(wm8776_ngth_db_scale, -7800, 600, 0);
1009*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_lim_db_scale, -1200, 100, 0);
1010*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_alc_db_scale, -2100, 400, 0);
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun static const struct snd_kcontrol_new ds_controls[] = {
1013*4882a593Smuzhiyun 	{
1014*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1015*4882a593Smuzhiyun 		.name = "Headphone Playback Volume",
1016*4882a593Smuzhiyun 		.info = wm8776_hp_vol_info,
1017*4882a593Smuzhiyun 		.get = wm8776_hp_vol_get,
1018*4882a593Smuzhiyun 		.put = wm8776_hp_vol_put,
1019*4882a593Smuzhiyun 		.tlv = { .p = wm8776_hp_db_scale },
1020*4882a593Smuzhiyun 	},
1021*4882a593Smuzhiyun 	WM8776_BIT_SWITCH("Headphone Playback Switch",
1022*4882a593Smuzhiyun 			  WM8776_PWRDOWN, WM8776_HPPD, 1, 0),
1023*4882a593Smuzhiyun 	{
1024*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1025*4882a593Smuzhiyun 		.name = "Input Capture Volume",
1026*4882a593Smuzhiyun 		.info = wm8776_input_vol_info,
1027*4882a593Smuzhiyun 		.get = wm8776_input_vol_get,
1028*4882a593Smuzhiyun 		.put = wm8776_input_vol_put,
1029*4882a593Smuzhiyun 		.tlv = { .p = wm8776_adc_db_scale },
1030*4882a593Smuzhiyun 	},
1031*4882a593Smuzhiyun 	{
1032*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1033*4882a593Smuzhiyun 		.name = "Line Capture Switch",
1034*4882a593Smuzhiyun 		.info = snd_ctl_boolean_mono_info,
1035*4882a593Smuzhiyun 		.get = wm8776_input_mux_get,
1036*4882a593Smuzhiyun 		.put = wm8776_input_mux_put,
1037*4882a593Smuzhiyun 		.private_value = 1 << 0,
1038*4882a593Smuzhiyun 	},
1039*4882a593Smuzhiyun 	{
1040*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1041*4882a593Smuzhiyun 		.name = "Mic Capture Switch",
1042*4882a593Smuzhiyun 		.info = snd_ctl_boolean_mono_info,
1043*4882a593Smuzhiyun 		.get = wm8776_input_mux_get,
1044*4882a593Smuzhiyun 		.put = wm8776_input_mux_put,
1045*4882a593Smuzhiyun 		.private_value = 1 << 1,
1046*4882a593Smuzhiyun 	},
1047*4882a593Smuzhiyun 	WM8776_BIT_SWITCH("Front Mic Capture Switch",
1048*4882a593Smuzhiyun 			  WM8776_ADCMUX, 1 << 2, 0, 0),
1049*4882a593Smuzhiyun 	WM8776_BIT_SWITCH("Aux Capture Switch",
1050*4882a593Smuzhiyun 			  WM8776_ADCMUX, 1 << 3, 0, 0),
1051*4882a593Smuzhiyun 	{
1052*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1053*4882a593Smuzhiyun 		.name = "ADC Filter Capture Enum",
1054*4882a593Smuzhiyun 		.info = hpf_info,
1055*4882a593Smuzhiyun 		.get = hpf_get,
1056*4882a593Smuzhiyun 		.put = hpf_put,
1057*4882a593Smuzhiyun 	},
1058*4882a593Smuzhiyun 	{
1059*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1060*4882a593Smuzhiyun 		.name = "Level Control Capture Enum",
1061*4882a593Smuzhiyun 		.info = wm8776_level_control_info,
1062*4882a593Smuzhiyun 		.get = wm8776_level_control_get,
1063*4882a593Smuzhiyun 		.put = wm8776_level_control_put,
1064*4882a593Smuzhiyun 		.private_value = 0,
1065*4882a593Smuzhiyun 	},
1066*4882a593Smuzhiyun };
1067*4882a593Smuzhiyun static const struct snd_kcontrol_new hdav_slim_controls[] = {
1068*4882a593Smuzhiyun 	{
1069*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1070*4882a593Smuzhiyun 		.name = "HDMI Playback Switch",
1071*4882a593Smuzhiyun 		.info = snd_ctl_boolean_mono_info,
1072*4882a593Smuzhiyun 		.get = xonar_gpio_bit_switch_get,
1073*4882a593Smuzhiyun 		.put = xonar_gpio_bit_switch_put,
1074*4882a593Smuzhiyun 		.private_value = GPIO_SLIM_HDMI_DISABLE | XONAR_GPIO_BIT_INVERT,
1075*4882a593Smuzhiyun 	},
1076*4882a593Smuzhiyun 	{
1077*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1078*4882a593Smuzhiyun 		.name = "Headphone Playback Volume",
1079*4882a593Smuzhiyun 		.info = wm8776_hp_vol_info,
1080*4882a593Smuzhiyun 		.get = wm8776_hp_vol_get,
1081*4882a593Smuzhiyun 		.put = wm8776_hp_vol_put,
1082*4882a593Smuzhiyun 		.tlv = { .p = wm8776_hp_db_scale },
1083*4882a593Smuzhiyun 	},
1084*4882a593Smuzhiyun 	WM8776_BIT_SWITCH("Headphone Playback Switch",
1085*4882a593Smuzhiyun 			  WM8776_PWRDOWN, WM8776_HPPD, 1, 0),
1086*4882a593Smuzhiyun 	{
1087*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1088*4882a593Smuzhiyun 		.name = "Input Capture Volume",
1089*4882a593Smuzhiyun 		.info = wm8776_input_vol_info,
1090*4882a593Smuzhiyun 		.get = wm8776_input_vol_get,
1091*4882a593Smuzhiyun 		.put = wm8776_input_vol_put,
1092*4882a593Smuzhiyun 		.tlv = { .p = wm8776_adc_db_scale },
1093*4882a593Smuzhiyun 	},
1094*4882a593Smuzhiyun 	WM8776_BIT_SWITCH("Mic Capture Switch",
1095*4882a593Smuzhiyun 			  WM8776_ADCMUX, 1 << 0, 0, 0),
1096*4882a593Smuzhiyun 	WM8776_BIT_SWITCH("Aux Capture Switch",
1097*4882a593Smuzhiyun 			  WM8776_ADCMUX, 1 << 1, 0, 0),
1098*4882a593Smuzhiyun 	{
1099*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1100*4882a593Smuzhiyun 		.name = "ADC Filter Capture Enum",
1101*4882a593Smuzhiyun 		.info = hpf_info,
1102*4882a593Smuzhiyun 		.get = hpf_get,
1103*4882a593Smuzhiyun 		.put = hpf_put,
1104*4882a593Smuzhiyun 	},
1105*4882a593Smuzhiyun 	{
1106*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1107*4882a593Smuzhiyun 		.name = "Level Control Capture Enum",
1108*4882a593Smuzhiyun 		.info = wm8776_level_control_info,
1109*4882a593Smuzhiyun 		.get = wm8776_level_control_get,
1110*4882a593Smuzhiyun 		.put = wm8776_level_control_put,
1111*4882a593Smuzhiyun 		.private_value = 0,
1112*4882a593Smuzhiyun 	},
1113*4882a593Smuzhiyun };
1114*4882a593Smuzhiyun static const struct snd_kcontrol_new lc_controls[] = {
1115*4882a593Smuzhiyun 	WM8776_FIELD_CTL_VOLUME("Limiter Threshold",
1116*4882a593Smuzhiyun 				WM8776_ALCCTRL1, 0, 11, 0, 15, 0xf,
1117*4882a593Smuzhiyun 				LC_CONTROL_LIMITER, wm8776_lct_db_scale),
1118*4882a593Smuzhiyun 	WM8776_FIELD_CTL_ENUM("Limiter Attack Time",
1119*4882a593Smuzhiyun 			      WM8776_ALCCTRL3, 0, 2, 0, 10, 0xf,
1120*4882a593Smuzhiyun 			      LC_CONTROL_LIMITER),
1121*4882a593Smuzhiyun 	WM8776_FIELD_CTL_ENUM("Limiter Decay Time",
1122*4882a593Smuzhiyun 			      WM8776_ALCCTRL3, 4, 3, 0, 10, 0xf,
1123*4882a593Smuzhiyun 			      LC_CONTROL_LIMITER),
1124*4882a593Smuzhiyun 	WM8776_FIELD_CTL_ENUM("Limiter Transient Window",
1125*4882a593Smuzhiyun 			      WM8776_LIMITER, 4, 2, 0, 7, 0x7,
1126*4882a593Smuzhiyun 			      LC_CONTROL_LIMITER),
1127*4882a593Smuzhiyun 	WM8776_FIELD_CTL_VOLUME("Limiter Maximum Attenuation",
1128*4882a593Smuzhiyun 				WM8776_LIMITER, 0, 6, 3, 12, 0xf,
1129*4882a593Smuzhiyun 				LC_CONTROL_LIMITER,
1130*4882a593Smuzhiyun 				wm8776_maxatten_lim_db_scale),
1131*4882a593Smuzhiyun 	WM8776_FIELD_CTL_VOLUME("ALC Target Level",
1132*4882a593Smuzhiyun 				WM8776_ALCCTRL1, 0, 11, 0, 15, 0xf,
1133*4882a593Smuzhiyun 				LC_CONTROL_ALC, wm8776_lct_db_scale),
1134*4882a593Smuzhiyun 	WM8776_FIELD_CTL_ENUM("ALC Attack Time",
1135*4882a593Smuzhiyun 			      WM8776_ALCCTRL3, 0, 2, 0, 10, 0xf,
1136*4882a593Smuzhiyun 			      LC_CONTROL_ALC),
1137*4882a593Smuzhiyun 	WM8776_FIELD_CTL_ENUM("ALC Decay Time",
1138*4882a593Smuzhiyun 			      WM8776_ALCCTRL3, 4, 3, 0, 10, 0xf,
1139*4882a593Smuzhiyun 			      LC_CONTROL_ALC),
1140*4882a593Smuzhiyun 	WM8776_FIELD_CTL_VOLUME("ALC Maximum Gain",
1141*4882a593Smuzhiyun 				WM8776_ALCCTRL1, 4, 7, 1, 7, 0x7,
1142*4882a593Smuzhiyun 				LC_CONTROL_ALC, wm8776_maxgain_db_scale),
1143*4882a593Smuzhiyun 	WM8776_FIELD_CTL_VOLUME("ALC Maximum Attenuation",
1144*4882a593Smuzhiyun 				WM8776_LIMITER, 0, 10, 10, 15, 0xf,
1145*4882a593Smuzhiyun 				LC_CONTROL_ALC, wm8776_maxatten_alc_db_scale),
1146*4882a593Smuzhiyun 	WM8776_FIELD_CTL_ENUM("ALC Hold Time",
1147*4882a593Smuzhiyun 			      WM8776_ALCCTRL2, 0, 0, 0, 15, 0xf,
1148*4882a593Smuzhiyun 			      LC_CONTROL_ALC),
1149*4882a593Smuzhiyun 	WM8776_BIT_SWITCH("Noise Gate Capture Switch",
1150*4882a593Smuzhiyun 			  WM8776_NOISEGATE, WM8776_NGAT, 0,
1151*4882a593Smuzhiyun 			  LC_CONTROL_ALC),
1152*4882a593Smuzhiyun 	WM8776_FIELD_CTL_VOLUME("Noise Gate Threshold",
1153*4882a593Smuzhiyun 				WM8776_NOISEGATE, 2, 0, 0, 7, 0x7,
1154*4882a593Smuzhiyun 				LC_CONTROL_ALC, wm8776_ngth_db_scale),
1155*4882a593Smuzhiyun };
1156*4882a593Smuzhiyun 
add_lc_controls(struct oxygen * chip)1157*4882a593Smuzhiyun static int add_lc_controls(struct oxygen *chip)
1158*4882a593Smuzhiyun {
1159*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
1160*4882a593Smuzhiyun 	unsigned int i;
1161*4882a593Smuzhiyun 	struct snd_kcontrol *ctl;
1162*4882a593Smuzhiyun 	int err;
1163*4882a593Smuzhiyun 
1164*4882a593Smuzhiyun 	BUILD_BUG_ON(ARRAY_SIZE(lc_controls) != ARRAY_SIZE(data->lc_controls));
1165*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(lc_controls); ++i) {
1166*4882a593Smuzhiyun 		ctl = snd_ctl_new1(&lc_controls[i], chip);
1167*4882a593Smuzhiyun 		if (!ctl)
1168*4882a593Smuzhiyun 			return -ENOMEM;
1169*4882a593Smuzhiyun 		err = snd_ctl_add(chip->card, ctl);
1170*4882a593Smuzhiyun 		if (err < 0)
1171*4882a593Smuzhiyun 			return err;
1172*4882a593Smuzhiyun 		data->lc_controls[i] = ctl;
1173*4882a593Smuzhiyun 	}
1174*4882a593Smuzhiyun 	return 0;
1175*4882a593Smuzhiyun }
1176*4882a593Smuzhiyun 
xonar_ds_mixer_init(struct oxygen * chip)1177*4882a593Smuzhiyun static int xonar_ds_mixer_init(struct oxygen *chip)
1178*4882a593Smuzhiyun {
1179*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
1180*4882a593Smuzhiyun 	unsigned int i;
1181*4882a593Smuzhiyun 	struct snd_kcontrol *ctl;
1182*4882a593Smuzhiyun 	int err;
1183*4882a593Smuzhiyun 
1184*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(ds_controls); ++i) {
1185*4882a593Smuzhiyun 		ctl = snd_ctl_new1(&ds_controls[i], chip);
1186*4882a593Smuzhiyun 		if (!ctl)
1187*4882a593Smuzhiyun 			return -ENOMEM;
1188*4882a593Smuzhiyun 		err = snd_ctl_add(chip->card, ctl);
1189*4882a593Smuzhiyun 		if (err < 0)
1190*4882a593Smuzhiyun 			return err;
1191*4882a593Smuzhiyun 		if (!strcmp(ctl->id.name, "Line Capture Switch"))
1192*4882a593Smuzhiyun 			data->line_adcmux_control = ctl;
1193*4882a593Smuzhiyun 		else if (!strcmp(ctl->id.name, "Mic Capture Switch"))
1194*4882a593Smuzhiyun 			data->mic_adcmux_control = ctl;
1195*4882a593Smuzhiyun 	}
1196*4882a593Smuzhiyun 	if (!data->line_adcmux_control || !data->mic_adcmux_control)
1197*4882a593Smuzhiyun 		return -ENXIO;
1198*4882a593Smuzhiyun 
1199*4882a593Smuzhiyun 	return add_lc_controls(chip);
1200*4882a593Smuzhiyun }
1201*4882a593Smuzhiyun 
xonar_hdav_slim_mixer_init(struct oxygen * chip)1202*4882a593Smuzhiyun static int xonar_hdav_slim_mixer_init(struct oxygen *chip)
1203*4882a593Smuzhiyun {
1204*4882a593Smuzhiyun 	unsigned int i;
1205*4882a593Smuzhiyun 	struct snd_kcontrol *ctl;
1206*4882a593Smuzhiyun 	int err;
1207*4882a593Smuzhiyun 
1208*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(hdav_slim_controls); ++i) {
1209*4882a593Smuzhiyun 		ctl = snd_ctl_new1(&hdav_slim_controls[i], chip);
1210*4882a593Smuzhiyun 		if (!ctl)
1211*4882a593Smuzhiyun 			return -ENOMEM;
1212*4882a593Smuzhiyun 		err = snd_ctl_add(chip->card, ctl);
1213*4882a593Smuzhiyun 		if (err < 0)
1214*4882a593Smuzhiyun 			return err;
1215*4882a593Smuzhiyun 	}
1216*4882a593Smuzhiyun 
1217*4882a593Smuzhiyun 	return add_lc_controls(chip);
1218*4882a593Smuzhiyun }
1219*4882a593Smuzhiyun 
dump_wm8776_registers(struct oxygen * chip,struct snd_info_buffer * buffer)1220*4882a593Smuzhiyun static void dump_wm8776_registers(struct oxygen *chip,
1221*4882a593Smuzhiyun 				  struct snd_info_buffer *buffer)
1222*4882a593Smuzhiyun {
1223*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
1224*4882a593Smuzhiyun 	unsigned int i;
1225*4882a593Smuzhiyun 
1226*4882a593Smuzhiyun 	snd_iprintf(buffer, "\nWM8776:\n00:");
1227*4882a593Smuzhiyun 	for (i = 0; i < 0x10; ++i)
1228*4882a593Smuzhiyun 		snd_iprintf(buffer, " %03x", data->wm8776_regs[i]);
1229*4882a593Smuzhiyun 	snd_iprintf(buffer, "\n10:");
1230*4882a593Smuzhiyun 	for (i = 0x10; i < 0x17; ++i)
1231*4882a593Smuzhiyun 		snd_iprintf(buffer, " %03x", data->wm8776_regs[i]);
1232*4882a593Smuzhiyun 	snd_iprintf(buffer, "\n");
1233*4882a593Smuzhiyun }
1234*4882a593Smuzhiyun 
dump_wm87x6_registers(struct oxygen * chip,struct snd_info_buffer * buffer)1235*4882a593Smuzhiyun static void dump_wm87x6_registers(struct oxygen *chip,
1236*4882a593Smuzhiyun 				  struct snd_info_buffer *buffer)
1237*4882a593Smuzhiyun {
1238*4882a593Smuzhiyun 	struct xonar_wm87x6 *data = chip->model_data;
1239*4882a593Smuzhiyun 	unsigned int i;
1240*4882a593Smuzhiyun 
1241*4882a593Smuzhiyun 	dump_wm8776_registers(chip, buffer);
1242*4882a593Smuzhiyun 	snd_iprintf(buffer, "\nWM8766:\n00:");
1243*4882a593Smuzhiyun 	for (i = 0; i < 0x10; ++i)
1244*4882a593Smuzhiyun 		snd_iprintf(buffer, " %03x", data->wm8766_regs[i]);
1245*4882a593Smuzhiyun 	snd_iprintf(buffer, "\n");
1246*4882a593Smuzhiyun }
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun static const struct oxygen_model model_xonar_ds = {
1249*4882a593Smuzhiyun 	.longname = "Asus Virtuoso 66",
1250*4882a593Smuzhiyun 	.chip = "AV200",
1251*4882a593Smuzhiyun 	.init = xonar_ds_init,
1252*4882a593Smuzhiyun 	.mixer_init = xonar_ds_mixer_init,
1253*4882a593Smuzhiyun 	.cleanup = xonar_ds_cleanup,
1254*4882a593Smuzhiyun 	.suspend = xonar_ds_suspend,
1255*4882a593Smuzhiyun 	.resume = xonar_ds_resume,
1256*4882a593Smuzhiyun 	.pcm_hardware_filter = wm8776_adc_hardware_filter,
1257*4882a593Smuzhiyun 	.set_dac_params = set_wm87x6_dac_params,
1258*4882a593Smuzhiyun 	.set_adc_params = set_wm8776_adc_params,
1259*4882a593Smuzhiyun 	.update_dac_volume = update_wm87x6_volume,
1260*4882a593Smuzhiyun 	.update_dac_mute = update_wm87x6_mute,
1261*4882a593Smuzhiyun 	.update_center_lfe_mix = update_wm8766_center_lfe_mix,
1262*4882a593Smuzhiyun 	.gpio_changed = xonar_ds_gpio_changed,
1263*4882a593Smuzhiyun 	.dump_registers = dump_wm87x6_registers,
1264*4882a593Smuzhiyun 	.dac_tlv = wm87x6_dac_db_scale,
1265*4882a593Smuzhiyun 	.model_data_size = sizeof(struct xonar_wm87x6),
1266*4882a593Smuzhiyun 	.device_config = PLAYBACK_0_TO_I2S |
1267*4882a593Smuzhiyun 			 PLAYBACK_1_TO_SPDIF |
1268*4882a593Smuzhiyun 			 CAPTURE_0_FROM_I2S_1 |
1269*4882a593Smuzhiyun 			 CAPTURE_1_FROM_SPDIF,
1270*4882a593Smuzhiyun 	.dac_channels_pcm = 8,
1271*4882a593Smuzhiyun 	.dac_channels_mixer = 8,
1272*4882a593Smuzhiyun 	.dac_volume_min = 255 - 2*60,
1273*4882a593Smuzhiyun 	.dac_volume_max = 255,
1274*4882a593Smuzhiyun 	.function_flags = OXYGEN_FUNCTION_SPI,
1275*4882a593Smuzhiyun 	.dac_mclks = OXYGEN_MCLKS(256, 256, 128),
1276*4882a593Smuzhiyun 	.adc_mclks = OXYGEN_MCLKS(256, 256, 128),
1277*4882a593Smuzhiyun 	.dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
1278*4882a593Smuzhiyun 	.adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
1279*4882a593Smuzhiyun };
1280*4882a593Smuzhiyun 
1281*4882a593Smuzhiyun static const struct oxygen_model model_xonar_hdav_slim = {
1282*4882a593Smuzhiyun 	.shortname = "Xonar HDAV1.3 Slim",
1283*4882a593Smuzhiyun 	.longname = "Asus Virtuoso 200",
1284*4882a593Smuzhiyun 	.chip = "AV200",
1285*4882a593Smuzhiyun 	.init = xonar_hdav_slim_init,
1286*4882a593Smuzhiyun 	.mixer_init = xonar_hdav_slim_mixer_init,
1287*4882a593Smuzhiyun 	.cleanup = xonar_hdav_slim_cleanup,
1288*4882a593Smuzhiyun 	.suspend = xonar_hdav_slim_suspend,
1289*4882a593Smuzhiyun 	.resume = xonar_hdav_slim_resume,
1290*4882a593Smuzhiyun 	.pcm_hardware_filter = xonar_hdav_slim_hardware_filter,
1291*4882a593Smuzhiyun 	.set_dac_params = set_hdav_slim_dac_params,
1292*4882a593Smuzhiyun 	.set_adc_params = set_wm8776_adc_params,
1293*4882a593Smuzhiyun 	.update_dac_volume = update_wm8776_volume,
1294*4882a593Smuzhiyun 	.update_dac_mute = update_wm8776_mute,
1295*4882a593Smuzhiyun 	.uart_input = xonar_hdmi_uart_input,
1296*4882a593Smuzhiyun 	.dump_registers = dump_wm8776_registers,
1297*4882a593Smuzhiyun 	.dac_tlv = wm87x6_dac_db_scale,
1298*4882a593Smuzhiyun 	.model_data_size = sizeof(struct xonar_wm87x6),
1299*4882a593Smuzhiyun 	.device_config = PLAYBACK_0_TO_I2S |
1300*4882a593Smuzhiyun 			 PLAYBACK_1_TO_SPDIF |
1301*4882a593Smuzhiyun 			 CAPTURE_0_FROM_I2S_1 |
1302*4882a593Smuzhiyun 			 CAPTURE_1_FROM_SPDIF,
1303*4882a593Smuzhiyun 	.dac_channels_pcm = 8,
1304*4882a593Smuzhiyun 	.dac_channels_mixer = 2,
1305*4882a593Smuzhiyun 	.dac_volume_min = 255 - 2*60,
1306*4882a593Smuzhiyun 	.dac_volume_max = 255,
1307*4882a593Smuzhiyun 	.function_flags = OXYGEN_FUNCTION_2WIRE,
1308*4882a593Smuzhiyun 	.dac_mclks = OXYGEN_MCLKS(256, 256, 128),
1309*4882a593Smuzhiyun 	.adc_mclks = OXYGEN_MCLKS(256, 256, 128),
1310*4882a593Smuzhiyun 	.dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
1311*4882a593Smuzhiyun 	.adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
1312*4882a593Smuzhiyun };
1313*4882a593Smuzhiyun 
get_xonar_wm87x6_model(struct oxygen * chip,const struct pci_device_id * id)1314*4882a593Smuzhiyun int get_xonar_wm87x6_model(struct oxygen *chip,
1315*4882a593Smuzhiyun 			   const struct pci_device_id *id)
1316*4882a593Smuzhiyun {
1317*4882a593Smuzhiyun 	switch (id->subdevice) {
1318*4882a593Smuzhiyun 	case 0x838e:
1319*4882a593Smuzhiyun 		chip->model = model_xonar_ds;
1320*4882a593Smuzhiyun 		chip->model.shortname = "Xonar DS";
1321*4882a593Smuzhiyun 		break;
1322*4882a593Smuzhiyun 	case 0x8522:
1323*4882a593Smuzhiyun 		chip->model = model_xonar_ds;
1324*4882a593Smuzhiyun 		chip->model.shortname = "Xonar DSX";
1325*4882a593Smuzhiyun 		break;
1326*4882a593Smuzhiyun 	case 0x835e:
1327*4882a593Smuzhiyun 		chip->model = model_xonar_hdav_slim;
1328*4882a593Smuzhiyun 		break;
1329*4882a593Smuzhiyun 	default:
1330*4882a593Smuzhiyun 		return -EINVAL;
1331*4882a593Smuzhiyun 	}
1332*4882a593Smuzhiyun 	return 0;
1333*4882a593Smuzhiyun }
1334