1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef WM8766_H_INCLUDED 3*4882a593Smuzhiyun #define WM8766_H_INCLUDED 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define WM8766_LDA1 0x00 6*4882a593Smuzhiyun #define WM8766_RDA1 0x01 7*4882a593Smuzhiyun #define WM8766_DAC_CTRL 0x02 8*4882a593Smuzhiyun #define WM8766_INT_CTRL 0x03 9*4882a593Smuzhiyun #define WM8766_LDA2 0x04 10*4882a593Smuzhiyun #define WM8766_RDA2 0x05 11*4882a593Smuzhiyun #define WM8766_LDA3 0x06 12*4882a593Smuzhiyun #define WM8766_RDA3 0x07 13*4882a593Smuzhiyun #define WM8766_MASTDA 0x08 14*4882a593Smuzhiyun #define WM8766_DAC_CTRL2 0x09 15*4882a593Smuzhiyun #define WM8766_DAC_CTRL3 0x0a 16*4882a593Smuzhiyun #define WM8766_MUTE1 0x0c 17*4882a593Smuzhiyun #define WM8766_MUTE2 0x0f 18*4882a593Smuzhiyun #define WM8766_RESET 0x1f 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* LDAx/RDAx/MASTDA */ 21*4882a593Smuzhiyun #define WM8766_ATT_MASK 0x0ff 22*4882a593Smuzhiyun #define WM8766_UPDATE 0x100 23*4882a593Smuzhiyun /* DAC_CTRL */ 24*4882a593Smuzhiyun #define WM8766_MUTEALL 0x001 25*4882a593Smuzhiyun #define WM8766_DEEMPALL 0x002 26*4882a593Smuzhiyun #define WM8766_PWDN 0x004 27*4882a593Smuzhiyun #define WM8766_ATC 0x008 28*4882a593Smuzhiyun #define WM8766_IZD 0x010 29*4882a593Smuzhiyun #define WM8766_PL_LEFT_MASK 0x060 30*4882a593Smuzhiyun #define WM8766_PL_LEFT_MUTE 0x000 31*4882a593Smuzhiyun #define WM8766_PL_LEFT_LEFT 0x020 32*4882a593Smuzhiyun #define WM8766_PL_LEFT_RIGHT 0x040 33*4882a593Smuzhiyun #define WM8766_PL_LEFT_LRMIX 0x060 34*4882a593Smuzhiyun #define WM8766_PL_RIGHT_MASK 0x180 35*4882a593Smuzhiyun #define WM8766_PL_RIGHT_MUTE 0x000 36*4882a593Smuzhiyun #define WM8766_PL_RIGHT_LEFT 0x080 37*4882a593Smuzhiyun #define WM8766_PL_RIGHT_RIGHT 0x100 38*4882a593Smuzhiyun #define WM8766_PL_RIGHT_LRMIX 0x180 39*4882a593Smuzhiyun /* INT_CTRL */ 40*4882a593Smuzhiyun #define WM8766_FMT_MASK 0x003 41*4882a593Smuzhiyun #define WM8766_FMT_RJUST 0x000 42*4882a593Smuzhiyun #define WM8766_FMT_LJUST 0x001 43*4882a593Smuzhiyun #define WM8766_FMT_I2S 0x002 44*4882a593Smuzhiyun #define WM8766_FMT_DSP 0x003 45*4882a593Smuzhiyun #define WM8766_LRP 0x004 46*4882a593Smuzhiyun #define WM8766_BCP 0x008 47*4882a593Smuzhiyun #define WM8766_IWL_MASK 0x030 48*4882a593Smuzhiyun #define WM8766_IWL_16 0x000 49*4882a593Smuzhiyun #define WM8766_IWL_20 0x010 50*4882a593Smuzhiyun #define WM8766_IWL_24 0x020 51*4882a593Smuzhiyun #define WM8766_IWL_32 0x030 52*4882a593Smuzhiyun #define WM8766_PHASE_MASK 0x1c0 53*4882a593Smuzhiyun /* DAC_CTRL2 */ 54*4882a593Smuzhiyun #define WM8766_ZCD 0x001 55*4882a593Smuzhiyun #define WM8766_DZFM_MASK 0x006 56*4882a593Smuzhiyun #define WM8766_DMUTE_MASK 0x038 57*4882a593Smuzhiyun #define WM8766_DEEMP_MASK 0x1c0 58*4882a593Smuzhiyun /* DAC_CTRL3 */ 59*4882a593Smuzhiyun #define WM8766_DACPD_MASK 0x00e 60*4882a593Smuzhiyun #define WM8766_PWRDNALL 0x010 61*4882a593Smuzhiyun #define WM8766_MS 0x020 62*4882a593Smuzhiyun #define WM8766_RATE_MASK 0x1c0 63*4882a593Smuzhiyun #define WM8766_RATE_128 0x000 64*4882a593Smuzhiyun #define WM8766_RATE_192 0x040 65*4882a593Smuzhiyun #define WM8766_RATE_256 0x080 66*4882a593Smuzhiyun #define WM8766_RATE_384 0x0c0 67*4882a593Smuzhiyun #define WM8766_RATE_512 0x100 68*4882a593Smuzhiyun #define WM8766_RATE_768 0x140 69*4882a593Smuzhiyun /* MUTE1 */ 70*4882a593Smuzhiyun #define WM8766_MPD1 0x040 71*4882a593Smuzhiyun /* MUTE2 */ 72*4882a593Smuzhiyun #define WM8766_MPD2 0x020 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif 75