1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* register 1 */ 3*4882a593Smuzhiyun #define CS4398_REV_MASK 0x07 4*4882a593Smuzhiyun #define CS4398_PART_MASK 0xf8 5*4882a593Smuzhiyun #define CS4398_PART_CS4398 0x70 6*4882a593Smuzhiyun /* register 2 */ 7*4882a593Smuzhiyun #define CS4398_FM_MASK 0x03 8*4882a593Smuzhiyun #define CS4398_FM_SINGLE 0x00 9*4882a593Smuzhiyun #define CS4398_FM_DOUBLE 0x01 10*4882a593Smuzhiyun #define CS4398_FM_QUAD 0x02 11*4882a593Smuzhiyun #define CS4398_FM_DSD 0x03 12*4882a593Smuzhiyun #define CS4398_DEM_MASK 0x0c 13*4882a593Smuzhiyun #define CS4398_DEM_NONE 0x00 14*4882a593Smuzhiyun #define CS4398_DEM_44100 0x04 15*4882a593Smuzhiyun #define CS4398_DEM_48000 0x08 16*4882a593Smuzhiyun #define CS4398_DEM_32000 0x0c 17*4882a593Smuzhiyun #define CS4398_DIF_MASK 0x70 18*4882a593Smuzhiyun #define CS4398_DIF_LJUST 0x00 19*4882a593Smuzhiyun #define CS4398_DIF_I2S 0x10 20*4882a593Smuzhiyun #define CS4398_DIF_RJUST_16 0x20 21*4882a593Smuzhiyun #define CS4398_DIF_RJUST_24 0x30 22*4882a593Smuzhiyun #define CS4398_DIF_RJUST_20 0x40 23*4882a593Smuzhiyun #define CS4398_DIF_RJUST_18 0x50 24*4882a593Smuzhiyun #define CS4398_DSD_SRC 0x80 25*4882a593Smuzhiyun /* register 3 */ 26*4882a593Smuzhiyun #define CS4398_ATAPI_MASK 0x1f 27*4882a593Smuzhiyun #define CS4398_ATAPI_B_MUTE 0x00 28*4882a593Smuzhiyun #define CS4398_ATAPI_B_R 0x01 29*4882a593Smuzhiyun #define CS4398_ATAPI_B_L 0x02 30*4882a593Smuzhiyun #define CS4398_ATAPI_B_LR 0x03 31*4882a593Smuzhiyun #define CS4398_ATAPI_A_MUTE 0x00 32*4882a593Smuzhiyun #define CS4398_ATAPI_A_R 0x04 33*4882a593Smuzhiyun #define CS4398_ATAPI_A_L 0x08 34*4882a593Smuzhiyun #define CS4398_ATAPI_A_LR 0x0c 35*4882a593Smuzhiyun #define CS4398_ATAPI_MIX_LR_VOL 0x10 36*4882a593Smuzhiyun #define CS4398_INVERT_B 0x20 37*4882a593Smuzhiyun #define CS4398_INVERT_A 0x40 38*4882a593Smuzhiyun #define CS4398_VOL_B_EQ_A 0x80 39*4882a593Smuzhiyun /* register 4 */ 40*4882a593Smuzhiyun #define CS4398_MUTEP_MASK 0x03 41*4882a593Smuzhiyun #define CS4398_MUTEP_AUTO 0x00 42*4882a593Smuzhiyun #define CS4398_MUTEP_LOW 0x02 43*4882a593Smuzhiyun #define CS4398_MUTEP_HIGH 0x03 44*4882a593Smuzhiyun #define CS4398_MUTE_B 0x08 45*4882a593Smuzhiyun #define CS4398_MUTE_A 0x10 46*4882a593Smuzhiyun #define CS4398_MUTEC_A_EQ_B 0x20 47*4882a593Smuzhiyun #define CS4398_DAMUTE 0x40 48*4882a593Smuzhiyun #define CS4398_PAMUTE 0x80 49*4882a593Smuzhiyun /* register 5 */ 50*4882a593Smuzhiyun #define CS4398_VOL_A_MASK 0xff 51*4882a593Smuzhiyun /* register 6 */ 52*4882a593Smuzhiyun #define CS4398_VOL_B_MASK 0xff 53*4882a593Smuzhiyun /* register 7 */ 54*4882a593Smuzhiyun #define CS4398_DIR_DSD 0x01 55*4882a593Smuzhiyun #define CS4398_FILT_SEL 0x04 56*4882a593Smuzhiyun #define CS4398_RMP_DN 0x10 57*4882a593Smuzhiyun #define CS4398_RMP_UP 0x20 58*4882a593Smuzhiyun #define CS4398_ZERO_CROSS 0x40 59*4882a593Smuzhiyun #define CS4398_SOFT_RAMP 0x80 60*4882a593Smuzhiyun /* register 8 */ 61*4882a593Smuzhiyun #define CS4398_MCLKDIV3 0x08 62*4882a593Smuzhiyun #define CS4398_MCLKDIV2 0x10 63*4882a593Smuzhiyun #define CS4398_FREEZE 0x20 64*4882a593Smuzhiyun #define CS4398_CPEN 0x40 65*4882a593Smuzhiyun #define CS4398_PDN 0x80 66*4882a593Smuzhiyun /* register 9 */ 67*4882a593Smuzhiyun #define CS4398_DSD_PM_EN 0x01 68*4882a593Smuzhiyun #define CS4398_DSD_PM_MODE 0x02 69*4882a593Smuzhiyun #define CS4398_INVALID_DSD 0x04 70*4882a593Smuzhiyun #define CS4398_STATIC_DSD 0x08 71