1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #define CS4245_CHIP_ID 0x01 3*4882a593Smuzhiyun #define CS4245_POWER_CTRL 0x02 4*4882a593Smuzhiyun #define CS4245_DAC_CTRL_1 0x03 5*4882a593Smuzhiyun #define CS4245_ADC_CTRL 0x04 6*4882a593Smuzhiyun #define CS4245_MCLK_FREQ 0x05 7*4882a593Smuzhiyun #define CS4245_SIGNAL_SEL 0x06 8*4882a593Smuzhiyun #define CS4245_PGA_B_CTRL 0x07 9*4882a593Smuzhiyun #define CS4245_PGA_A_CTRL 0x08 10*4882a593Smuzhiyun #define CS4245_ANALOG_IN 0x09 11*4882a593Smuzhiyun #define CS4245_DAC_A_CTRL 0x0a 12*4882a593Smuzhiyun #define CS4245_DAC_B_CTRL 0x0b 13*4882a593Smuzhiyun #define CS4245_DAC_CTRL_2 0x0c 14*4882a593Smuzhiyun #define CS4245_INT_STATUS 0x0d 15*4882a593Smuzhiyun #define CS4245_INT_MASK 0x0e 16*4882a593Smuzhiyun #define CS4245_INT_MODE_MSB 0x0f 17*4882a593Smuzhiyun #define CS4245_INT_MODE_LSB 0x10 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Chip ID */ 20*4882a593Smuzhiyun #define CS4245_CHIP_PART_MASK 0xf0 21*4882a593Smuzhiyun #define CS4245_CHIP_REV_MASK 0x0f 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Power Control */ 24*4882a593Smuzhiyun #define CS4245_FREEZE 0x80 25*4882a593Smuzhiyun #define CS4245_PDN_MIC 0x08 26*4882a593Smuzhiyun #define CS4245_PDN_ADC 0x04 27*4882a593Smuzhiyun #define CS4245_PDN_DAC 0x02 28*4882a593Smuzhiyun #define CS4245_PDN 0x01 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* DAC Control */ 31*4882a593Smuzhiyun #define CS4245_DAC_FM_MASK 0xc0 32*4882a593Smuzhiyun #define CS4245_DAC_FM_SINGLE 0x00 33*4882a593Smuzhiyun #define CS4245_DAC_FM_DOUBLE 0x40 34*4882a593Smuzhiyun #define CS4245_DAC_FM_QUAD 0x80 35*4882a593Smuzhiyun #define CS4245_DAC_DIF_MASK 0x30 36*4882a593Smuzhiyun #define CS4245_DAC_DIF_LJUST 0x00 37*4882a593Smuzhiyun #define CS4245_DAC_DIF_I2S 0x10 38*4882a593Smuzhiyun #define CS4245_DAC_DIF_RJUST_16 0x20 39*4882a593Smuzhiyun #define CS4245_DAC_DIF_RJUST_24 0x30 40*4882a593Smuzhiyun #define CS4245_RESERVED_1 0x08 41*4882a593Smuzhiyun #define CS4245_MUTE_DAC 0x04 42*4882a593Smuzhiyun #define CS4245_DEEMPH 0x02 43*4882a593Smuzhiyun #define CS4245_DAC_MASTER 0x01 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* ADC Control */ 46*4882a593Smuzhiyun #define CS4245_ADC_FM_MASK 0xc0 47*4882a593Smuzhiyun #define CS4245_ADC_FM_SINGLE 0x00 48*4882a593Smuzhiyun #define CS4245_ADC_FM_DOUBLE 0x40 49*4882a593Smuzhiyun #define CS4245_ADC_FM_QUAD 0x80 50*4882a593Smuzhiyun #define CS4245_ADC_DIF_MASK 0x10 51*4882a593Smuzhiyun #define CS4245_ADC_DIF_LJUST 0x00 52*4882a593Smuzhiyun #define CS4245_ADC_DIF_I2S 0x10 53*4882a593Smuzhiyun #define CS4245_MUTE_ADC 0x04 54*4882a593Smuzhiyun #define CS4245_HPF_FREEZE 0x02 55*4882a593Smuzhiyun #define CS4245_ADC_MASTER 0x01 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* MCLK Frequency */ 58*4882a593Smuzhiyun #define CS4245_MCLK1_MASK 0x70 59*4882a593Smuzhiyun #define CS4245_MCLK1_SHIFT 4 60*4882a593Smuzhiyun #define CS4245_MCLK2_MASK 0x07 61*4882a593Smuzhiyun #define CS4245_MCLK2_SHIFT 0 62*4882a593Smuzhiyun #define CS4245_MCLK_1 0 63*4882a593Smuzhiyun #define CS4245_MCLK_1_5 1 64*4882a593Smuzhiyun #define CS4245_MCLK_2 2 65*4882a593Smuzhiyun #define CS4245_MCLK_3 3 66*4882a593Smuzhiyun #define CS4245_MCLK_4 4 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* Signal Selection */ 69*4882a593Smuzhiyun #define CS4245_A_OUT_SEL_MASK 0x60 70*4882a593Smuzhiyun #define CS4245_A_OUT_SEL_HIZ 0x00 71*4882a593Smuzhiyun #define CS4245_A_OUT_SEL_DAC 0x20 72*4882a593Smuzhiyun #define CS4245_A_OUT_SEL_PGA 0x40 73*4882a593Smuzhiyun #define CS4245_LOOP 0x02 74*4882a593Smuzhiyun #define CS4245_ASYNCH 0x01 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Channel B/A PGA Control */ 77*4882a593Smuzhiyun #define CS4245_PGA_GAIN_MASK 0x3f 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* ADC Input Control */ 80*4882a593Smuzhiyun #define CS4245_PGA_SOFT 0x10 81*4882a593Smuzhiyun #define CS4245_PGA_ZERO 0x08 82*4882a593Smuzhiyun #define CS4245_SEL_MASK 0x07 83*4882a593Smuzhiyun #define CS4245_SEL_MIC 0x00 84*4882a593Smuzhiyun #define CS4245_SEL_INPUT_1 0x01 85*4882a593Smuzhiyun #define CS4245_SEL_INPUT_2 0x02 86*4882a593Smuzhiyun #define CS4245_SEL_INPUT_3 0x03 87*4882a593Smuzhiyun #define CS4245_SEL_INPUT_4 0x04 88*4882a593Smuzhiyun #define CS4245_SEL_INPUT_5 0x05 89*4882a593Smuzhiyun #define CS4245_SEL_INPUT_6 0x06 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* DAC Channel A/B Volume Control */ 92*4882a593Smuzhiyun #define CS4245_VOL_MASK 0xff 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* DAC Control 2 */ 95*4882a593Smuzhiyun #define CS4245_DAC_SOFT 0x80 96*4882a593Smuzhiyun #define CS4245_DAC_ZERO 0x40 97*4882a593Smuzhiyun #define CS4245_INVERT_DAC 0x20 98*4882a593Smuzhiyun #define CS4245_INT_ACTIVE_HIGH 0x01 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* Interrupt Status/Mask/Mode */ 101*4882a593Smuzhiyun #define CS4245_ADC_CLK_ERR 0x08 102*4882a593Smuzhiyun #define CS4245_DAC_CLK_ERR 0x04 103*4882a593Smuzhiyun #define CS4245_ADC_OVFL 0x02 104*4882a593Smuzhiyun #define CS4245_ADC_UNDRFL 0x01 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define CS4245_SPI_ADDRESS_S (0x9e << 16) 107*4882a593Smuzhiyun #define CS4245_SPI_WRITE_S (0 << 16) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define CS4245_SPI_ADDRESS 0x9e 110*4882a593Smuzhiyun #define CS4245_SPI_WRITE 0 111*4882a593Smuzhiyun #define CS4245_SPI_READ 1 112