1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef CM9780_H_INCLUDED 3*4882a593Smuzhiyun #define CM9780_H_INCLUDED 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define CM9780_JACK 0x62 6*4882a593Smuzhiyun #define CM9780_MIXER 0x64 7*4882a593Smuzhiyun #define CM9780_GPIO_SETUP 0x70 8*4882a593Smuzhiyun #define CM9780_GPIO_STATUS 0x72 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* jack control */ 11*4882a593Smuzhiyun #define CM9780_RSOE 0x0001 12*4882a593Smuzhiyun #define CM9780_CBOE 0x0002 13*4882a593Smuzhiyun #define CM9780_SSOE 0x0004 14*4882a593Smuzhiyun #define CM9780_FROE 0x0008 15*4882a593Smuzhiyun #define CM9780_HP2FMICOE 0x0010 16*4882a593Smuzhiyun #define CM9780_CB2MICOE 0x0020 17*4882a593Smuzhiyun #define CM9780_FMIC2LI 0x0040 18*4882a593Smuzhiyun #define CM9780_FMIC2MIC 0x0080 19*4882a593Smuzhiyun #define CM9780_HP2LI 0x0100 20*4882a593Smuzhiyun #define CM9780_HP2MIC 0x0200 21*4882a593Smuzhiyun #define CM9780_MIC2LI 0x0400 22*4882a593Smuzhiyun #define CM9780_MIC2MIC 0x0800 23*4882a593Smuzhiyun #define CM9780_LI2LI 0x1000 24*4882a593Smuzhiyun #define CM9780_LI2MIC 0x2000 25*4882a593Smuzhiyun #define CM9780_LO2LI 0x4000 26*4882a593Smuzhiyun #define CM9780_LO2MIC 0x8000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* mixer control */ 29*4882a593Smuzhiyun #define CM9780_BSTSEL 0x0001 30*4882a593Smuzhiyun #define CM9780_STRO_MIC 0x0002 31*4882a593Smuzhiyun #define CM9780_SPDI_FREX 0x0004 32*4882a593Smuzhiyun #define CM9780_SPDI_SSEX 0x0008 33*4882a593Smuzhiyun #define CM9780_SPDI_CBEX 0x0010 34*4882a593Smuzhiyun #define CM9780_SPDI_RSEX 0x0020 35*4882a593Smuzhiyun #define CM9780_MIX2FR 0x0040 36*4882a593Smuzhiyun #define CM9780_MIX2SS 0x0080 37*4882a593Smuzhiyun #define CM9780_MIX2CB 0x0100 38*4882a593Smuzhiyun #define CM9780_MIX2RS 0x0200 39*4882a593Smuzhiyun #define CM9780_MIX2FR_EX 0x0400 40*4882a593Smuzhiyun #define CM9780_MIX2SS_EX 0x0800 41*4882a593Smuzhiyun #define CM9780_MIX2CB_EX 0x1000 42*4882a593Smuzhiyun #define CM9780_MIX2RS_EX 0x2000 43*4882a593Smuzhiyun #define CM9780_P47_IO 0x4000 44*4882a593Smuzhiyun #define CM9780_PCBSW 0x8000 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* GPIO setup */ 47*4882a593Smuzhiyun #define CM9780_GPI0EN 0x0001 48*4882a593Smuzhiyun #define CM9780_GPI1EN 0x0002 49*4882a593Smuzhiyun #define CM9780_SENSE_P 0x0004 50*4882a593Smuzhiyun #define CM9780_LOCK_P 0x0008 51*4882a593Smuzhiyun #define CM9780_GPIO0P 0x0010 52*4882a593Smuzhiyun #define CM9780_GPIO1P 0x0020 53*4882a593Smuzhiyun #define CM9780_GPIO0IO 0x0100 54*4882a593Smuzhiyun #define CM9780_GPIO1IO 0x0200 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* GPIO status */ 57*4882a593Smuzhiyun #define CM9780_GPO0 0x0001 58*4882a593Smuzhiyun #define CM9780_GPO1 0x0002 59*4882a593Smuzhiyun #define CM9780_GPIO0S 0x0010 60*4882a593Smuzhiyun #define CM9780_GPIO1S 0x0020 61*4882a593Smuzhiyun #define CM9780_GPII0S 0x0100 62*4882a593Smuzhiyun #define CM9780_GPII1S 0x0200 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif 65