1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef AK4396_H_INCLUDED 3*4882a593Smuzhiyun #define AK4396_H_INCLUDED 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define AK4396_WRITE 0x2000 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define AK4396_CONTROL_1 0 8*4882a593Smuzhiyun #define AK4396_CONTROL_2 1 9*4882a593Smuzhiyun #define AK4396_CONTROL_3 2 10*4882a593Smuzhiyun #define AK4396_LCH_ATT 3 11*4882a593Smuzhiyun #define AK4396_RCH_ATT 4 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* control 1 */ 14*4882a593Smuzhiyun #define AK4396_RSTN 0x01 15*4882a593Smuzhiyun #define AK4396_DIF_MASK 0x0e 16*4882a593Smuzhiyun #define AK4396_DIF_16_LSB 0x00 17*4882a593Smuzhiyun #define AK4396_DIF_20_LSB 0x02 18*4882a593Smuzhiyun #define AK4396_DIF_24_MSB 0x04 19*4882a593Smuzhiyun #define AK4396_DIF_24_I2S 0x06 20*4882a593Smuzhiyun #define AK4396_DIF_24_LSB 0x08 21*4882a593Smuzhiyun #define AK4396_ACKS 0x80 22*4882a593Smuzhiyun /* control 2 */ 23*4882a593Smuzhiyun #define AK4396_SMUTE 0x01 24*4882a593Smuzhiyun #define AK4396_DEM_MASK 0x06 25*4882a593Smuzhiyun #define AK4396_DEM_441 0x00 26*4882a593Smuzhiyun #define AK4396_DEM_OFF 0x02 27*4882a593Smuzhiyun #define AK4396_DEM_48 0x04 28*4882a593Smuzhiyun #define AK4396_DEM_32 0x06 29*4882a593Smuzhiyun #define AK4396_DFS_MASK 0x18 30*4882a593Smuzhiyun #define AK4396_DFS_NORMAL 0x00 31*4882a593Smuzhiyun #define AK4396_DFS_DOUBLE 0x08 32*4882a593Smuzhiyun #define AK4396_DFS_QUAD 0x10 33*4882a593Smuzhiyun #define AK4396_SLOW 0x20 34*4882a593Smuzhiyun #define AK4396_DZFM 0x40 35*4882a593Smuzhiyun #define AK4396_DZFE 0x80 36*4882a593Smuzhiyun /* control 3 */ 37*4882a593Smuzhiyun #define AK4396_DZFB 0x04 38*4882a593Smuzhiyun #define AK4396_DCKB 0x10 39*4882a593Smuzhiyun #define AK4396_DCKS 0x20 40*4882a593Smuzhiyun #define AK4396_DSDM 0x40 41*4882a593Smuzhiyun #define AK4396_D_P_MASK 0x80 42*4882a593Smuzhiyun #define AK4396_PCM 0x00 43*4882a593Smuzhiyun #define AK4396_DSD 0x80 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif 46