1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for NeoMagic 256AV and 256ZX chipsets.
4*4882a593Smuzhiyun * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Based on nm256_audio.c OSS driver in linux kernel.
7*4882a593Smuzhiyun * The original author of OSS nm256 driver wishes to remain anonymous,
8*4882a593Smuzhiyun * so I just put my acknoledgment to him/her here.
9*4882a593Smuzhiyun * The original author's web page is found at
10*4882a593Smuzhiyun * http://www.uglx.org/sony.html
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/pci.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/mutex.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <sound/core.h>
23*4882a593Smuzhiyun #include <sound/info.h>
24*4882a593Smuzhiyun #include <sound/control.h>
25*4882a593Smuzhiyun #include <sound/pcm.h>
26*4882a593Smuzhiyun #include <sound/ac97_codec.h>
27*4882a593Smuzhiyun #include <sound/initval.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define CARD_NAME "NeoMagic 256AV/ZX"
30*4882a593Smuzhiyun #define DRIVER_NAME "NM256"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
33*4882a593Smuzhiyun MODULE_DESCRIPTION("NeoMagic NM256AV/ZX");
34*4882a593Smuzhiyun MODULE_LICENSE("GPL");
35*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{{NeoMagic,NM256AV},"
36*4882a593Smuzhiyun "{NeoMagic,NM256ZX}}");
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * some compile conditions.
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static int index = SNDRV_DEFAULT_IDX1; /* Index */
43*4882a593Smuzhiyun static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
44*4882a593Smuzhiyun static int playback_bufsize = 16;
45*4882a593Smuzhiyun static int capture_bufsize = 16;
46*4882a593Smuzhiyun static bool force_ac97; /* disabled as default */
47*4882a593Smuzhiyun static int buffer_top; /* not specified */
48*4882a593Smuzhiyun static bool use_cache; /* disabled */
49*4882a593Smuzhiyun static bool vaio_hack; /* disabled */
50*4882a593Smuzhiyun static bool reset_workaround;
51*4882a593Smuzhiyun static bool reset_workaround_2;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun module_param(index, int, 0444);
54*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
55*4882a593Smuzhiyun module_param(id, charp, 0444);
56*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
57*4882a593Smuzhiyun module_param(playback_bufsize, int, 0444);
58*4882a593Smuzhiyun MODULE_PARM_DESC(playback_bufsize, "DAC frame size in kB for " CARD_NAME " soundcard.");
59*4882a593Smuzhiyun module_param(capture_bufsize, int, 0444);
60*4882a593Smuzhiyun MODULE_PARM_DESC(capture_bufsize, "ADC frame size in kB for " CARD_NAME " soundcard.");
61*4882a593Smuzhiyun module_param(force_ac97, bool, 0444);
62*4882a593Smuzhiyun MODULE_PARM_DESC(force_ac97, "Force to use AC97 codec for " CARD_NAME " soundcard.");
63*4882a593Smuzhiyun module_param(buffer_top, int, 0444);
64*4882a593Smuzhiyun MODULE_PARM_DESC(buffer_top, "Set the top address of audio buffer for " CARD_NAME " soundcard.");
65*4882a593Smuzhiyun module_param(use_cache, bool, 0444);
66*4882a593Smuzhiyun MODULE_PARM_DESC(use_cache, "Enable the cache for coefficient table access.");
67*4882a593Smuzhiyun module_param(vaio_hack, bool, 0444);
68*4882a593Smuzhiyun MODULE_PARM_DESC(vaio_hack, "Enable workaround for Sony VAIO notebooks.");
69*4882a593Smuzhiyun module_param(reset_workaround, bool, 0444);
70*4882a593Smuzhiyun MODULE_PARM_DESC(reset_workaround, "Enable AC97 RESET workaround for some laptops.");
71*4882a593Smuzhiyun module_param(reset_workaround_2, bool, 0444);
72*4882a593Smuzhiyun MODULE_PARM_DESC(reset_workaround_2, "Enable extended AC97 RESET workaround for some other laptops.");
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* just for backward compatibility */
75*4882a593Smuzhiyun static bool enable;
76*4882a593Smuzhiyun module_param(enable, bool, 0444);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * hw definitions
82*4882a593Smuzhiyun */
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* The BIOS signature. */
85*4882a593Smuzhiyun #define NM_SIGNATURE 0x4e4d0000
86*4882a593Smuzhiyun /* Signature mask. */
87*4882a593Smuzhiyun #define NM_SIG_MASK 0xffff0000
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Size of the second memory area. */
90*4882a593Smuzhiyun #define NM_PORT2_SIZE 4096
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* The base offset of the mixer in the second memory area. */
93*4882a593Smuzhiyun #define NM_MIXER_OFFSET 0x600
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* The maximum size of a coefficient entry. */
96*4882a593Smuzhiyun #define NM_MAX_PLAYBACK_COEF_SIZE 0x5000
97*4882a593Smuzhiyun #define NM_MAX_RECORD_COEF_SIZE 0x1260
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* The interrupt register. */
100*4882a593Smuzhiyun #define NM_INT_REG 0xa04
101*4882a593Smuzhiyun /* And its bits. */
102*4882a593Smuzhiyun #define NM_PLAYBACK_INT 0x40
103*4882a593Smuzhiyun #define NM_RECORD_INT 0x100
104*4882a593Smuzhiyun #define NM_MISC_INT_1 0x4000
105*4882a593Smuzhiyun #define NM_MISC_INT_2 0x1
106*4882a593Smuzhiyun #define NM_ACK_INT(chip, X) snd_nm256_writew(chip, NM_INT_REG, (X) << 1)
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* The AV's "mixer ready" status bit and location. */
109*4882a593Smuzhiyun #define NM_MIXER_STATUS_OFFSET 0xa04
110*4882a593Smuzhiyun #define NM_MIXER_READY_MASK 0x0800
111*4882a593Smuzhiyun #define NM_MIXER_PRESENCE 0xa06
112*4882a593Smuzhiyun #define NM_PRESENCE_MASK 0x0050
113*4882a593Smuzhiyun #define NM_PRESENCE_VALUE 0x0040
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun * For the ZX. It uses the same interrupt register, but it holds 32
117*4882a593Smuzhiyun * bits instead of 16.
118*4882a593Smuzhiyun */
119*4882a593Smuzhiyun #define NM2_PLAYBACK_INT 0x10000
120*4882a593Smuzhiyun #define NM2_RECORD_INT 0x80000
121*4882a593Smuzhiyun #define NM2_MISC_INT_1 0x8
122*4882a593Smuzhiyun #define NM2_MISC_INT_2 0x2
123*4882a593Smuzhiyun #define NM2_ACK_INT(chip, X) snd_nm256_writel(chip, NM_INT_REG, (X))
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* The ZX's "mixer ready" status bit and location. */
126*4882a593Smuzhiyun #define NM2_MIXER_STATUS_OFFSET 0xa06
127*4882a593Smuzhiyun #define NM2_MIXER_READY_MASK 0x0800
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* The playback registers start from here. */
130*4882a593Smuzhiyun #define NM_PLAYBACK_REG_OFFSET 0x0
131*4882a593Smuzhiyun /* The record registers start from here. */
132*4882a593Smuzhiyun #define NM_RECORD_REG_OFFSET 0x200
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* The rate register is located 2 bytes from the start of the register area. */
135*4882a593Smuzhiyun #define NM_RATE_REG_OFFSET 2
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* Mono/stereo flag, number of bits on playback, and rate mask. */
138*4882a593Smuzhiyun #define NM_RATE_STEREO 1
139*4882a593Smuzhiyun #define NM_RATE_BITS_16 2
140*4882a593Smuzhiyun #define NM_RATE_MASK 0xf0
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* Playback enable register. */
143*4882a593Smuzhiyun #define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1)
144*4882a593Smuzhiyun #define NM_PLAYBACK_ENABLE_FLAG 1
145*4882a593Smuzhiyun #define NM_PLAYBACK_ONESHOT 2
146*4882a593Smuzhiyun #define NM_PLAYBACK_FREERUN 4
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* Mutes the audio output. */
149*4882a593Smuzhiyun #define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18)
150*4882a593Smuzhiyun #define NM_AUDIO_MUTE_LEFT 0x8000
151*4882a593Smuzhiyun #define NM_AUDIO_MUTE_RIGHT 0x0080
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* Recording enable register. */
154*4882a593Smuzhiyun #define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0)
155*4882a593Smuzhiyun #define NM_RECORD_ENABLE_FLAG 1
156*4882a593Smuzhiyun #define NM_RECORD_FREERUN 2
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* coefficient buffer pointer */
159*4882a593Smuzhiyun #define NM_COEFF_START_OFFSET 0x1c
160*4882a593Smuzhiyun #define NM_COEFF_END_OFFSET 0x20
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* DMA buffer offsets */
163*4882a593Smuzhiyun #define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4)
164*4882a593Smuzhiyun #define NM_RBUFFER_END (NM_RECORD_REG_OFFSET + 0x10)
165*4882a593Smuzhiyun #define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc)
166*4882a593Smuzhiyun #define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8)
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun #define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4)
169*4882a593Smuzhiyun #define NM_PBUFFER_END (NM_PLAYBACK_REG_OFFSET + 0x14)
170*4882a593Smuzhiyun #define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc)
171*4882a593Smuzhiyun #define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8)
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun struct nm256_stream {
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun struct nm256 *chip;
176*4882a593Smuzhiyun struct snd_pcm_substream *substream;
177*4882a593Smuzhiyun int running;
178*4882a593Smuzhiyun int suspended;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun u32 buf; /* offset from chip->buffer */
181*4882a593Smuzhiyun int bufsize; /* buffer size in bytes */
182*4882a593Smuzhiyun void __iomem *bufptr; /* mapped pointer */
183*4882a593Smuzhiyun unsigned long bufptr_addr; /* physical address of the mapped pointer */
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun int dma_size; /* buffer size of the substream in bytes */
186*4882a593Smuzhiyun int period_size; /* period size in bytes */
187*4882a593Smuzhiyun int periods; /* # of periods */
188*4882a593Smuzhiyun int shift; /* bit shifts */
189*4882a593Smuzhiyun int cur_period; /* current period # */
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun struct nm256 {
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun struct snd_card *card;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun void __iomem *cport; /* control port */
198*4882a593Smuzhiyun struct resource *res_cport; /* its resource */
199*4882a593Smuzhiyun unsigned long cport_addr; /* physical address */
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun void __iomem *buffer; /* buffer */
202*4882a593Smuzhiyun struct resource *res_buffer; /* its resource */
203*4882a593Smuzhiyun unsigned long buffer_addr; /* buffer phyiscal address */
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun u32 buffer_start; /* start offset from pci resource 0 */
206*4882a593Smuzhiyun u32 buffer_end; /* end offset */
207*4882a593Smuzhiyun u32 buffer_size; /* total buffer size */
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun u32 all_coeff_buf; /* coefficient buffer */
210*4882a593Smuzhiyun u32 coeff_buf[2]; /* coefficient buffer for each stream */
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun unsigned int coeffs_current: 1; /* coeff. table is loaded? */
213*4882a593Smuzhiyun unsigned int use_cache: 1; /* use one big coef. table */
214*4882a593Smuzhiyun unsigned int reset_workaround: 1; /* Workaround for some laptops to avoid freeze */
215*4882a593Smuzhiyun unsigned int reset_workaround_2: 1; /* Extended workaround for some other laptops to avoid freeze */
216*4882a593Smuzhiyun unsigned int in_resume: 1;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun int mixer_base; /* register offset of ac97 mixer */
219*4882a593Smuzhiyun int mixer_status_offset; /* offset of mixer status reg. */
220*4882a593Smuzhiyun int mixer_status_mask; /* bit mask to test the mixer status */
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun int irq;
223*4882a593Smuzhiyun int irq_acks;
224*4882a593Smuzhiyun irq_handler_t interrupt;
225*4882a593Smuzhiyun int badintrcount; /* counter to check bogus interrupts */
226*4882a593Smuzhiyun struct mutex irq_mutex;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun struct nm256_stream streams[2];
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun struct snd_ac97 *ac97;
231*4882a593Smuzhiyun unsigned short *ac97_regs; /* register caches, only for valid regs */
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun struct snd_pcm *pcm;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun struct pci_dev *pci;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun spinlock_t reg_lock;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun /*
243*4882a593Smuzhiyun * include coefficient table
244*4882a593Smuzhiyun */
245*4882a593Smuzhiyun #include "nm256_coef.c"
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /*
249*4882a593Smuzhiyun * PCI ids
250*4882a593Smuzhiyun */
251*4882a593Smuzhiyun static const struct pci_device_id snd_nm256_ids[] = {
252*4882a593Smuzhiyun {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO), 0},
253*4882a593Smuzhiyun {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO), 0},
254*4882a593Smuzhiyun {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO), 0},
255*4882a593Smuzhiyun {0,},
256*4882a593Smuzhiyun };
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, snd_nm256_ids);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /*
262*4882a593Smuzhiyun * lowlvel stuffs
263*4882a593Smuzhiyun */
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun static inline u8
snd_nm256_readb(struct nm256 * chip,int offset)266*4882a593Smuzhiyun snd_nm256_readb(struct nm256 *chip, int offset)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun return readb(chip->cport + offset);
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun static inline u16
snd_nm256_readw(struct nm256 * chip,int offset)272*4882a593Smuzhiyun snd_nm256_readw(struct nm256 *chip, int offset)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun return readw(chip->cport + offset);
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun static inline u32
snd_nm256_readl(struct nm256 * chip,int offset)278*4882a593Smuzhiyun snd_nm256_readl(struct nm256 *chip, int offset)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun return readl(chip->cport + offset);
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun static inline void
snd_nm256_writeb(struct nm256 * chip,int offset,u8 val)284*4882a593Smuzhiyun snd_nm256_writeb(struct nm256 *chip, int offset, u8 val)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun writeb(val, chip->cport + offset);
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun static inline void
snd_nm256_writew(struct nm256 * chip,int offset,u16 val)290*4882a593Smuzhiyun snd_nm256_writew(struct nm256 *chip, int offset, u16 val)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun writew(val, chip->cport + offset);
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun static inline void
snd_nm256_writel(struct nm256 * chip,int offset,u32 val)296*4882a593Smuzhiyun snd_nm256_writel(struct nm256 *chip, int offset, u32 val)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun writel(val, chip->cport + offset);
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun static inline void
snd_nm256_write_buffer(struct nm256 * chip,const void * src,int offset,int size)302*4882a593Smuzhiyun snd_nm256_write_buffer(struct nm256 *chip, const void *src, int offset, int size)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun offset -= chip->buffer_start;
305*4882a593Smuzhiyun #ifdef CONFIG_SND_DEBUG
306*4882a593Smuzhiyun if (offset < 0 || offset >= chip->buffer_size) {
307*4882a593Smuzhiyun dev_err(chip->card->dev,
308*4882a593Smuzhiyun "write_buffer invalid offset = %d size = %d\n",
309*4882a593Smuzhiyun offset, size);
310*4882a593Smuzhiyun return;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun #endif
313*4882a593Smuzhiyun memcpy_toio(chip->buffer + offset, src, size);
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /*
317*4882a593Smuzhiyun * coefficient handlers -- what a magic!
318*4882a593Smuzhiyun */
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun static u16
snd_nm256_get_start_offset(int which)321*4882a593Smuzhiyun snd_nm256_get_start_offset(int which)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun u16 offset = 0;
324*4882a593Smuzhiyun while (which-- > 0)
325*4882a593Smuzhiyun offset += coefficient_sizes[which];
326*4882a593Smuzhiyun return offset;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun static void
snd_nm256_load_one_coefficient(struct nm256 * chip,int stream,u32 port,int which)330*4882a593Smuzhiyun snd_nm256_load_one_coefficient(struct nm256 *chip, int stream, u32 port, int which)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun u32 coeff_buf = chip->coeff_buf[stream];
333*4882a593Smuzhiyun u16 offset = snd_nm256_get_start_offset(which);
334*4882a593Smuzhiyun u16 size = coefficient_sizes[which];
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun snd_nm256_write_buffer(chip, coefficients + offset, coeff_buf, size);
337*4882a593Smuzhiyun snd_nm256_writel(chip, port, coeff_buf);
338*4882a593Smuzhiyun /* ??? Record seems to behave differently than playback. */
339*4882a593Smuzhiyun if (stream == SNDRV_PCM_STREAM_PLAYBACK)
340*4882a593Smuzhiyun size--;
341*4882a593Smuzhiyun snd_nm256_writel(chip, port + 4, coeff_buf + size);
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun static void
snd_nm256_load_coefficient(struct nm256 * chip,int stream,int number)345*4882a593Smuzhiyun snd_nm256_load_coefficient(struct nm256 *chip, int stream, int number)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun /* The enable register for the specified engine. */
348*4882a593Smuzhiyun u32 poffset = (stream == SNDRV_PCM_STREAM_CAPTURE ?
349*4882a593Smuzhiyun NM_RECORD_ENABLE_REG : NM_PLAYBACK_ENABLE_REG);
350*4882a593Smuzhiyun u32 addr = NM_COEFF_START_OFFSET;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun addr += (stream == SNDRV_PCM_STREAM_CAPTURE ?
353*4882a593Smuzhiyun NM_RECORD_REG_OFFSET : NM_PLAYBACK_REG_OFFSET);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun if (snd_nm256_readb(chip, poffset) & 1) {
356*4882a593Smuzhiyun dev_dbg(chip->card->dev,
357*4882a593Smuzhiyun "NM256: Engine was enabled while loading coefficients!\n");
358*4882a593Smuzhiyun return;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun /* The recording engine uses coefficient values 8-15. */
362*4882a593Smuzhiyun number &= 7;
363*4882a593Smuzhiyun if (stream == SNDRV_PCM_STREAM_CAPTURE)
364*4882a593Smuzhiyun number += 8;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun if (! chip->use_cache) {
367*4882a593Smuzhiyun snd_nm256_load_one_coefficient(chip, stream, addr, number);
368*4882a593Smuzhiyun return;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun if (! chip->coeffs_current) {
371*4882a593Smuzhiyun snd_nm256_write_buffer(chip, coefficients, chip->all_coeff_buf,
372*4882a593Smuzhiyun NM_TOTAL_COEFF_COUNT * 4);
373*4882a593Smuzhiyun chip->coeffs_current = 1;
374*4882a593Smuzhiyun } else {
375*4882a593Smuzhiyun u32 base = chip->all_coeff_buf;
376*4882a593Smuzhiyun u32 offset = snd_nm256_get_start_offset(number);
377*4882a593Smuzhiyun u32 end_offset = offset + coefficient_sizes[number];
378*4882a593Smuzhiyun snd_nm256_writel(chip, addr, base + offset);
379*4882a593Smuzhiyun if (stream == SNDRV_PCM_STREAM_PLAYBACK)
380*4882a593Smuzhiyun end_offset--;
381*4882a593Smuzhiyun snd_nm256_writel(chip, addr + 4, base + end_offset);
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun /* The actual rates supported by the card. */
387*4882a593Smuzhiyun static const unsigned int samplerates[8] = {
388*4882a593Smuzhiyun 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
389*4882a593Smuzhiyun };
390*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list constraints_rates = {
391*4882a593Smuzhiyun .count = ARRAY_SIZE(samplerates),
392*4882a593Smuzhiyun .list = samplerates,
393*4882a593Smuzhiyun .mask = 0,
394*4882a593Smuzhiyun };
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun /*
397*4882a593Smuzhiyun * return the index of the target rate
398*4882a593Smuzhiyun */
399*4882a593Smuzhiyun static int
snd_nm256_fixed_rate(unsigned int rate)400*4882a593Smuzhiyun snd_nm256_fixed_rate(unsigned int rate)
401*4882a593Smuzhiyun {
402*4882a593Smuzhiyun unsigned int i;
403*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
404*4882a593Smuzhiyun if (rate == samplerates[i])
405*4882a593Smuzhiyun return i;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun snd_BUG();
408*4882a593Smuzhiyun return 0;
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun /*
412*4882a593Smuzhiyun * set sample rate and format
413*4882a593Smuzhiyun */
414*4882a593Smuzhiyun static void
snd_nm256_set_format(struct nm256 * chip,struct nm256_stream * s,struct snd_pcm_substream * substream)415*4882a593Smuzhiyun snd_nm256_set_format(struct nm256 *chip, struct nm256_stream *s,
416*4882a593Smuzhiyun struct snd_pcm_substream *substream)
417*4882a593Smuzhiyun {
418*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
419*4882a593Smuzhiyun int rate_index = snd_nm256_fixed_rate(runtime->rate);
420*4882a593Smuzhiyun unsigned char ratebits = (rate_index << 4) & NM_RATE_MASK;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun s->shift = 0;
423*4882a593Smuzhiyun if (snd_pcm_format_width(runtime->format) == 16) {
424*4882a593Smuzhiyun ratebits |= NM_RATE_BITS_16;
425*4882a593Smuzhiyun s->shift++;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun if (runtime->channels > 1) {
428*4882a593Smuzhiyun ratebits |= NM_RATE_STEREO;
429*4882a593Smuzhiyun s->shift++;
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun runtime->rate = samplerates[rate_index];
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun switch (substream->stream) {
435*4882a593Smuzhiyun case SNDRV_PCM_STREAM_PLAYBACK:
436*4882a593Smuzhiyun snd_nm256_load_coefficient(chip, 0, rate_index); /* 0 = playback */
437*4882a593Smuzhiyun snd_nm256_writeb(chip,
438*4882a593Smuzhiyun NM_PLAYBACK_REG_OFFSET + NM_RATE_REG_OFFSET,
439*4882a593Smuzhiyun ratebits);
440*4882a593Smuzhiyun break;
441*4882a593Smuzhiyun case SNDRV_PCM_STREAM_CAPTURE:
442*4882a593Smuzhiyun snd_nm256_load_coefficient(chip, 1, rate_index); /* 1 = record */
443*4882a593Smuzhiyun snd_nm256_writeb(chip,
444*4882a593Smuzhiyun NM_RECORD_REG_OFFSET + NM_RATE_REG_OFFSET,
445*4882a593Smuzhiyun ratebits);
446*4882a593Smuzhiyun break;
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun /* acquire interrupt */
snd_nm256_acquire_irq(struct nm256 * chip)451*4882a593Smuzhiyun static int snd_nm256_acquire_irq(struct nm256 *chip)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun mutex_lock(&chip->irq_mutex);
454*4882a593Smuzhiyun if (chip->irq < 0) {
455*4882a593Smuzhiyun if (request_irq(chip->pci->irq, chip->interrupt, IRQF_SHARED,
456*4882a593Smuzhiyun KBUILD_MODNAME, chip)) {
457*4882a593Smuzhiyun dev_err(chip->card->dev,
458*4882a593Smuzhiyun "unable to grab IRQ %d\n", chip->pci->irq);
459*4882a593Smuzhiyun mutex_unlock(&chip->irq_mutex);
460*4882a593Smuzhiyun return -EBUSY;
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun chip->irq = chip->pci->irq;
463*4882a593Smuzhiyun chip->card->sync_irq = chip->irq;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun chip->irq_acks++;
466*4882a593Smuzhiyun mutex_unlock(&chip->irq_mutex);
467*4882a593Smuzhiyun return 0;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun /* release interrupt */
snd_nm256_release_irq(struct nm256 * chip)471*4882a593Smuzhiyun static void snd_nm256_release_irq(struct nm256 *chip)
472*4882a593Smuzhiyun {
473*4882a593Smuzhiyun mutex_lock(&chip->irq_mutex);
474*4882a593Smuzhiyun if (chip->irq_acks > 0)
475*4882a593Smuzhiyun chip->irq_acks--;
476*4882a593Smuzhiyun if (chip->irq_acks == 0 && chip->irq >= 0) {
477*4882a593Smuzhiyun free_irq(chip->irq, chip);
478*4882a593Smuzhiyun chip->irq = -1;
479*4882a593Smuzhiyun chip->card->sync_irq = -1;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun mutex_unlock(&chip->irq_mutex);
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun /*
485*4882a593Smuzhiyun * start / stop
486*4882a593Smuzhiyun */
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun /* update the watermark (current period) */
snd_nm256_pcm_mark(struct nm256 * chip,struct nm256_stream * s,int reg)489*4882a593Smuzhiyun static void snd_nm256_pcm_mark(struct nm256 *chip, struct nm256_stream *s, int reg)
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun s->cur_period++;
492*4882a593Smuzhiyun s->cur_period %= s->periods;
493*4882a593Smuzhiyun snd_nm256_writel(chip, reg, s->buf + s->cur_period * s->period_size);
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun #define snd_nm256_playback_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_PBUFFER_WMARK)
497*4882a593Smuzhiyun #define snd_nm256_capture_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_RBUFFER_WMARK)
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun static void
snd_nm256_playback_start(struct nm256 * chip,struct nm256_stream * s,struct snd_pcm_substream * substream)500*4882a593Smuzhiyun snd_nm256_playback_start(struct nm256 *chip, struct nm256_stream *s,
501*4882a593Smuzhiyun struct snd_pcm_substream *substream)
502*4882a593Smuzhiyun {
503*4882a593Smuzhiyun /* program buffer pointers */
504*4882a593Smuzhiyun snd_nm256_writel(chip, NM_PBUFFER_START, s->buf);
505*4882a593Smuzhiyun snd_nm256_writel(chip, NM_PBUFFER_END, s->buf + s->dma_size - (1 << s->shift));
506*4882a593Smuzhiyun snd_nm256_writel(chip, NM_PBUFFER_CURRP, s->buf);
507*4882a593Smuzhiyun snd_nm256_playback_mark(chip, s);
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun /* Enable playback engine and interrupts. */
510*4882a593Smuzhiyun snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG,
511*4882a593Smuzhiyun NM_PLAYBACK_ENABLE_FLAG | NM_PLAYBACK_FREERUN);
512*4882a593Smuzhiyun /* Enable both channels. */
513*4882a593Smuzhiyun snd_nm256_writew(chip, NM_AUDIO_MUTE_REG, 0x0);
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun static void
snd_nm256_capture_start(struct nm256 * chip,struct nm256_stream * s,struct snd_pcm_substream * substream)517*4882a593Smuzhiyun snd_nm256_capture_start(struct nm256 *chip, struct nm256_stream *s,
518*4882a593Smuzhiyun struct snd_pcm_substream *substream)
519*4882a593Smuzhiyun {
520*4882a593Smuzhiyun /* program buffer pointers */
521*4882a593Smuzhiyun snd_nm256_writel(chip, NM_RBUFFER_START, s->buf);
522*4882a593Smuzhiyun snd_nm256_writel(chip, NM_RBUFFER_END, s->buf + s->dma_size);
523*4882a593Smuzhiyun snd_nm256_writel(chip, NM_RBUFFER_CURRP, s->buf);
524*4882a593Smuzhiyun snd_nm256_capture_mark(chip, s);
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun /* Enable playback engine and interrupts. */
527*4882a593Smuzhiyun snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG,
528*4882a593Smuzhiyun NM_RECORD_ENABLE_FLAG | NM_RECORD_FREERUN);
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun /* Stop the play engine. */
532*4882a593Smuzhiyun static void
snd_nm256_playback_stop(struct nm256 * chip)533*4882a593Smuzhiyun snd_nm256_playback_stop(struct nm256 *chip)
534*4882a593Smuzhiyun {
535*4882a593Smuzhiyun /* Shut off sound from both channels. */
536*4882a593Smuzhiyun snd_nm256_writew(chip, NM_AUDIO_MUTE_REG,
537*4882a593Smuzhiyun NM_AUDIO_MUTE_LEFT | NM_AUDIO_MUTE_RIGHT);
538*4882a593Smuzhiyun /* Disable play engine. */
539*4882a593Smuzhiyun snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG, 0);
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun static void
snd_nm256_capture_stop(struct nm256 * chip)543*4882a593Smuzhiyun snd_nm256_capture_stop(struct nm256 *chip)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun /* Disable recording engine. */
546*4882a593Smuzhiyun snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG, 0);
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun static int
snd_nm256_playback_trigger(struct snd_pcm_substream * substream,int cmd)550*4882a593Smuzhiyun snd_nm256_playback_trigger(struct snd_pcm_substream *substream, int cmd)
551*4882a593Smuzhiyun {
552*4882a593Smuzhiyun struct nm256 *chip = snd_pcm_substream_chip(substream);
553*4882a593Smuzhiyun struct nm256_stream *s = substream->runtime->private_data;
554*4882a593Smuzhiyun int err = 0;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun if (snd_BUG_ON(!s))
557*4882a593Smuzhiyun return -ENXIO;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
560*4882a593Smuzhiyun switch (cmd) {
561*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
562*4882a593Smuzhiyun s->suspended = 0;
563*4882a593Smuzhiyun fallthrough;
564*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
565*4882a593Smuzhiyun if (! s->running) {
566*4882a593Smuzhiyun snd_nm256_playback_start(chip, s, substream);
567*4882a593Smuzhiyun s->running = 1;
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun break;
570*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
571*4882a593Smuzhiyun s->suspended = 1;
572*4882a593Smuzhiyun fallthrough;
573*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
574*4882a593Smuzhiyun if (s->running) {
575*4882a593Smuzhiyun snd_nm256_playback_stop(chip);
576*4882a593Smuzhiyun s->running = 0;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun break;
579*4882a593Smuzhiyun default:
580*4882a593Smuzhiyun err = -EINVAL;
581*4882a593Smuzhiyun break;
582*4882a593Smuzhiyun }
583*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
584*4882a593Smuzhiyun return err;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun static int
snd_nm256_capture_trigger(struct snd_pcm_substream * substream,int cmd)588*4882a593Smuzhiyun snd_nm256_capture_trigger(struct snd_pcm_substream *substream, int cmd)
589*4882a593Smuzhiyun {
590*4882a593Smuzhiyun struct nm256 *chip = snd_pcm_substream_chip(substream);
591*4882a593Smuzhiyun struct nm256_stream *s = substream->runtime->private_data;
592*4882a593Smuzhiyun int err = 0;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun if (snd_BUG_ON(!s))
595*4882a593Smuzhiyun return -ENXIO;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
598*4882a593Smuzhiyun switch (cmd) {
599*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
600*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
601*4882a593Smuzhiyun if (! s->running) {
602*4882a593Smuzhiyun snd_nm256_capture_start(chip, s, substream);
603*4882a593Smuzhiyun s->running = 1;
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun break;
606*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
607*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
608*4882a593Smuzhiyun if (s->running) {
609*4882a593Smuzhiyun snd_nm256_capture_stop(chip);
610*4882a593Smuzhiyun s->running = 0;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun break;
613*4882a593Smuzhiyun default:
614*4882a593Smuzhiyun err = -EINVAL;
615*4882a593Smuzhiyun break;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
618*4882a593Smuzhiyun return err;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun /*
623*4882a593Smuzhiyun * prepare playback/capture channel
624*4882a593Smuzhiyun */
snd_nm256_pcm_prepare(struct snd_pcm_substream * substream)625*4882a593Smuzhiyun static int snd_nm256_pcm_prepare(struct snd_pcm_substream *substream)
626*4882a593Smuzhiyun {
627*4882a593Smuzhiyun struct nm256 *chip = snd_pcm_substream_chip(substream);
628*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
629*4882a593Smuzhiyun struct nm256_stream *s = runtime->private_data;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun if (snd_BUG_ON(!s))
632*4882a593Smuzhiyun return -ENXIO;
633*4882a593Smuzhiyun s->dma_size = frames_to_bytes(runtime, substream->runtime->buffer_size);
634*4882a593Smuzhiyun s->period_size = frames_to_bytes(runtime, substream->runtime->period_size);
635*4882a593Smuzhiyun s->periods = substream->runtime->periods;
636*4882a593Smuzhiyun s->cur_period = 0;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun spin_lock_irq(&chip->reg_lock);
639*4882a593Smuzhiyun s->running = 0;
640*4882a593Smuzhiyun snd_nm256_set_format(chip, s, substream);
641*4882a593Smuzhiyun spin_unlock_irq(&chip->reg_lock);
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun return 0;
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /*
648*4882a593Smuzhiyun * get the current pointer
649*4882a593Smuzhiyun */
650*4882a593Smuzhiyun static snd_pcm_uframes_t
snd_nm256_playback_pointer(struct snd_pcm_substream * substream)651*4882a593Smuzhiyun snd_nm256_playback_pointer(struct snd_pcm_substream *substream)
652*4882a593Smuzhiyun {
653*4882a593Smuzhiyun struct nm256 *chip = snd_pcm_substream_chip(substream);
654*4882a593Smuzhiyun struct nm256_stream *s = substream->runtime->private_data;
655*4882a593Smuzhiyun unsigned long curp;
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun if (snd_BUG_ON(!s))
658*4882a593Smuzhiyun return 0;
659*4882a593Smuzhiyun curp = snd_nm256_readl(chip, NM_PBUFFER_CURRP) - (unsigned long)s->buf;
660*4882a593Smuzhiyun curp %= s->dma_size;
661*4882a593Smuzhiyun return bytes_to_frames(substream->runtime, curp);
662*4882a593Smuzhiyun }
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun static snd_pcm_uframes_t
snd_nm256_capture_pointer(struct snd_pcm_substream * substream)665*4882a593Smuzhiyun snd_nm256_capture_pointer(struct snd_pcm_substream *substream)
666*4882a593Smuzhiyun {
667*4882a593Smuzhiyun struct nm256 *chip = snd_pcm_substream_chip(substream);
668*4882a593Smuzhiyun struct nm256_stream *s = substream->runtime->private_data;
669*4882a593Smuzhiyun unsigned long curp;
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun if (snd_BUG_ON(!s))
672*4882a593Smuzhiyun return 0;
673*4882a593Smuzhiyun curp = snd_nm256_readl(chip, NM_RBUFFER_CURRP) - (unsigned long)s->buf;
674*4882a593Smuzhiyun curp %= s->dma_size;
675*4882a593Smuzhiyun return bytes_to_frames(substream->runtime, curp);
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun /* Remapped I/O space can be accessible as pointer on i386 */
679*4882a593Smuzhiyun /* This might be changed in the future */
680*4882a593Smuzhiyun #ifndef __i386__
681*4882a593Smuzhiyun /*
682*4882a593Smuzhiyun * silence / copy for playback
683*4882a593Smuzhiyun */
684*4882a593Smuzhiyun static int
snd_nm256_playback_silence(struct snd_pcm_substream * substream,int channel,unsigned long pos,unsigned long count)685*4882a593Smuzhiyun snd_nm256_playback_silence(struct snd_pcm_substream *substream,
686*4882a593Smuzhiyun int channel, unsigned long pos, unsigned long count)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
689*4882a593Smuzhiyun struct nm256_stream *s = runtime->private_data;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun memset_io(s->bufptr + pos, 0, count);
692*4882a593Smuzhiyun return 0;
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun static int
snd_nm256_playback_copy(struct snd_pcm_substream * substream,int channel,unsigned long pos,void __user * src,unsigned long count)696*4882a593Smuzhiyun snd_nm256_playback_copy(struct snd_pcm_substream *substream,
697*4882a593Smuzhiyun int channel, unsigned long pos,
698*4882a593Smuzhiyun void __user *src, unsigned long count)
699*4882a593Smuzhiyun {
700*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
701*4882a593Smuzhiyun struct nm256_stream *s = runtime->private_data;
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun if (copy_from_user_toio(s->bufptr + pos, src, count))
704*4882a593Smuzhiyun return -EFAULT;
705*4882a593Smuzhiyun return 0;
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun static int
snd_nm256_playback_copy_kernel(struct snd_pcm_substream * substream,int channel,unsigned long pos,void * src,unsigned long count)709*4882a593Smuzhiyun snd_nm256_playback_copy_kernel(struct snd_pcm_substream *substream,
710*4882a593Smuzhiyun int channel, unsigned long pos,
711*4882a593Smuzhiyun void *src, unsigned long count)
712*4882a593Smuzhiyun {
713*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
714*4882a593Smuzhiyun struct nm256_stream *s = runtime->private_data;
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun memcpy_toio(s->bufptr + pos, src, count);
717*4882a593Smuzhiyun return 0;
718*4882a593Smuzhiyun }
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun /*
721*4882a593Smuzhiyun * copy to user
722*4882a593Smuzhiyun */
723*4882a593Smuzhiyun static int
snd_nm256_capture_copy(struct snd_pcm_substream * substream,int channel,unsigned long pos,void __user * dst,unsigned long count)724*4882a593Smuzhiyun snd_nm256_capture_copy(struct snd_pcm_substream *substream,
725*4882a593Smuzhiyun int channel, unsigned long pos,
726*4882a593Smuzhiyun void __user *dst, unsigned long count)
727*4882a593Smuzhiyun {
728*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
729*4882a593Smuzhiyun struct nm256_stream *s = runtime->private_data;
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun if (copy_to_user_fromio(dst, s->bufptr + pos, count))
732*4882a593Smuzhiyun return -EFAULT;
733*4882a593Smuzhiyun return 0;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun static int
snd_nm256_capture_copy_kernel(struct snd_pcm_substream * substream,int channel,unsigned long pos,void * dst,unsigned long count)737*4882a593Smuzhiyun snd_nm256_capture_copy_kernel(struct snd_pcm_substream *substream,
738*4882a593Smuzhiyun int channel, unsigned long pos,
739*4882a593Smuzhiyun void *dst, unsigned long count)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
742*4882a593Smuzhiyun struct nm256_stream *s = runtime->private_data;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun memcpy_fromio(dst, s->bufptr + pos, count);
745*4882a593Smuzhiyun return 0;
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun #endif /* !__i386__ */
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun /*
752*4882a593Smuzhiyun * update playback/capture watermarks
753*4882a593Smuzhiyun */
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun /* spinlock held! */
756*4882a593Smuzhiyun static void
snd_nm256_playback_update(struct nm256 * chip)757*4882a593Smuzhiyun snd_nm256_playback_update(struct nm256 *chip)
758*4882a593Smuzhiyun {
759*4882a593Smuzhiyun struct nm256_stream *s;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun s = &chip->streams[SNDRV_PCM_STREAM_PLAYBACK];
762*4882a593Smuzhiyun if (s->running && s->substream) {
763*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
764*4882a593Smuzhiyun snd_pcm_period_elapsed(s->substream);
765*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
766*4882a593Smuzhiyun snd_nm256_playback_mark(chip, s);
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun /* spinlock held! */
771*4882a593Smuzhiyun static void
snd_nm256_capture_update(struct nm256 * chip)772*4882a593Smuzhiyun snd_nm256_capture_update(struct nm256 *chip)
773*4882a593Smuzhiyun {
774*4882a593Smuzhiyun struct nm256_stream *s;
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun s = &chip->streams[SNDRV_PCM_STREAM_CAPTURE];
777*4882a593Smuzhiyun if (s->running && s->substream) {
778*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
779*4882a593Smuzhiyun snd_pcm_period_elapsed(s->substream);
780*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
781*4882a593Smuzhiyun snd_nm256_capture_mark(chip, s);
782*4882a593Smuzhiyun }
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun /*
786*4882a593Smuzhiyun * hardware info
787*4882a593Smuzhiyun */
788*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_nm256_playback =
789*4882a593Smuzhiyun {
790*4882a593Smuzhiyun .info = SNDRV_PCM_INFO_MMAP_IOMEM |SNDRV_PCM_INFO_MMAP_VALID |
791*4882a593Smuzhiyun SNDRV_PCM_INFO_INTERLEAVED |
792*4882a593Smuzhiyun /*SNDRV_PCM_INFO_PAUSE |*/
793*4882a593Smuzhiyun SNDRV_PCM_INFO_RESUME,
794*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
795*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
796*4882a593Smuzhiyun .rate_min = 8000,
797*4882a593Smuzhiyun .rate_max = 48000,
798*4882a593Smuzhiyun .channels_min = 1,
799*4882a593Smuzhiyun .channels_max = 2,
800*4882a593Smuzhiyun .periods_min = 2,
801*4882a593Smuzhiyun .periods_max = 1024,
802*4882a593Smuzhiyun .buffer_bytes_max = 128 * 1024,
803*4882a593Smuzhiyun .period_bytes_min = 256,
804*4882a593Smuzhiyun .period_bytes_max = 128 * 1024,
805*4882a593Smuzhiyun };
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_nm256_capture =
808*4882a593Smuzhiyun {
809*4882a593Smuzhiyun .info = SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID |
810*4882a593Smuzhiyun SNDRV_PCM_INFO_INTERLEAVED |
811*4882a593Smuzhiyun /*SNDRV_PCM_INFO_PAUSE |*/
812*4882a593Smuzhiyun SNDRV_PCM_INFO_RESUME,
813*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
814*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
815*4882a593Smuzhiyun .rate_min = 8000,
816*4882a593Smuzhiyun .rate_max = 48000,
817*4882a593Smuzhiyun .channels_min = 1,
818*4882a593Smuzhiyun .channels_max = 2,
819*4882a593Smuzhiyun .periods_min = 2,
820*4882a593Smuzhiyun .periods_max = 1024,
821*4882a593Smuzhiyun .buffer_bytes_max = 128 * 1024,
822*4882a593Smuzhiyun .period_bytes_min = 256,
823*4882a593Smuzhiyun .period_bytes_max = 128 * 1024,
824*4882a593Smuzhiyun };
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun /* set dma transfer size */
snd_nm256_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)828*4882a593Smuzhiyun static int snd_nm256_pcm_hw_params(struct snd_pcm_substream *substream,
829*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params)
830*4882a593Smuzhiyun {
831*4882a593Smuzhiyun /* area and addr are already set and unchanged */
832*4882a593Smuzhiyun substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
833*4882a593Smuzhiyun return 0;
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun /*
837*4882a593Smuzhiyun * open
838*4882a593Smuzhiyun */
snd_nm256_setup_stream(struct nm256 * chip,struct nm256_stream * s,struct snd_pcm_substream * substream,const struct snd_pcm_hardware * hw_ptr)839*4882a593Smuzhiyun static void snd_nm256_setup_stream(struct nm256 *chip, struct nm256_stream *s,
840*4882a593Smuzhiyun struct snd_pcm_substream *substream,
841*4882a593Smuzhiyun const struct snd_pcm_hardware *hw_ptr)
842*4882a593Smuzhiyun {
843*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun s->running = 0;
846*4882a593Smuzhiyun runtime->hw = *hw_ptr;
847*4882a593Smuzhiyun runtime->hw.buffer_bytes_max = s->bufsize;
848*4882a593Smuzhiyun runtime->hw.period_bytes_max = s->bufsize / 2;
849*4882a593Smuzhiyun runtime->dma_area = (void __force *) s->bufptr;
850*4882a593Smuzhiyun runtime->dma_addr = s->bufptr_addr;
851*4882a593Smuzhiyun runtime->dma_bytes = s->bufsize;
852*4882a593Smuzhiyun runtime->private_data = s;
853*4882a593Smuzhiyun s->substream = substream;
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
856*4882a593Smuzhiyun &constraints_rates);
857*4882a593Smuzhiyun }
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun static int
snd_nm256_playback_open(struct snd_pcm_substream * substream)860*4882a593Smuzhiyun snd_nm256_playback_open(struct snd_pcm_substream *substream)
861*4882a593Smuzhiyun {
862*4882a593Smuzhiyun struct nm256 *chip = snd_pcm_substream_chip(substream);
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun if (snd_nm256_acquire_irq(chip) < 0)
865*4882a593Smuzhiyun return -EBUSY;
866*4882a593Smuzhiyun snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_PLAYBACK],
867*4882a593Smuzhiyun substream, &snd_nm256_playback);
868*4882a593Smuzhiyun return 0;
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun static int
snd_nm256_capture_open(struct snd_pcm_substream * substream)872*4882a593Smuzhiyun snd_nm256_capture_open(struct snd_pcm_substream *substream)
873*4882a593Smuzhiyun {
874*4882a593Smuzhiyun struct nm256 *chip = snd_pcm_substream_chip(substream);
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun if (snd_nm256_acquire_irq(chip) < 0)
877*4882a593Smuzhiyun return -EBUSY;
878*4882a593Smuzhiyun snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_CAPTURE],
879*4882a593Smuzhiyun substream, &snd_nm256_capture);
880*4882a593Smuzhiyun return 0;
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun /*
884*4882a593Smuzhiyun * close - we don't have to do special..
885*4882a593Smuzhiyun */
886*4882a593Smuzhiyun static int
snd_nm256_playback_close(struct snd_pcm_substream * substream)887*4882a593Smuzhiyun snd_nm256_playback_close(struct snd_pcm_substream *substream)
888*4882a593Smuzhiyun {
889*4882a593Smuzhiyun struct nm256 *chip = snd_pcm_substream_chip(substream);
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun snd_nm256_release_irq(chip);
892*4882a593Smuzhiyun return 0;
893*4882a593Smuzhiyun }
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun static int
snd_nm256_capture_close(struct snd_pcm_substream * substream)897*4882a593Smuzhiyun snd_nm256_capture_close(struct snd_pcm_substream *substream)
898*4882a593Smuzhiyun {
899*4882a593Smuzhiyun struct nm256 *chip = snd_pcm_substream_chip(substream);
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun snd_nm256_release_irq(chip);
902*4882a593Smuzhiyun return 0;
903*4882a593Smuzhiyun }
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun /*
906*4882a593Smuzhiyun * create a pcm instance
907*4882a593Smuzhiyun */
908*4882a593Smuzhiyun static const struct snd_pcm_ops snd_nm256_playback_ops = {
909*4882a593Smuzhiyun .open = snd_nm256_playback_open,
910*4882a593Smuzhiyun .close = snd_nm256_playback_close,
911*4882a593Smuzhiyun .hw_params = snd_nm256_pcm_hw_params,
912*4882a593Smuzhiyun .prepare = snd_nm256_pcm_prepare,
913*4882a593Smuzhiyun .trigger = snd_nm256_playback_trigger,
914*4882a593Smuzhiyun .pointer = snd_nm256_playback_pointer,
915*4882a593Smuzhiyun #ifndef __i386__
916*4882a593Smuzhiyun .copy_user = snd_nm256_playback_copy,
917*4882a593Smuzhiyun .copy_kernel = snd_nm256_playback_copy_kernel,
918*4882a593Smuzhiyun .fill_silence = snd_nm256_playback_silence,
919*4882a593Smuzhiyun #endif
920*4882a593Smuzhiyun .mmap = snd_pcm_lib_mmap_iomem,
921*4882a593Smuzhiyun };
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun static const struct snd_pcm_ops snd_nm256_capture_ops = {
924*4882a593Smuzhiyun .open = snd_nm256_capture_open,
925*4882a593Smuzhiyun .close = snd_nm256_capture_close,
926*4882a593Smuzhiyun .hw_params = snd_nm256_pcm_hw_params,
927*4882a593Smuzhiyun .prepare = snd_nm256_pcm_prepare,
928*4882a593Smuzhiyun .trigger = snd_nm256_capture_trigger,
929*4882a593Smuzhiyun .pointer = snd_nm256_capture_pointer,
930*4882a593Smuzhiyun #ifndef __i386__
931*4882a593Smuzhiyun .copy_user = snd_nm256_capture_copy,
932*4882a593Smuzhiyun .copy_kernel = snd_nm256_capture_copy_kernel,
933*4882a593Smuzhiyun #endif
934*4882a593Smuzhiyun .mmap = snd_pcm_lib_mmap_iomem,
935*4882a593Smuzhiyun };
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun static int
snd_nm256_pcm(struct nm256 * chip,int device)938*4882a593Smuzhiyun snd_nm256_pcm(struct nm256 *chip, int device)
939*4882a593Smuzhiyun {
940*4882a593Smuzhiyun struct snd_pcm *pcm;
941*4882a593Smuzhiyun int i, err;
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
944*4882a593Smuzhiyun struct nm256_stream *s = &chip->streams[i];
945*4882a593Smuzhiyun s->bufptr = chip->buffer + (s->buf - chip->buffer_start);
946*4882a593Smuzhiyun s->bufptr_addr = chip->buffer_addr + (s->buf - chip->buffer_start);
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun err = snd_pcm_new(chip->card, chip->card->driver, device,
950*4882a593Smuzhiyun 1, 1, &pcm);
951*4882a593Smuzhiyun if (err < 0)
952*4882a593Smuzhiyun return err;
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_nm256_playback_ops);
955*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_nm256_capture_ops);
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun pcm->private_data = chip;
958*4882a593Smuzhiyun pcm->info_flags = 0;
959*4882a593Smuzhiyun chip->pcm = pcm;
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun return 0;
962*4882a593Smuzhiyun }
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun /*
966*4882a593Smuzhiyun * Initialize the hardware.
967*4882a593Smuzhiyun */
968*4882a593Smuzhiyun static void
snd_nm256_init_chip(struct nm256 * chip)969*4882a593Smuzhiyun snd_nm256_init_chip(struct nm256 *chip)
970*4882a593Smuzhiyun {
971*4882a593Smuzhiyun /* Reset everything. */
972*4882a593Smuzhiyun snd_nm256_writeb(chip, 0x0, 0x11);
973*4882a593Smuzhiyun snd_nm256_writew(chip, 0x214, 0);
974*4882a593Smuzhiyun /* stop sounds.. */
975*4882a593Smuzhiyun //snd_nm256_playback_stop(chip);
976*4882a593Smuzhiyun //snd_nm256_capture_stop(chip);
977*4882a593Smuzhiyun }
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun static irqreturn_t
snd_nm256_intr_check(struct nm256 * chip)981*4882a593Smuzhiyun snd_nm256_intr_check(struct nm256 *chip)
982*4882a593Smuzhiyun {
983*4882a593Smuzhiyun if (chip->badintrcount++ > 1000) {
984*4882a593Smuzhiyun /*
985*4882a593Smuzhiyun * I'm not sure if the best thing is to stop the card from
986*4882a593Smuzhiyun * playing or just release the interrupt (after all, we're in
987*4882a593Smuzhiyun * a bad situation, so doing fancy stuff may not be such a good
988*4882a593Smuzhiyun * idea).
989*4882a593Smuzhiyun *
990*4882a593Smuzhiyun * I worry about the card engine continuing to play noise
991*4882a593Smuzhiyun * over and over, however--that could become a very
992*4882a593Smuzhiyun * obnoxious problem. And we know that when this usually
993*4882a593Smuzhiyun * happens things are fairly safe, it just means the user's
994*4882a593Smuzhiyun * inserted a PCMCIA card and someone's spamming us with IRQ 9s.
995*4882a593Smuzhiyun */
996*4882a593Smuzhiyun if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
997*4882a593Smuzhiyun snd_nm256_playback_stop(chip);
998*4882a593Smuzhiyun if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
999*4882a593Smuzhiyun snd_nm256_capture_stop(chip);
1000*4882a593Smuzhiyun chip->badintrcount = 0;
1001*4882a593Smuzhiyun return IRQ_HANDLED;
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun return IRQ_NONE;
1004*4882a593Smuzhiyun }
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun /*
1007*4882a593Smuzhiyun * Handle a potential interrupt for the device referred to by DEV_ID.
1008*4882a593Smuzhiyun *
1009*4882a593Smuzhiyun * I don't like the cut-n-paste job here either between the two routines,
1010*4882a593Smuzhiyun * but there are sufficient differences between the two interrupt handlers
1011*4882a593Smuzhiyun * that parameterizing it isn't all that great either. (Could use a macro,
1012*4882a593Smuzhiyun * I suppose...yucky bleah.)
1013*4882a593Smuzhiyun */
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun static irqreturn_t
snd_nm256_interrupt(int irq,void * dev_id)1016*4882a593Smuzhiyun snd_nm256_interrupt(int irq, void *dev_id)
1017*4882a593Smuzhiyun {
1018*4882a593Smuzhiyun struct nm256 *chip = dev_id;
1019*4882a593Smuzhiyun u16 status;
1020*4882a593Smuzhiyun u8 cbyte;
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun status = snd_nm256_readw(chip, NM_INT_REG);
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun /* Not ours. */
1025*4882a593Smuzhiyun if (status == 0)
1026*4882a593Smuzhiyun return snd_nm256_intr_check(chip);
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun chip->badintrcount = 0;
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun /* Rather boring; check for individual interrupts and process them. */
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
1033*4882a593Smuzhiyun if (status & NM_PLAYBACK_INT) {
1034*4882a593Smuzhiyun status &= ~NM_PLAYBACK_INT;
1035*4882a593Smuzhiyun NM_ACK_INT(chip, NM_PLAYBACK_INT);
1036*4882a593Smuzhiyun snd_nm256_playback_update(chip);
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun if (status & NM_RECORD_INT) {
1040*4882a593Smuzhiyun status &= ~NM_RECORD_INT;
1041*4882a593Smuzhiyun NM_ACK_INT(chip, NM_RECORD_INT);
1042*4882a593Smuzhiyun snd_nm256_capture_update(chip);
1043*4882a593Smuzhiyun }
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun if (status & NM_MISC_INT_1) {
1046*4882a593Smuzhiyun status &= ~NM_MISC_INT_1;
1047*4882a593Smuzhiyun NM_ACK_INT(chip, NM_MISC_INT_1);
1048*4882a593Smuzhiyun dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
1049*4882a593Smuzhiyun snd_nm256_writew(chip, NM_INT_REG, 0x8000);
1050*4882a593Smuzhiyun cbyte = snd_nm256_readb(chip, 0x400);
1051*4882a593Smuzhiyun snd_nm256_writeb(chip, 0x400, cbyte | 2);
1052*4882a593Smuzhiyun }
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun if (status & NM_MISC_INT_2) {
1055*4882a593Smuzhiyun status &= ~NM_MISC_INT_2;
1056*4882a593Smuzhiyun NM_ACK_INT(chip, NM_MISC_INT_2);
1057*4882a593Smuzhiyun dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
1058*4882a593Smuzhiyun cbyte = snd_nm256_readb(chip, 0x400);
1059*4882a593Smuzhiyun snd_nm256_writeb(chip, 0x400, cbyte & ~2);
1060*4882a593Smuzhiyun }
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun /* Unknown interrupt. */
1063*4882a593Smuzhiyun if (status) {
1064*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1065*4882a593Smuzhiyun "NM256: Fire in the hole! Unknown status 0x%x\n",
1066*4882a593Smuzhiyun status);
1067*4882a593Smuzhiyun /* Pray. */
1068*4882a593Smuzhiyun NM_ACK_INT(chip, status);
1069*4882a593Smuzhiyun }
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
1072*4882a593Smuzhiyun return IRQ_HANDLED;
1073*4882a593Smuzhiyun }
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun /*
1076*4882a593Smuzhiyun * Handle a potential interrupt for the device referred to by DEV_ID.
1077*4882a593Smuzhiyun * This handler is for the 256ZX, and is very similar to the non-ZX
1078*4882a593Smuzhiyun * routine.
1079*4882a593Smuzhiyun */
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun static irqreturn_t
snd_nm256_interrupt_zx(int irq,void * dev_id)1082*4882a593Smuzhiyun snd_nm256_interrupt_zx(int irq, void *dev_id)
1083*4882a593Smuzhiyun {
1084*4882a593Smuzhiyun struct nm256 *chip = dev_id;
1085*4882a593Smuzhiyun u32 status;
1086*4882a593Smuzhiyun u8 cbyte;
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun status = snd_nm256_readl(chip, NM_INT_REG);
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun /* Not ours. */
1091*4882a593Smuzhiyun if (status == 0)
1092*4882a593Smuzhiyun return snd_nm256_intr_check(chip);
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun chip->badintrcount = 0;
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun /* Rather boring; check for individual interrupts and process them. */
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
1099*4882a593Smuzhiyun if (status & NM2_PLAYBACK_INT) {
1100*4882a593Smuzhiyun status &= ~NM2_PLAYBACK_INT;
1101*4882a593Smuzhiyun NM2_ACK_INT(chip, NM2_PLAYBACK_INT);
1102*4882a593Smuzhiyun snd_nm256_playback_update(chip);
1103*4882a593Smuzhiyun }
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun if (status & NM2_RECORD_INT) {
1106*4882a593Smuzhiyun status &= ~NM2_RECORD_INT;
1107*4882a593Smuzhiyun NM2_ACK_INT(chip, NM2_RECORD_INT);
1108*4882a593Smuzhiyun snd_nm256_capture_update(chip);
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun if (status & NM2_MISC_INT_1) {
1112*4882a593Smuzhiyun status &= ~NM2_MISC_INT_1;
1113*4882a593Smuzhiyun NM2_ACK_INT(chip, NM2_MISC_INT_1);
1114*4882a593Smuzhiyun dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
1115*4882a593Smuzhiyun cbyte = snd_nm256_readb(chip, 0x400);
1116*4882a593Smuzhiyun snd_nm256_writeb(chip, 0x400, cbyte | 2);
1117*4882a593Smuzhiyun }
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun if (status & NM2_MISC_INT_2) {
1120*4882a593Smuzhiyun status &= ~NM2_MISC_INT_2;
1121*4882a593Smuzhiyun NM2_ACK_INT(chip, NM2_MISC_INT_2);
1122*4882a593Smuzhiyun dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
1123*4882a593Smuzhiyun cbyte = snd_nm256_readb(chip, 0x400);
1124*4882a593Smuzhiyun snd_nm256_writeb(chip, 0x400, cbyte & ~2);
1125*4882a593Smuzhiyun }
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun /* Unknown interrupt. */
1128*4882a593Smuzhiyun if (status) {
1129*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1130*4882a593Smuzhiyun "NM256: Fire in the hole! Unknown status 0x%x\n",
1131*4882a593Smuzhiyun status);
1132*4882a593Smuzhiyun /* Pray. */
1133*4882a593Smuzhiyun NM2_ACK_INT(chip, status);
1134*4882a593Smuzhiyun }
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
1137*4882a593Smuzhiyun return IRQ_HANDLED;
1138*4882a593Smuzhiyun }
1139*4882a593Smuzhiyun
1140*4882a593Smuzhiyun /*
1141*4882a593Smuzhiyun * AC97 interface
1142*4882a593Smuzhiyun */
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun /*
1145*4882a593Smuzhiyun * Waits for the mixer to become ready to be written; returns a zero value
1146*4882a593Smuzhiyun * if it timed out.
1147*4882a593Smuzhiyun */
1148*4882a593Smuzhiyun static int
snd_nm256_ac97_ready(struct nm256 * chip)1149*4882a593Smuzhiyun snd_nm256_ac97_ready(struct nm256 *chip)
1150*4882a593Smuzhiyun {
1151*4882a593Smuzhiyun int timeout = 10;
1152*4882a593Smuzhiyun u32 testaddr;
1153*4882a593Smuzhiyun u16 testb;
1154*4882a593Smuzhiyun
1155*4882a593Smuzhiyun testaddr = chip->mixer_status_offset;
1156*4882a593Smuzhiyun testb = chip->mixer_status_mask;
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun /*
1159*4882a593Smuzhiyun * Loop around waiting for the mixer to become ready.
1160*4882a593Smuzhiyun */
1161*4882a593Smuzhiyun while (timeout-- > 0) {
1162*4882a593Smuzhiyun if ((snd_nm256_readw(chip, testaddr) & testb) == 0)
1163*4882a593Smuzhiyun return 1;
1164*4882a593Smuzhiyun udelay(100);
1165*4882a593Smuzhiyun }
1166*4882a593Smuzhiyun return 0;
1167*4882a593Smuzhiyun }
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun /*
1170*4882a593Smuzhiyun * Initial register values to be written to the AC97 mixer.
1171*4882a593Smuzhiyun * While most of these are identical to the reset values, we do this
1172*4882a593Smuzhiyun * so that we have most of the register contents cached--this avoids
1173*4882a593Smuzhiyun * reading from the mixer directly (which seems to be problematic,
1174*4882a593Smuzhiyun * probably due to ignorance).
1175*4882a593Smuzhiyun */
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun struct initialValues {
1178*4882a593Smuzhiyun unsigned short reg;
1179*4882a593Smuzhiyun unsigned short value;
1180*4882a593Smuzhiyun };
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun static const struct initialValues nm256_ac97_init_val[] =
1183*4882a593Smuzhiyun {
1184*4882a593Smuzhiyun { AC97_MASTER, 0x8000 },
1185*4882a593Smuzhiyun { AC97_HEADPHONE, 0x8000 },
1186*4882a593Smuzhiyun { AC97_MASTER_MONO, 0x8000 },
1187*4882a593Smuzhiyun { AC97_PC_BEEP, 0x8000 },
1188*4882a593Smuzhiyun { AC97_PHONE, 0x8008 },
1189*4882a593Smuzhiyun { AC97_MIC, 0x8000 },
1190*4882a593Smuzhiyun { AC97_LINE, 0x8808 },
1191*4882a593Smuzhiyun { AC97_CD, 0x8808 },
1192*4882a593Smuzhiyun { AC97_VIDEO, 0x8808 },
1193*4882a593Smuzhiyun { AC97_AUX, 0x8808 },
1194*4882a593Smuzhiyun { AC97_PCM, 0x8808 },
1195*4882a593Smuzhiyun { AC97_REC_SEL, 0x0000 },
1196*4882a593Smuzhiyun { AC97_REC_GAIN, 0x0B0B },
1197*4882a593Smuzhiyun { AC97_GENERAL_PURPOSE, 0x0000 },
1198*4882a593Smuzhiyun { AC97_3D_CONTROL, 0x8000 },
1199*4882a593Smuzhiyun { AC97_VENDOR_ID1, 0x8384 },
1200*4882a593Smuzhiyun { AC97_VENDOR_ID2, 0x7609 },
1201*4882a593Smuzhiyun };
1202*4882a593Smuzhiyun
nm256_ac97_idx(unsigned short reg)1203*4882a593Smuzhiyun static int nm256_ac97_idx(unsigned short reg)
1204*4882a593Smuzhiyun {
1205*4882a593Smuzhiyun int i;
1206*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++)
1207*4882a593Smuzhiyun if (nm256_ac97_init_val[i].reg == reg)
1208*4882a593Smuzhiyun return i;
1209*4882a593Smuzhiyun return -1;
1210*4882a593Smuzhiyun }
1211*4882a593Smuzhiyun
1212*4882a593Smuzhiyun /*
1213*4882a593Smuzhiyun * some nm256 easily crash when reading from mixer registers
1214*4882a593Smuzhiyun * thus we're treating it as a write-only mixer and cache the
1215*4882a593Smuzhiyun * written values
1216*4882a593Smuzhiyun */
1217*4882a593Smuzhiyun static unsigned short
snd_nm256_ac97_read(struct snd_ac97 * ac97,unsigned short reg)1218*4882a593Smuzhiyun snd_nm256_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1219*4882a593Smuzhiyun {
1220*4882a593Smuzhiyun struct nm256 *chip = ac97->private_data;
1221*4882a593Smuzhiyun int idx = nm256_ac97_idx(reg);
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun if (idx < 0)
1224*4882a593Smuzhiyun return 0;
1225*4882a593Smuzhiyun return chip->ac97_regs[idx];
1226*4882a593Smuzhiyun }
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun /*
1229*4882a593Smuzhiyun */
1230*4882a593Smuzhiyun static void
snd_nm256_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)1231*4882a593Smuzhiyun snd_nm256_ac97_write(struct snd_ac97 *ac97,
1232*4882a593Smuzhiyun unsigned short reg, unsigned short val)
1233*4882a593Smuzhiyun {
1234*4882a593Smuzhiyun struct nm256 *chip = ac97->private_data;
1235*4882a593Smuzhiyun int tries = 2;
1236*4882a593Smuzhiyun int idx = nm256_ac97_idx(reg);
1237*4882a593Smuzhiyun u32 base;
1238*4882a593Smuzhiyun
1239*4882a593Smuzhiyun if (idx < 0)
1240*4882a593Smuzhiyun return;
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun base = chip->mixer_base;
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun snd_nm256_ac97_ready(chip);
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun /* Wait for the write to take, too. */
1247*4882a593Smuzhiyun while (tries-- > 0) {
1248*4882a593Smuzhiyun snd_nm256_writew(chip, base + reg, val);
1249*4882a593Smuzhiyun msleep(1); /* a little delay here seems better.. */
1250*4882a593Smuzhiyun if (snd_nm256_ac97_ready(chip)) {
1251*4882a593Smuzhiyun /* successful write: set cache */
1252*4882a593Smuzhiyun chip->ac97_regs[idx] = val;
1253*4882a593Smuzhiyun return;
1254*4882a593Smuzhiyun }
1255*4882a593Smuzhiyun }
1256*4882a593Smuzhiyun dev_dbg(chip->card->dev, "nm256: ac97 codec not ready..\n");
1257*4882a593Smuzhiyun }
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun /* static resolution table */
1260*4882a593Smuzhiyun static const struct snd_ac97_res_table nm256_res_table[] = {
1261*4882a593Smuzhiyun { AC97_MASTER, 0x1f1f },
1262*4882a593Smuzhiyun { AC97_HEADPHONE, 0x1f1f },
1263*4882a593Smuzhiyun { AC97_MASTER_MONO, 0x001f },
1264*4882a593Smuzhiyun { AC97_PC_BEEP, 0x001f },
1265*4882a593Smuzhiyun { AC97_PHONE, 0x001f },
1266*4882a593Smuzhiyun { AC97_MIC, 0x001f },
1267*4882a593Smuzhiyun { AC97_LINE, 0x1f1f },
1268*4882a593Smuzhiyun { AC97_CD, 0x1f1f },
1269*4882a593Smuzhiyun { AC97_VIDEO, 0x1f1f },
1270*4882a593Smuzhiyun { AC97_AUX, 0x1f1f },
1271*4882a593Smuzhiyun { AC97_PCM, 0x1f1f },
1272*4882a593Smuzhiyun { AC97_REC_GAIN, 0x0f0f },
1273*4882a593Smuzhiyun { } /* terminator */
1274*4882a593Smuzhiyun };
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun /* initialize the ac97 into a known state */
1277*4882a593Smuzhiyun static void
snd_nm256_ac97_reset(struct snd_ac97 * ac97)1278*4882a593Smuzhiyun snd_nm256_ac97_reset(struct snd_ac97 *ac97)
1279*4882a593Smuzhiyun {
1280*4882a593Smuzhiyun struct nm256 *chip = ac97->private_data;
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun /* Reset the mixer. 'Tis magic! */
1283*4882a593Smuzhiyun snd_nm256_writeb(chip, 0x6c0, 1);
1284*4882a593Smuzhiyun if (! chip->reset_workaround) {
1285*4882a593Smuzhiyun /* Dell latitude LS will lock up by this */
1286*4882a593Smuzhiyun snd_nm256_writeb(chip, 0x6cc, 0x87);
1287*4882a593Smuzhiyun }
1288*4882a593Smuzhiyun if (! chip->reset_workaround_2) {
1289*4882a593Smuzhiyun /* Dell latitude CSx will lock up by this */
1290*4882a593Smuzhiyun snd_nm256_writeb(chip, 0x6cc, 0x80);
1291*4882a593Smuzhiyun snd_nm256_writeb(chip, 0x6cc, 0x0);
1292*4882a593Smuzhiyun }
1293*4882a593Smuzhiyun if (! chip->in_resume) {
1294*4882a593Smuzhiyun int i;
1295*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++) {
1296*4882a593Smuzhiyun /* preload the cache, so as to avoid even a single
1297*4882a593Smuzhiyun * read of the mixer regs
1298*4882a593Smuzhiyun */
1299*4882a593Smuzhiyun snd_nm256_ac97_write(ac97, nm256_ac97_init_val[i].reg,
1300*4882a593Smuzhiyun nm256_ac97_init_val[i].value);
1301*4882a593Smuzhiyun }
1302*4882a593Smuzhiyun }
1303*4882a593Smuzhiyun }
1304*4882a593Smuzhiyun
1305*4882a593Smuzhiyun /* create an ac97 mixer interface */
1306*4882a593Smuzhiyun static int
snd_nm256_mixer(struct nm256 * chip)1307*4882a593Smuzhiyun snd_nm256_mixer(struct nm256 *chip)
1308*4882a593Smuzhiyun {
1309*4882a593Smuzhiyun struct snd_ac97_bus *pbus;
1310*4882a593Smuzhiyun struct snd_ac97_template ac97;
1311*4882a593Smuzhiyun int err;
1312*4882a593Smuzhiyun static const struct snd_ac97_bus_ops ops = {
1313*4882a593Smuzhiyun .reset = snd_nm256_ac97_reset,
1314*4882a593Smuzhiyun .write = snd_nm256_ac97_write,
1315*4882a593Smuzhiyun .read = snd_nm256_ac97_read,
1316*4882a593Smuzhiyun };
1317*4882a593Smuzhiyun
1318*4882a593Smuzhiyun chip->ac97_regs = kcalloc(ARRAY_SIZE(nm256_ac97_init_val),
1319*4882a593Smuzhiyun sizeof(short), GFP_KERNEL);
1320*4882a593Smuzhiyun if (! chip->ac97_regs)
1321*4882a593Smuzhiyun return -ENOMEM;
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
1324*4882a593Smuzhiyun return err;
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun memset(&ac97, 0, sizeof(ac97));
1327*4882a593Smuzhiyun ac97.scaps = AC97_SCAP_AUDIO; /* we support audio! */
1328*4882a593Smuzhiyun ac97.private_data = chip;
1329*4882a593Smuzhiyun ac97.res_table = nm256_res_table;
1330*4882a593Smuzhiyun pbus->no_vra = 1;
1331*4882a593Smuzhiyun err = snd_ac97_mixer(pbus, &ac97, &chip->ac97);
1332*4882a593Smuzhiyun if (err < 0)
1333*4882a593Smuzhiyun return err;
1334*4882a593Smuzhiyun if (! (chip->ac97->id & (0xf0000000))) {
1335*4882a593Smuzhiyun /* looks like an invalid id */
1336*4882a593Smuzhiyun sprintf(chip->card->mixername, "%s AC97", chip->card->driver);
1337*4882a593Smuzhiyun }
1338*4882a593Smuzhiyun return 0;
1339*4882a593Smuzhiyun }
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun /*
1342*4882a593Smuzhiyun * See if the signature left by the NM256 BIOS is intact; if so, we use
1343*4882a593Smuzhiyun * the associated address as the end of our audio buffer in the video
1344*4882a593Smuzhiyun * RAM.
1345*4882a593Smuzhiyun */
1346*4882a593Smuzhiyun
1347*4882a593Smuzhiyun static int
snd_nm256_peek_for_sig(struct nm256 * chip)1348*4882a593Smuzhiyun snd_nm256_peek_for_sig(struct nm256 *chip)
1349*4882a593Smuzhiyun {
1350*4882a593Smuzhiyun /* The signature is located 1K below the end of video RAM. */
1351*4882a593Smuzhiyun void __iomem *temp;
1352*4882a593Smuzhiyun /* Default buffer end is 5120 bytes below the top of RAM. */
1353*4882a593Smuzhiyun unsigned long pointer_found = chip->buffer_end - 0x1400;
1354*4882a593Smuzhiyun u32 sig;
1355*4882a593Smuzhiyun
1356*4882a593Smuzhiyun temp = ioremap(chip->buffer_addr + chip->buffer_end - 0x400, 16);
1357*4882a593Smuzhiyun if (temp == NULL) {
1358*4882a593Smuzhiyun dev_err(chip->card->dev,
1359*4882a593Smuzhiyun "Unable to scan for card signature in video RAM\n");
1360*4882a593Smuzhiyun return -EBUSY;
1361*4882a593Smuzhiyun }
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun sig = readl(temp);
1364*4882a593Smuzhiyun if ((sig & NM_SIG_MASK) == NM_SIGNATURE) {
1365*4882a593Smuzhiyun u32 pointer = readl(temp + 4);
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun /*
1368*4882a593Smuzhiyun * If it's obviously invalid, don't use it
1369*4882a593Smuzhiyun */
1370*4882a593Smuzhiyun if (pointer == 0xffffffff ||
1371*4882a593Smuzhiyun pointer < chip->buffer_size ||
1372*4882a593Smuzhiyun pointer > chip->buffer_end) {
1373*4882a593Smuzhiyun dev_err(chip->card->dev,
1374*4882a593Smuzhiyun "invalid signature found: 0x%x\n", pointer);
1375*4882a593Smuzhiyun iounmap(temp);
1376*4882a593Smuzhiyun return -ENODEV;
1377*4882a593Smuzhiyun } else {
1378*4882a593Smuzhiyun pointer_found = pointer;
1379*4882a593Smuzhiyun dev_info(chip->card->dev,
1380*4882a593Smuzhiyun "found card signature in video RAM: 0x%x\n",
1381*4882a593Smuzhiyun pointer);
1382*4882a593Smuzhiyun }
1383*4882a593Smuzhiyun }
1384*4882a593Smuzhiyun
1385*4882a593Smuzhiyun iounmap(temp);
1386*4882a593Smuzhiyun chip->buffer_end = pointer_found;
1387*4882a593Smuzhiyun
1388*4882a593Smuzhiyun return 0;
1389*4882a593Smuzhiyun }
1390*4882a593Smuzhiyun
1391*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
1392*4882a593Smuzhiyun /*
1393*4882a593Smuzhiyun * APM event handler, so the card is properly reinitialized after a power
1394*4882a593Smuzhiyun * event.
1395*4882a593Smuzhiyun */
nm256_suspend(struct device * dev)1396*4882a593Smuzhiyun static int nm256_suspend(struct device *dev)
1397*4882a593Smuzhiyun {
1398*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
1399*4882a593Smuzhiyun struct nm256 *chip = card->private_data;
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1402*4882a593Smuzhiyun snd_ac97_suspend(chip->ac97);
1403*4882a593Smuzhiyun chip->coeffs_current = 0;
1404*4882a593Smuzhiyun return 0;
1405*4882a593Smuzhiyun }
1406*4882a593Smuzhiyun
nm256_resume(struct device * dev)1407*4882a593Smuzhiyun static int nm256_resume(struct device *dev)
1408*4882a593Smuzhiyun {
1409*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
1410*4882a593Smuzhiyun struct nm256 *chip = card->private_data;
1411*4882a593Smuzhiyun int i;
1412*4882a593Smuzhiyun
1413*4882a593Smuzhiyun /* Perform a full reset on the hardware */
1414*4882a593Smuzhiyun chip->in_resume = 1;
1415*4882a593Smuzhiyun
1416*4882a593Smuzhiyun snd_nm256_init_chip(chip);
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun /* restore ac97 */
1419*4882a593Smuzhiyun snd_ac97_resume(chip->ac97);
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
1422*4882a593Smuzhiyun struct nm256_stream *s = &chip->streams[i];
1423*4882a593Smuzhiyun if (s->substream && s->suspended) {
1424*4882a593Smuzhiyun spin_lock_irq(&chip->reg_lock);
1425*4882a593Smuzhiyun snd_nm256_set_format(chip, s, s->substream);
1426*4882a593Smuzhiyun spin_unlock_irq(&chip->reg_lock);
1427*4882a593Smuzhiyun }
1428*4882a593Smuzhiyun }
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1431*4882a593Smuzhiyun chip->in_resume = 0;
1432*4882a593Smuzhiyun return 0;
1433*4882a593Smuzhiyun }
1434*4882a593Smuzhiyun
1435*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(nm256_pm, nm256_suspend, nm256_resume);
1436*4882a593Smuzhiyun #define NM256_PM_OPS &nm256_pm
1437*4882a593Smuzhiyun #else
1438*4882a593Smuzhiyun #define NM256_PM_OPS NULL
1439*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
1440*4882a593Smuzhiyun
snd_nm256_free(struct nm256 * chip)1441*4882a593Smuzhiyun static int snd_nm256_free(struct nm256 *chip)
1442*4882a593Smuzhiyun {
1443*4882a593Smuzhiyun if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
1444*4882a593Smuzhiyun snd_nm256_playback_stop(chip);
1445*4882a593Smuzhiyun if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
1446*4882a593Smuzhiyun snd_nm256_capture_stop(chip);
1447*4882a593Smuzhiyun
1448*4882a593Smuzhiyun if (chip->irq >= 0)
1449*4882a593Smuzhiyun free_irq(chip->irq, chip);
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun iounmap(chip->cport);
1452*4882a593Smuzhiyun iounmap(chip->buffer);
1453*4882a593Smuzhiyun release_and_free_resource(chip->res_cport);
1454*4882a593Smuzhiyun release_and_free_resource(chip->res_buffer);
1455*4882a593Smuzhiyun
1456*4882a593Smuzhiyun pci_disable_device(chip->pci);
1457*4882a593Smuzhiyun kfree(chip->ac97_regs);
1458*4882a593Smuzhiyun kfree(chip);
1459*4882a593Smuzhiyun return 0;
1460*4882a593Smuzhiyun }
1461*4882a593Smuzhiyun
snd_nm256_dev_free(struct snd_device * device)1462*4882a593Smuzhiyun static int snd_nm256_dev_free(struct snd_device *device)
1463*4882a593Smuzhiyun {
1464*4882a593Smuzhiyun struct nm256 *chip = device->device_data;
1465*4882a593Smuzhiyun return snd_nm256_free(chip);
1466*4882a593Smuzhiyun }
1467*4882a593Smuzhiyun
1468*4882a593Smuzhiyun static int
snd_nm256_create(struct snd_card * card,struct pci_dev * pci,struct nm256 ** chip_ret)1469*4882a593Smuzhiyun snd_nm256_create(struct snd_card *card, struct pci_dev *pci,
1470*4882a593Smuzhiyun struct nm256 **chip_ret)
1471*4882a593Smuzhiyun {
1472*4882a593Smuzhiyun struct nm256 *chip;
1473*4882a593Smuzhiyun int err, pval;
1474*4882a593Smuzhiyun static const struct snd_device_ops ops = {
1475*4882a593Smuzhiyun .dev_free = snd_nm256_dev_free,
1476*4882a593Smuzhiyun };
1477*4882a593Smuzhiyun u32 addr;
1478*4882a593Smuzhiyun
1479*4882a593Smuzhiyun *chip_ret = NULL;
1480*4882a593Smuzhiyun
1481*4882a593Smuzhiyun if ((err = pci_enable_device(pci)) < 0)
1482*4882a593Smuzhiyun return err;
1483*4882a593Smuzhiyun
1484*4882a593Smuzhiyun chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1485*4882a593Smuzhiyun if (chip == NULL) {
1486*4882a593Smuzhiyun pci_disable_device(pci);
1487*4882a593Smuzhiyun return -ENOMEM;
1488*4882a593Smuzhiyun }
1489*4882a593Smuzhiyun
1490*4882a593Smuzhiyun chip->card = card;
1491*4882a593Smuzhiyun chip->pci = pci;
1492*4882a593Smuzhiyun chip->use_cache = use_cache;
1493*4882a593Smuzhiyun spin_lock_init(&chip->reg_lock);
1494*4882a593Smuzhiyun chip->irq = -1;
1495*4882a593Smuzhiyun mutex_init(&chip->irq_mutex);
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun /* store buffer sizes in bytes */
1498*4882a593Smuzhiyun chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize = playback_bufsize * 1024;
1499*4882a593Smuzhiyun chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize = capture_bufsize * 1024;
1500*4882a593Smuzhiyun
1501*4882a593Smuzhiyun /*
1502*4882a593Smuzhiyun * The NM256 has two memory ports. The first port is nothing
1503*4882a593Smuzhiyun * more than a chunk of video RAM, which is used as the I/O ring
1504*4882a593Smuzhiyun * buffer. The second port has the actual juicy stuff (like the
1505*4882a593Smuzhiyun * mixer and the playback engine control registers).
1506*4882a593Smuzhiyun */
1507*4882a593Smuzhiyun
1508*4882a593Smuzhiyun chip->buffer_addr = pci_resource_start(pci, 0);
1509*4882a593Smuzhiyun chip->cport_addr = pci_resource_start(pci, 1);
1510*4882a593Smuzhiyun
1511*4882a593Smuzhiyun /* Init the memory port info. */
1512*4882a593Smuzhiyun /* remap control port (#2) */
1513*4882a593Smuzhiyun chip->res_cport = request_mem_region(chip->cport_addr, NM_PORT2_SIZE,
1514*4882a593Smuzhiyun card->driver);
1515*4882a593Smuzhiyun if (chip->res_cport == NULL) {
1516*4882a593Smuzhiyun dev_err(card->dev, "memory region 0x%lx (size 0x%x) busy\n",
1517*4882a593Smuzhiyun chip->cport_addr, NM_PORT2_SIZE);
1518*4882a593Smuzhiyun err = -EBUSY;
1519*4882a593Smuzhiyun goto __error;
1520*4882a593Smuzhiyun }
1521*4882a593Smuzhiyun chip->cport = ioremap(chip->cport_addr, NM_PORT2_SIZE);
1522*4882a593Smuzhiyun if (chip->cport == NULL) {
1523*4882a593Smuzhiyun dev_err(card->dev, "unable to map control port %lx\n",
1524*4882a593Smuzhiyun chip->cport_addr);
1525*4882a593Smuzhiyun err = -ENOMEM;
1526*4882a593Smuzhiyun goto __error;
1527*4882a593Smuzhiyun }
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun if (!strcmp(card->driver, "NM256AV")) {
1530*4882a593Smuzhiyun /* Ok, try to see if this is a non-AC97 version of the hardware. */
1531*4882a593Smuzhiyun pval = snd_nm256_readw(chip, NM_MIXER_PRESENCE);
1532*4882a593Smuzhiyun if ((pval & NM_PRESENCE_MASK) != NM_PRESENCE_VALUE) {
1533*4882a593Smuzhiyun if (! force_ac97) {
1534*4882a593Smuzhiyun dev_err(card->dev,
1535*4882a593Smuzhiyun "no ac97 is found!\n");
1536*4882a593Smuzhiyun dev_err(card->dev,
1537*4882a593Smuzhiyun "force the driver to load by passing in the module parameter\n");
1538*4882a593Smuzhiyun dev_err(card->dev,
1539*4882a593Smuzhiyun " force_ac97=1\n");
1540*4882a593Smuzhiyun dev_err(card->dev,
1541*4882a593Smuzhiyun "or try sb16, opl3sa2, or cs423x drivers instead.\n");
1542*4882a593Smuzhiyun err = -ENXIO;
1543*4882a593Smuzhiyun goto __error;
1544*4882a593Smuzhiyun }
1545*4882a593Smuzhiyun }
1546*4882a593Smuzhiyun chip->buffer_end = 2560 * 1024;
1547*4882a593Smuzhiyun chip->interrupt = snd_nm256_interrupt;
1548*4882a593Smuzhiyun chip->mixer_status_offset = NM_MIXER_STATUS_OFFSET;
1549*4882a593Smuzhiyun chip->mixer_status_mask = NM_MIXER_READY_MASK;
1550*4882a593Smuzhiyun } else {
1551*4882a593Smuzhiyun /* Not sure if there is any relevant detect for the ZX or not. */
1552*4882a593Smuzhiyun if (snd_nm256_readb(chip, 0xa0b) != 0)
1553*4882a593Smuzhiyun chip->buffer_end = 6144 * 1024;
1554*4882a593Smuzhiyun else
1555*4882a593Smuzhiyun chip->buffer_end = 4096 * 1024;
1556*4882a593Smuzhiyun
1557*4882a593Smuzhiyun chip->interrupt = snd_nm256_interrupt_zx;
1558*4882a593Smuzhiyun chip->mixer_status_offset = NM2_MIXER_STATUS_OFFSET;
1559*4882a593Smuzhiyun chip->mixer_status_mask = NM2_MIXER_READY_MASK;
1560*4882a593Smuzhiyun }
1561*4882a593Smuzhiyun
1562*4882a593Smuzhiyun chip->buffer_size = chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize +
1563*4882a593Smuzhiyun chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
1564*4882a593Smuzhiyun if (chip->use_cache)
1565*4882a593Smuzhiyun chip->buffer_size += NM_TOTAL_COEFF_COUNT * 4;
1566*4882a593Smuzhiyun else
1567*4882a593Smuzhiyun chip->buffer_size += NM_MAX_PLAYBACK_COEF_SIZE + NM_MAX_RECORD_COEF_SIZE;
1568*4882a593Smuzhiyun
1569*4882a593Smuzhiyun if (buffer_top >= chip->buffer_size && buffer_top < chip->buffer_end)
1570*4882a593Smuzhiyun chip->buffer_end = buffer_top;
1571*4882a593Smuzhiyun else {
1572*4882a593Smuzhiyun /* get buffer end pointer from signature */
1573*4882a593Smuzhiyun if ((err = snd_nm256_peek_for_sig(chip)) < 0)
1574*4882a593Smuzhiyun goto __error;
1575*4882a593Smuzhiyun }
1576*4882a593Smuzhiyun
1577*4882a593Smuzhiyun chip->buffer_start = chip->buffer_end - chip->buffer_size;
1578*4882a593Smuzhiyun chip->buffer_addr += chip->buffer_start;
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun dev_info(card->dev, "Mapping port 1 from 0x%x - 0x%x\n",
1581*4882a593Smuzhiyun chip->buffer_start, chip->buffer_end);
1582*4882a593Smuzhiyun
1583*4882a593Smuzhiyun chip->res_buffer = request_mem_region(chip->buffer_addr,
1584*4882a593Smuzhiyun chip->buffer_size,
1585*4882a593Smuzhiyun card->driver);
1586*4882a593Smuzhiyun if (chip->res_buffer == NULL) {
1587*4882a593Smuzhiyun dev_err(card->dev, "buffer 0x%lx (size 0x%x) busy\n",
1588*4882a593Smuzhiyun chip->buffer_addr, chip->buffer_size);
1589*4882a593Smuzhiyun err = -EBUSY;
1590*4882a593Smuzhiyun goto __error;
1591*4882a593Smuzhiyun }
1592*4882a593Smuzhiyun chip->buffer = ioremap(chip->buffer_addr, chip->buffer_size);
1593*4882a593Smuzhiyun if (chip->buffer == NULL) {
1594*4882a593Smuzhiyun err = -ENOMEM;
1595*4882a593Smuzhiyun dev_err(card->dev, "unable to map ring buffer at %lx\n",
1596*4882a593Smuzhiyun chip->buffer_addr);
1597*4882a593Smuzhiyun goto __error;
1598*4882a593Smuzhiyun }
1599*4882a593Smuzhiyun
1600*4882a593Smuzhiyun /* set offsets */
1601*4882a593Smuzhiyun addr = chip->buffer_start;
1602*4882a593Smuzhiyun chip->streams[SNDRV_PCM_STREAM_PLAYBACK].buf = addr;
1603*4882a593Smuzhiyun addr += chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize;
1604*4882a593Smuzhiyun chip->streams[SNDRV_PCM_STREAM_CAPTURE].buf = addr;
1605*4882a593Smuzhiyun addr += chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
1606*4882a593Smuzhiyun if (chip->use_cache) {
1607*4882a593Smuzhiyun chip->all_coeff_buf = addr;
1608*4882a593Smuzhiyun } else {
1609*4882a593Smuzhiyun chip->coeff_buf[SNDRV_PCM_STREAM_PLAYBACK] = addr;
1610*4882a593Smuzhiyun addr += NM_MAX_PLAYBACK_COEF_SIZE;
1611*4882a593Smuzhiyun chip->coeff_buf[SNDRV_PCM_STREAM_CAPTURE] = addr;
1612*4882a593Smuzhiyun }
1613*4882a593Smuzhiyun
1614*4882a593Smuzhiyun /* Fixed setting. */
1615*4882a593Smuzhiyun chip->mixer_base = NM_MIXER_OFFSET;
1616*4882a593Smuzhiyun
1617*4882a593Smuzhiyun chip->coeffs_current = 0;
1618*4882a593Smuzhiyun
1619*4882a593Smuzhiyun snd_nm256_init_chip(chip);
1620*4882a593Smuzhiyun
1621*4882a593Smuzhiyun // pci_set_master(pci); /* needed? */
1622*4882a593Smuzhiyun
1623*4882a593Smuzhiyun if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0)
1624*4882a593Smuzhiyun goto __error;
1625*4882a593Smuzhiyun
1626*4882a593Smuzhiyun *chip_ret = chip;
1627*4882a593Smuzhiyun return 0;
1628*4882a593Smuzhiyun
1629*4882a593Smuzhiyun __error:
1630*4882a593Smuzhiyun snd_nm256_free(chip);
1631*4882a593Smuzhiyun return err;
1632*4882a593Smuzhiyun }
1633*4882a593Smuzhiyun
1634*4882a593Smuzhiyun
1635*4882a593Smuzhiyun enum { NM_IGNORED, NM_RESET_WORKAROUND, NM_RESET_WORKAROUND_2 };
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun static const struct snd_pci_quirk nm256_quirks[] = {
1638*4882a593Smuzhiyun /* HP omnibook 4150 has cs4232 codec internally */
1639*4882a593Smuzhiyun SND_PCI_QUIRK(0x103c, 0x0007, "HP omnibook 4150", NM_IGNORED),
1640*4882a593Smuzhiyun /* Reset workarounds to avoid lock-ups */
1641*4882a593Smuzhiyun SND_PCI_QUIRK(0x104d, 0x8041, "Sony PCG-F305", NM_RESET_WORKAROUND),
1642*4882a593Smuzhiyun SND_PCI_QUIRK(0x1028, 0x0080, "Dell Latitude LS", NM_RESET_WORKAROUND),
1643*4882a593Smuzhiyun SND_PCI_QUIRK(0x1028, 0x0091, "Dell Latitude CSx", NM_RESET_WORKAROUND_2),
1644*4882a593Smuzhiyun { } /* terminator */
1645*4882a593Smuzhiyun };
1646*4882a593Smuzhiyun
1647*4882a593Smuzhiyun
snd_nm256_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1648*4882a593Smuzhiyun static int snd_nm256_probe(struct pci_dev *pci,
1649*4882a593Smuzhiyun const struct pci_device_id *pci_id)
1650*4882a593Smuzhiyun {
1651*4882a593Smuzhiyun struct snd_card *card;
1652*4882a593Smuzhiyun struct nm256 *chip;
1653*4882a593Smuzhiyun int err;
1654*4882a593Smuzhiyun const struct snd_pci_quirk *q;
1655*4882a593Smuzhiyun
1656*4882a593Smuzhiyun q = snd_pci_quirk_lookup(pci, nm256_quirks);
1657*4882a593Smuzhiyun if (q) {
1658*4882a593Smuzhiyun dev_dbg(&pci->dev, "Enabled quirk for %s.\n",
1659*4882a593Smuzhiyun snd_pci_quirk_name(q));
1660*4882a593Smuzhiyun switch (q->value) {
1661*4882a593Smuzhiyun case NM_IGNORED:
1662*4882a593Smuzhiyun dev_info(&pci->dev,
1663*4882a593Smuzhiyun "The device is on the denylist. Loading stopped\n");
1664*4882a593Smuzhiyun return -ENODEV;
1665*4882a593Smuzhiyun case NM_RESET_WORKAROUND_2:
1666*4882a593Smuzhiyun reset_workaround_2 = 1;
1667*4882a593Smuzhiyun fallthrough;
1668*4882a593Smuzhiyun case NM_RESET_WORKAROUND:
1669*4882a593Smuzhiyun reset_workaround = 1;
1670*4882a593Smuzhiyun break;
1671*4882a593Smuzhiyun }
1672*4882a593Smuzhiyun }
1673*4882a593Smuzhiyun
1674*4882a593Smuzhiyun err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
1675*4882a593Smuzhiyun if (err < 0)
1676*4882a593Smuzhiyun return err;
1677*4882a593Smuzhiyun
1678*4882a593Smuzhiyun switch (pci->device) {
1679*4882a593Smuzhiyun case PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO:
1680*4882a593Smuzhiyun strcpy(card->driver, "NM256AV");
1681*4882a593Smuzhiyun break;
1682*4882a593Smuzhiyun case PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO:
1683*4882a593Smuzhiyun strcpy(card->driver, "NM256ZX");
1684*4882a593Smuzhiyun break;
1685*4882a593Smuzhiyun case PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO:
1686*4882a593Smuzhiyun strcpy(card->driver, "NM256XL+");
1687*4882a593Smuzhiyun break;
1688*4882a593Smuzhiyun default:
1689*4882a593Smuzhiyun dev_err(&pci->dev, "invalid device id 0x%x\n", pci->device);
1690*4882a593Smuzhiyun snd_card_free(card);
1691*4882a593Smuzhiyun return -EINVAL;
1692*4882a593Smuzhiyun }
1693*4882a593Smuzhiyun
1694*4882a593Smuzhiyun if (vaio_hack)
1695*4882a593Smuzhiyun buffer_top = 0x25a800; /* this avoids conflicts with XFree86 server */
1696*4882a593Smuzhiyun
1697*4882a593Smuzhiyun if (playback_bufsize < 4)
1698*4882a593Smuzhiyun playback_bufsize = 4;
1699*4882a593Smuzhiyun if (playback_bufsize > 128)
1700*4882a593Smuzhiyun playback_bufsize = 128;
1701*4882a593Smuzhiyun if (capture_bufsize < 4)
1702*4882a593Smuzhiyun capture_bufsize = 4;
1703*4882a593Smuzhiyun if (capture_bufsize > 128)
1704*4882a593Smuzhiyun capture_bufsize = 128;
1705*4882a593Smuzhiyun if ((err = snd_nm256_create(card, pci, &chip)) < 0) {
1706*4882a593Smuzhiyun snd_card_free(card);
1707*4882a593Smuzhiyun return err;
1708*4882a593Smuzhiyun }
1709*4882a593Smuzhiyun card->private_data = chip;
1710*4882a593Smuzhiyun
1711*4882a593Smuzhiyun if (reset_workaround) {
1712*4882a593Smuzhiyun dev_dbg(&pci->dev, "reset_workaround activated\n");
1713*4882a593Smuzhiyun chip->reset_workaround = 1;
1714*4882a593Smuzhiyun }
1715*4882a593Smuzhiyun
1716*4882a593Smuzhiyun if (reset_workaround_2) {
1717*4882a593Smuzhiyun dev_dbg(&pci->dev, "reset_workaround_2 activated\n");
1718*4882a593Smuzhiyun chip->reset_workaround_2 = 1;
1719*4882a593Smuzhiyun }
1720*4882a593Smuzhiyun
1721*4882a593Smuzhiyun if ((err = snd_nm256_pcm(chip, 0)) < 0 ||
1722*4882a593Smuzhiyun (err = snd_nm256_mixer(chip)) < 0) {
1723*4882a593Smuzhiyun snd_card_free(card);
1724*4882a593Smuzhiyun return err;
1725*4882a593Smuzhiyun }
1726*4882a593Smuzhiyun
1727*4882a593Smuzhiyun sprintf(card->shortname, "NeoMagic %s", card->driver);
1728*4882a593Smuzhiyun sprintf(card->longname, "%s at 0x%lx & 0x%lx, irq %d",
1729*4882a593Smuzhiyun card->shortname,
1730*4882a593Smuzhiyun chip->buffer_addr, chip->cport_addr, chip->irq);
1731*4882a593Smuzhiyun
1732*4882a593Smuzhiyun if ((err = snd_card_register(card)) < 0) {
1733*4882a593Smuzhiyun snd_card_free(card);
1734*4882a593Smuzhiyun return err;
1735*4882a593Smuzhiyun }
1736*4882a593Smuzhiyun
1737*4882a593Smuzhiyun pci_set_drvdata(pci, card);
1738*4882a593Smuzhiyun return 0;
1739*4882a593Smuzhiyun }
1740*4882a593Smuzhiyun
snd_nm256_remove(struct pci_dev * pci)1741*4882a593Smuzhiyun static void snd_nm256_remove(struct pci_dev *pci)
1742*4882a593Smuzhiyun {
1743*4882a593Smuzhiyun snd_card_free(pci_get_drvdata(pci));
1744*4882a593Smuzhiyun }
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun
1747*4882a593Smuzhiyun static struct pci_driver nm256_driver = {
1748*4882a593Smuzhiyun .name = KBUILD_MODNAME,
1749*4882a593Smuzhiyun .id_table = snd_nm256_ids,
1750*4882a593Smuzhiyun .probe = snd_nm256_probe,
1751*4882a593Smuzhiyun .remove = snd_nm256_remove,
1752*4882a593Smuzhiyun .driver = {
1753*4882a593Smuzhiyun .pm = NM256_PM_OPS,
1754*4882a593Smuzhiyun },
1755*4882a593Smuzhiyun };
1756*4882a593Smuzhiyun
1757*4882a593Smuzhiyun module_pci_driver(nm256_driver);
1758