1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Support for Digigram Lola PCI-e boards
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2011 Takashi Iwai <tiwai@suse.de>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/dma-mapping.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/pci.h>
16*4882a593Smuzhiyun #include <sound/core.h>
17*4882a593Smuzhiyun #include <sound/control.h>
18*4882a593Smuzhiyun #include <sound/pcm.h>
19*4882a593Smuzhiyun #include <sound/initval.h>
20*4882a593Smuzhiyun #include "lola.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Standard options */
23*4882a593Smuzhiyun static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
24*4882a593Smuzhiyun static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
25*4882a593Smuzhiyun static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun module_param_array(index, int, NULL, 0444);
28*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for Digigram Lola driver.");
29*4882a593Smuzhiyun module_param_array(id, charp, NULL, 0444);
30*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for Digigram Lola driver.");
31*4882a593Smuzhiyun module_param_array(enable, bool, NULL, 0444);
32*4882a593Smuzhiyun MODULE_PARM_DESC(enable, "Enable Digigram Lola driver.");
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Lola-specific options */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* for instance use always max granularity which is compatible
37*4882a593Smuzhiyun * with all sample rates
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun static int granularity[SNDRV_CARDS] = {
40*4882a593Smuzhiyun [0 ... (SNDRV_CARDS - 1)] = LOLA_GRANULARITY_MAX
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* below a sample_rate of 16kHz the analogue audio quality is NOT excellent */
44*4882a593Smuzhiyun static int sample_rate_min[SNDRV_CARDS] = {
45*4882a593Smuzhiyun [0 ... (SNDRV_CARDS - 1) ] = 16000
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun module_param_array(granularity, int, NULL, 0444);
49*4882a593Smuzhiyun MODULE_PARM_DESC(granularity, "Granularity value");
50*4882a593Smuzhiyun module_param_array(sample_rate_min, int, NULL, 0444);
51*4882a593Smuzhiyun MODULE_PARM_DESC(sample_rate_min, "Minimal sample rate");
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun MODULE_LICENSE("GPL");
57*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{{Digigram, Lola}}");
58*4882a593Smuzhiyun MODULE_DESCRIPTION("Digigram Lola driver");
59*4882a593Smuzhiyun MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #ifdef CONFIG_SND_DEBUG_VERBOSE
62*4882a593Smuzhiyun static int debug;
63*4882a593Smuzhiyun module_param(debug, int, 0644);
64*4882a593Smuzhiyun #define verbose_debug(fmt, args...) \
65*4882a593Smuzhiyun do { if (debug > 1) pr_debug(SFX fmt, ##args); } while (0)
66*4882a593Smuzhiyun #else
67*4882a593Smuzhiyun #define verbose_debug(fmt, args...)
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * pseudo-codec read/write via CORB/RIRB
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun
corb_send_verb(struct lola * chip,unsigned int nid,unsigned int verb,unsigned int data,unsigned int extdata)74*4882a593Smuzhiyun static int corb_send_verb(struct lola *chip, unsigned int nid,
75*4882a593Smuzhiyun unsigned int verb, unsigned int data,
76*4882a593Smuzhiyun unsigned int extdata)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun unsigned long flags;
79*4882a593Smuzhiyun int ret = -EIO;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun chip->last_cmd_nid = nid;
82*4882a593Smuzhiyun chip->last_verb = verb;
83*4882a593Smuzhiyun chip->last_data = data;
84*4882a593Smuzhiyun chip->last_extdata = extdata;
85*4882a593Smuzhiyun data |= (nid << 20) | (verb << 8);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
88*4882a593Smuzhiyun if (chip->rirb.cmds < LOLA_CORB_ENTRIES - 1) {
89*4882a593Smuzhiyun unsigned int wp = chip->corb.wp + 1;
90*4882a593Smuzhiyun wp %= LOLA_CORB_ENTRIES;
91*4882a593Smuzhiyun chip->corb.wp = wp;
92*4882a593Smuzhiyun chip->corb.buf[wp * 2] = cpu_to_le32(data);
93*4882a593Smuzhiyun chip->corb.buf[wp * 2 + 1] = cpu_to_le32(extdata);
94*4882a593Smuzhiyun lola_writew(chip, BAR0, CORBWP, wp);
95*4882a593Smuzhiyun chip->rirb.cmds++;
96*4882a593Smuzhiyun smp_wmb();
97*4882a593Smuzhiyun ret = 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
100*4882a593Smuzhiyun return ret;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
lola_queue_unsol_event(struct lola * chip,unsigned int res,unsigned int res_ex)103*4882a593Smuzhiyun static void lola_queue_unsol_event(struct lola *chip, unsigned int res,
104*4882a593Smuzhiyun unsigned int res_ex)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun lola_update_ext_clock_freq(chip, res);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* retrieve RIRB entry - called from interrupt handler */
lola_update_rirb(struct lola * chip)110*4882a593Smuzhiyun static void lola_update_rirb(struct lola *chip)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun unsigned int rp, wp;
113*4882a593Smuzhiyun u32 res, res_ex;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun wp = lola_readw(chip, BAR0, RIRBWP);
116*4882a593Smuzhiyun if (wp == chip->rirb.wp)
117*4882a593Smuzhiyun return;
118*4882a593Smuzhiyun chip->rirb.wp = wp;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun while (chip->rirb.rp != wp) {
121*4882a593Smuzhiyun chip->rirb.rp++;
122*4882a593Smuzhiyun chip->rirb.rp %= LOLA_CORB_ENTRIES;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
125*4882a593Smuzhiyun res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
126*4882a593Smuzhiyun res = le32_to_cpu(chip->rirb.buf[rp]);
127*4882a593Smuzhiyun if (res_ex & LOLA_RIRB_EX_UNSOL_EV)
128*4882a593Smuzhiyun lola_queue_unsol_event(chip, res, res_ex);
129*4882a593Smuzhiyun else if (chip->rirb.cmds) {
130*4882a593Smuzhiyun chip->res = res;
131*4882a593Smuzhiyun chip->res_ex = res_ex;
132*4882a593Smuzhiyun smp_wmb();
133*4882a593Smuzhiyun chip->rirb.cmds--;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
rirb_get_response(struct lola * chip,unsigned int * val,unsigned int * extval)138*4882a593Smuzhiyun static int rirb_get_response(struct lola *chip, unsigned int *val,
139*4882a593Smuzhiyun unsigned int *extval)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun unsigned long timeout;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun again:
144*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(1000);
145*4882a593Smuzhiyun for (;;) {
146*4882a593Smuzhiyun if (chip->polling_mode) {
147*4882a593Smuzhiyun spin_lock_irq(&chip->reg_lock);
148*4882a593Smuzhiyun lola_update_rirb(chip);
149*4882a593Smuzhiyun spin_unlock_irq(&chip->reg_lock);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun if (!chip->rirb.cmds) {
152*4882a593Smuzhiyun *val = chip->res;
153*4882a593Smuzhiyun if (extval)
154*4882a593Smuzhiyun *extval = chip->res_ex;
155*4882a593Smuzhiyun verbose_debug("get_response: %x, %x\n",
156*4882a593Smuzhiyun chip->res, chip->res_ex);
157*4882a593Smuzhiyun if (chip->res_ex & LOLA_RIRB_EX_ERROR) {
158*4882a593Smuzhiyun dev_warn(chip->card->dev, "RIRB ERROR: "
159*4882a593Smuzhiyun "NID=%x, verb=%x, data=%x, ext=%x\n",
160*4882a593Smuzhiyun chip->last_cmd_nid,
161*4882a593Smuzhiyun chip->last_verb, chip->last_data,
162*4882a593Smuzhiyun chip->last_extdata);
163*4882a593Smuzhiyun return -EIO;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun return 0;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun if (time_after(jiffies, timeout))
168*4882a593Smuzhiyun break;
169*4882a593Smuzhiyun udelay(20);
170*4882a593Smuzhiyun cond_resched();
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun dev_warn(chip->card->dev, "RIRB response error\n");
173*4882a593Smuzhiyun if (!chip->polling_mode) {
174*4882a593Smuzhiyun dev_warn(chip->card->dev, "switching to polling mode\n");
175*4882a593Smuzhiyun chip->polling_mode = 1;
176*4882a593Smuzhiyun goto again;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun return -EIO;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* aynchronous write of a codec verb with data */
lola_codec_write(struct lola * chip,unsigned int nid,unsigned int verb,unsigned int data,unsigned int extdata)182*4882a593Smuzhiyun int lola_codec_write(struct lola *chip, unsigned int nid, unsigned int verb,
183*4882a593Smuzhiyun unsigned int data, unsigned int extdata)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun verbose_debug("codec_write NID=%x, verb=%x, data=%x, ext=%x\n",
186*4882a593Smuzhiyun nid, verb, data, extdata);
187*4882a593Smuzhiyun return corb_send_verb(chip, nid, verb, data, extdata);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* write a codec verb with data and read the returned status */
lola_codec_read(struct lola * chip,unsigned int nid,unsigned int verb,unsigned int data,unsigned int extdata,unsigned int * val,unsigned int * extval)191*4882a593Smuzhiyun int lola_codec_read(struct lola *chip, unsigned int nid, unsigned int verb,
192*4882a593Smuzhiyun unsigned int data, unsigned int extdata,
193*4882a593Smuzhiyun unsigned int *val, unsigned int *extval)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun int err;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun verbose_debug("codec_read NID=%x, verb=%x, data=%x, ext=%x\n",
198*4882a593Smuzhiyun nid, verb, data, extdata);
199*4882a593Smuzhiyun err = corb_send_verb(chip, nid, verb, data, extdata);
200*4882a593Smuzhiyun if (err < 0)
201*4882a593Smuzhiyun return err;
202*4882a593Smuzhiyun err = rirb_get_response(chip, val, extval);
203*4882a593Smuzhiyun return err;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun /* flush all pending codec writes */
lola_codec_flush(struct lola * chip)207*4882a593Smuzhiyun int lola_codec_flush(struct lola *chip)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun unsigned int tmp;
210*4882a593Smuzhiyun return rirb_get_response(chip, &tmp, NULL);
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun /*
214*4882a593Smuzhiyun * interrupt handler
215*4882a593Smuzhiyun */
lola_interrupt(int irq,void * dev_id)216*4882a593Smuzhiyun static irqreturn_t lola_interrupt(int irq, void *dev_id)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun struct lola *chip = dev_id;
219*4882a593Smuzhiyun unsigned int notify_ins, notify_outs, error_ins, error_outs;
220*4882a593Smuzhiyun int handled = 0;
221*4882a593Smuzhiyun int i;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun notify_ins = notify_outs = error_ins = error_outs = 0;
224*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
225*4882a593Smuzhiyun for (;;) {
226*4882a593Smuzhiyun unsigned int status, in_sts, out_sts;
227*4882a593Smuzhiyun unsigned int reg;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun status = lola_readl(chip, BAR1, DINTSTS);
230*4882a593Smuzhiyun if (!status || status == -1)
231*4882a593Smuzhiyun break;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun in_sts = lola_readl(chip, BAR1, DIINTSTS);
234*4882a593Smuzhiyun out_sts = lola_readl(chip, BAR1, DOINTSTS);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /* clear Input Interrupts */
237*4882a593Smuzhiyun for (i = 0; in_sts && i < chip->pcm[CAPT].num_streams; i++) {
238*4882a593Smuzhiyun if (!(in_sts & (1 << i)))
239*4882a593Smuzhiyun continue;
240*4882a593Smuzhiyun in_sts &= ~(1 << i);
241*4882a593Smuzhiyun reg = lola_dsd_read(chip, i, STS);
242*4882a593Smuzhiyun if (reg & LOLA_DSD_STS_DESE) /* error */
243*4882a593Smuzhiyun error_ins |= (1 << i);
244*4882a593Smuzhiyun if (reg & LOLA_DSD_STS_BCIS) /* notify */
245*4882a593Smuzhiyun notify_ins |= (1 << i);
246*4882a593Smuzhiyun /* clear */
247*4882a593Smuzhiyun lola_dsd_write(chip, i, STS, reg);
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /* clear Output Interrupts */
251*4882a593Smuzhiyun for (i = 0; out_sts && i < chip->pcm[PLAY].num_streams; i++) {
252*4882a593Smuzhiyun if (!(out_sts & (1 << i)))
253*4882a593Smuzhiyun continue;
254*4882a593Smuzhiyun out_sts &= ~(1 << i);
255*4882a593Smuzhiyun reg = lola_dsd_read(chip, i + MAX_STREAM_IN_COUNT, STS);
256*4882a593Smuzhiyun if (reg & LOLA_DSD_STS_DESE) /* error */
257*4882a593Smuzhiyun error_outs |= (1 << i);
258*4882a593Smuzhiyun if (reg & LOLA_DSD_STS_BCIS) /* notify */
259*4882a593Smuzhiyun notify_outs |= (1 << i);
260*4882a593Smuzhiyun lola_dsd_write(chip, i + MAX_STREAM_IN_COUNT, STS, reg);
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun if (status & LOLA_DINT_CTRL) {
264*4882a593Smuzhiyun unsigned char rbsts; /* ring status is byte access */
265*4882a593Smuzhiyun rbsts = lola_readb(chip, BAR0, RIRBSTS);
266*4882a593Smuzhiyun rbsts &= LOLA_RIRB_INT_MASK;
267*4882a593Smuzhiyun if (rbsts)
268*4882a593Smuzhiyun lola_writeb(chip, BAR0, RIRBSTS, rbsts);
269*4882a593Smuzhiyun rbsts = lola_readb(chip, BAR0, CORBSTS);
270*4882a593Smuzhiyun rbsts &= LOLA_CORB_INT_MASK;
271*4882a593Smuzhiyun if (rbsts)
272*4882a593Smuzhiyun lola_writeb(chip, BAR0, CORBSTS, rbsts);
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun lola_update_rirb(chip);
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun if (status & (LOLA_DINT_FIFOERR | LOLA_DINT_MUERR)) {
278*4882a593Smuzhiyun /* clear global fifo error interrupt */
279*4882a593Smuzhiyun lola_writel(chip, BAR1, DINTSTS,
280*4882a593Smuzhiyun (status & (LOLA_DINT_FIFOERR | LOLA_DINT_MUERR)));
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun handled = 1;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun lola_pcm_update(chip, &chip->pcm[CAPT], notify_ins);
287*4882a593Smuzhiyun lola_pcm_update(chip, &chip->pcm[PLAY], notify_outs);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun return IRQ_RETVAL(handled);
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /*
294*4882a593Smuzhiyun * controller
295*4882a593Smuzhiyun */
reset_controller(struct lola * chip)296*4882a593Smuzhiyun static int reset_controller(struct lola *chip)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun unsigned int gctl = lola_readl(chip, BAR0, GCTL);
299*4882a593Smuzhiyun unsigned long end_time;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun if (gctl) {
302*4882a593Smuzhiyun /* to be sure */
303*4882a593Smuzhiyun lola_writel(chip, BAR1, BOARD_MODE, 0);
304*4882a593Smuzhiyun return 0;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun chip->cold_reset = 1;
308*4882a593Smuzhiyun lola_writel(chip, BAR0, GCTL, LOLA_GCTL_RESET);
309*4882a593Smuzhiyun end_time = jiffies + msecs_to_jiffies(200);
310*4882a593Smuzhiyun do {
311*4882a593Smuzhiyun msleep(1);
312*4882a593Smuzhiyun gctl = lola_readl(chip, BAR0, GCTL);
313*4882a593Smuzhiyun if (gctl)
314*4882a593Smuzhiyun break;
315*4882a593Smuzhiyun } while (time_before(jiffies, end_time));
316*4882a593Smuzhiyun if (!gctl) {
317*4882a593Smuzhiyun dev_err(chip->card->dev, "cannot reset controller\n");
318*4882a593Smuzhiyun return -EIO;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun return 0;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
lola_irq_enable(struct lola * chip)323*4882a593Smuzhiyun static void lola_irq_enable(struct lola *chip)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun unsigned int val;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /* enalbe all I/O streams */
328*4882a593Smuzhiyun val = (1 << chip->pcm[PLAY].num_streams) - 1;
329*4882a593Smuzhiyun lola_writel(chip, BAR1, DOINTCTL, val);
330*4882a593Smuzhiyun val = (1 << chip->pcm[CAPT].num_streams) - 1;
331*4882a593Smuzhiyun lola_writel(chip, BAR1, DIINTCTL, val);
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun /* enable global irqs */
334*4882a593Smuzhiyun val = LOLA_DINT_GLOBAL | LOLA_DINT_CTRL | LOLA_DINT_FIFOERR |
335*4882a593Smuzhiyun LOLA_DINT_MUERR;
336*4882a593Smuzhiyun lola_writel(chip, BAR1, DINTCTL, val);
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
lola_irq_disable(struct lola * chip)339*4882a593Smuzhiyun static void lola_irq_disable(struct lola *chip)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun lola_writel(chip, BAR1, DINTCTL, 0);
342*4882a593Smuzhiyun lola_writel(chip, BAR1, DIINTCTL, 0);
343*4882a593Smuzhiyun lola_writel(chip, BAR1, DOINTCTL, 0);
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
setup_corb_rirb(struct lola * chip)346*4882a593Smuzhiyun static int setup_corb_rirb(struct lola *chip)
347*4882a593Smuzhiyun {
348*4882a593Smuzhiyun int err;
349*4882a593Smuzhiyun unsigned char tmp;
350*4882a593Smuzhiyun unsigned long end_time;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
353*4882a593Smuzhiyun &chip->pci->dev,
354*4882a593Smuzhiyun PAGE_SIZE, &chip->rb);
355*4882a593Smuzhiyun if (err < 0)
356*4882a593Smuzhiyun return err;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun chip->corb.addr = chip->rb.addr;
359*4882a593Smuzhiyun chip->corb.buf = (__le32 *)chip->rb.area;
360*4882a593Smuzhiyun chip->rirb.addr = chip->rb.addr + 2048;
361*4882a593Smuzhiyun chip->rirb.buf = (__le32 *)(chip->rb.area + 2048);
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun /* disable ringbuffer DMAs */
364*4882a593Smuzhiyun lola_writeb(chip, BAR0, RIRBCTL, 0);
365*4882a593Smuzhiyun lola_writeb(chip, BAR0, CORBCTL, 0);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun end_time = jiffies + msecs_to_jiffies(200);
368*4882a593Smuzhiyun do {
369*4882a593Smuzhiyun if (!lola_readb(chip, BAR0, RIRBCTL) &&
370*4882a593Smuzhiyun !lola_readb(chip, BAR0, CORBCTL))
371*4882a593Smuzhiyun break;
372*4882a593Smuzhiyun msleep(1);
373*4882a593Smuzhiyun } while (time_before(jiffies, end_time));
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun /* CORB set up */
376*4882a593Smuzhiyun lola_writel(chip, BAR0, CORBLBASE, (u32)chip->corb.addr);
377*4882a593Smuzhiyun lola_writel(chip, BAR0, CORBUBASE, upper_32_bits(chip->corb.addr));
378*4882a593Smuzhiyun /* set the corb size to 256 entries */
379*4882a593Smuzhiyun lola_writeb(chip, BAR0, CORBSIZE, 0x02);
380*4882a593Smuzhiyun /* set the corb write pointer to 0 */
381*4882a593Smuzhiyun lola_writew(chip, BAR0, CORBWP, 0);
382*4882a593Smuzhiyun /* reset the corb hw read pointer */
383*4882a593Smuzhiyun lola_writew(chip, BAR0, CORBRP, LOLA_RBRWP_CLR);
384*4882a593Smuzhiyun /* enable corb dma */
385*4882a593Smuzhiyun lola_writeb(chip, BAR0, CORBCTL, LOLA_RBCTL_DMA_EN);
386*4882a593Smuzhiyun /* clear flags if set */
387*4882a593Smuzhiyun tmp = lola_readb(chip, BAR0, CORBSTS) & LOLA_CORB_INT_MASK;
388*4882a593Smuzhiyun if (tmp)
389*4882a593Smuzhiyun lola_writeb(chip, BAR0, CORBSTS, tmp);
390*4882a593Smuzhiyun chip->corb.wp = 0;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun /* RIRB set up */
393*4882a593Smuzhiyun lola_writel(chip, BAR0, RIRBLBASE, (u32)chip->rirb.addr);
394*4882a593Smuzhiyun lola_writel(chip, BAR0, RIRBUBASE, upper_32_bits(chip->rirb.addr));
395*4882a593Smuzhiyun /* set the rirb size to 256 entries */
396*4882a593Smuzhiyun lola_writeb(chip, BAR0, RIRBSIZE, 0x02);
397*4882a593Smuzhiyun /* reset the rirb hw write pointer */
398*4882a593Smuzhiyun lola_writew(chip, BAR0, RIRBWP, LOLA_RBRWP_CLR);
399*4882a593Smuzhiyun /* set N=1, get RIRB response interrupt for new entry */
400*4882a593Smuzhiyun lola_writew(chip, BAR0, RINTCNT, 1);
401*4882a593Smuzhiyun /* enable rirb dma and response irq */
402*4882a593Smuzhiyun lola_writeb(chip, BAR0, RIRBCTL, LOLA_RBCTL_DMA_EN | LOLA_RBCTL_IRQ_EN);
403*4882a593Smuzhiyun /* clear flags if set */
404*4882a593Smuzhiyun tmp = lola_readb(chip, BAR0, RIRBSTS) & LOLA_RIRB_INT_MASK;
405*4882a593Smuzhiyun if (tmp)
406*4882a593Smuzhiyun lola_writeb(chip, BAR0, RIRBSTS, tmp);
407*4882a593Smuzhiyun chip->rirb.rp = chip->rirb.cmds = 0;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun return 0;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
stop_corb_rirb(struct lola * chip)412*4882a593Smuzhiyun static void stop_corb_rirb(struct lola *chip)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun /* disable ringbuffer DMAs */
415*4882a593Smuzhiyun lola_writeb(chip, BAR0, RIRBCTL, 0);
416*4882a593Smuzhiyun lola_writeb(chip, BAR0, CORBCTL, 0);
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun
lola_reset_setups(struct lola * chip)419*4882a593Smuzhiyun static void lola_reset_setups(struct lola *chip)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun /* update the granularity */
422*4882a593Smuzhiyun lola_set_granularity(chip, chip->granularity, true);
423*4882a593Smuzhiyun /* update the sample clock */
424*4882a593Smuzhiyun lola_set_clock_index(chip, chip->clock.cur_index);
425*4882a593Smuzhiyun /* enable unsolicited events of the clock widget */
426*4882a593Smuzhiyun lola_enable_clock_events(chip);
427*4882a593Smuzhiyun /* update the analog gains */
428*4882a593Smuzhiyun lola_setup_all_analog_gains(chip, CAPT, false); /* input, update */
429*4882a593Smuzhiyun /* update SRC configuration if applicable */
430*4882a593Smuzhiyun lola_set_src_config(chip, chip->input_src_mask, false);
431*4882a593Smuzhiyun /* update the analog outputs */
432*4882a593Smuzhiyun lola_setup_all_analog_gains(chip, PLAY, false); /* output, update */
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun
lola_parse_tree(struct lola * chip)435*4882a593Smuzhiyun static int lola_parse_tree(struct lola *chip)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun unsigned int val;
438*4882a593Smuzhiyun int nid, err;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun err = lola_read_param(chip, 0, LOLA_PAR_VENDOR_ID, &val);
441*4882a593Smuzhiyun if (err < 0) {
442*4882a593Smuzhiyun dev_err(chip->card->dev, "Can't read VENDOR_ID\n");
443*4882a593Smuzhiyun return err;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun val >>= 16;
446*4882a593Smuzhiyun if (val != 0x1369) {
447*4882a593Smuzhiyun dev_err(chip->card->dev, "Unknown codec vendor 0x%x\n", val);
448*4882a593Smuzhiyun return -EINVAL;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun err = lola_read_param(chip, 1, LOLA_PAR_FUNCTION_TYPE, &val);
452*4882a593Smuzhiyun if (err < 0) {
453*4882a593Smuzhiyun dev_err(chip->card->dev, "Can't read FUNCTION_TYPE\n");
454*4882a593Smuzhiyun return err;
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun if (val != 1) {
457*4882a593Smuzhiyun dev_err(chip->card->dev, "Unknown function type %d\n", val);
458*4882a593Smuzhiyun return -EINVAL;
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun err = lola_read_param(chip, 1, LOLA_PAR_SPECIFIC_CAPS, &val);
462*4882a593Smuzhiyun if (err < 0) {
463*4882a593Smuzhiyun dev_err(chip->card->dev, "Can't read SPECCAPS\n");
464*4882a593Smuzhiyun return err;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun chip->lola_caps = val;
467*4882a593Smuzhiyun chip->pin[CAPT].num_pins = LOLA_AFG_INPUT_PIN_COUNT(chip->lola_caps);
468*4882a593Smuzhiyun chip->pin[PLAY].num_pins = LOLA_AFG_OUTPUT_PIN_COUNT(chip->lola_caps);
469*4882a593Smuzhiyun dev_dbg(chip->card->dev, "speccaps=0x%x, pins in=%d, out=%d\n",
470*4882a593Smuzhiyun chip->lola_caps,
471*4882a593Smuzhiyun chip->pin[CAPT].num_pins, chip->pin[PLAY].num_pins);
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun if (chip->pin[CAPT].num_pins > MAX_AUDIO_INOUT_COUNT ||
474*4882a593Smuzhiyun chip->pin[PLAY].num_pins > MAX_AUDIO_INOUT_COUNT) {
475*4882a593Smuzhiyun dev_err(chip->card->dev, "Invalid Lola-spec caps 0x%x\n", val);
476*4882a593Smuzhiyun return -EINVAL;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun nid = 0x02;
480*4882a593Smuzhiyun err = lola_init_pcm(chip, CAPT, &nid);
481*4882a593Smuzhiyun if (err < 0)
482*4882a593Smuzhiyun return err;
483*4882a593Smuzhiyun err = lola_init_pcm(chip, PLAY, &nid);
484*4882a593Smuzhiyun if (err < 0)
485*4882a593Smuzhiyun return err;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun err = lola_init_pins(chip, CAPT, &nid);
488*4882a593Smuzhiyun if (err < 0)
489*4882a593Smuzhiyun return err;
490*4882a593Smuzhiyun err = lola_init_pins(chip, PLAY, &nid);
491*4882a593Smuzhiyun if (err < 0)
492*4882a593Smuzhiyun return err;
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun if (LOLA_AFG_CLOCK_WIDGET_PRESENT(chip->lola_caps)) {
495*4882a593Smuzhiyun err = lola_init_clock_widget(chip, nid);
496*4882a593Smuzhiyun if (err < 0)
497*4882a593Smuzhiyun return err;
498*4882a593Smuzhiyun nid++;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun if (LOLA_AFG_MIXER_WIDGET_PRESENT(chip->lola_caps)) {
501*4882a593Smuzhiyun err = lola_init_mixer_widget(chip, nid);
502*4882a593Smuzhiyun if (err < 0)
503*4882a593Smuzhiyun return err;
504*4882a593Smuzhiyun nid++;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun /* enable unsolicited events of the clock widget */
508*4882a593Smuzhiyun err = lola_enable_clock_events(chip);
509*4882a593Smuzhiyun if (err < 0)
510*4882a593Smuzhiyun return err;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun /* if last ResetController was not a ColdReset, we don't know
513*4882a593Smuzhiyun * the state of the card; initialize here again
514*4882a593Smuzhiyun */
515*4882a593Smuzhiyun if (!chip->cold_reset) {
516*4882a593Smuzhiyun lola_reset_setups(chip);
517*4882a593Smuzhiyun chip->cold_reset = 1;
518*4882a593Smuzhiyun } else {
519*4882a593Smuzhiyun /* set the granularity if it is not the default */
520*4882a593Smuzhiyun if (chip->granularity != LOLA_GRANULARITY_MIN)
521*4882a593Smuzhiyun lola_set_granularity(chip, chip->granularity, true);
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun return 0;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun
lola_stop_hw(struct lola * chip)527*4882a593Smuzhiyun static void lola_stop_hw(struct lola *chip)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun stop_corb_rirb(chip);
530*4882a593Smuzhiyun lola_irq_disable(chip);
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun
lola_free(struct lola * chip)533*4882a593Smuzhiyun static void lola_free(struct lola *chip)
534*4882a593Smuzhiyun {
535*4882a593Smuzhiyun if (chip->initialized)
536*4882a593Smuzhiyun lola_stop_hw(chip);
537*4882a593Smuzhiyun lola_free_pcm(chip);
538*4882a593Smuzhiyun lola_free_mixer(chip);
539*4882a593Smuzhiyun if (chip->irq >= 0)
540*4882a593Smuzhiyun free_irq(chip->irq, (void *)chip);
541*4882a593Smuzhiyun iounmap(chip->bar[0].remap_addr);
542*4882a593Smuzhiyun iounmap(chip->bar[1].remap_addr);
543*4882a593Smuzhiyun if (chip->rb.area)
544*4882a593Smuzhiyun snd_dma_free_pages(&chip->rb);
545*4882a593Smuzhiyun pci_release_regions(chip->pci);
546*4882a593Smuzhiyun pci_disable_device(chip->pci);
547*4882a593Smuzhiyun kfree(chip);
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
lola_dev_free(struct snd_device * device)550*4882a593Smuzhiyun static int lola_dev_free(struct snd_device *device)
551*4882a593Smuzhiyun {
552*4882a593Smuzhiyun lola_free(device->device_data);
553*4882a593Smuzhiyun return 0;
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun
lola_create(struct snd_card * card,struct pci_dev * pci,int dev,struct lola ** rchip)556*4882a593Smuzhiyun static int lola_create(struct snd_card *card, struct pci_dev *pci,
557*4882a593Smuzhiyun int dev, struct lola **rchip)
558*4882a593Smuzhiyun {
559*4882a593Smuzhiyun struct lola *chip;
560*4882a593Smuzhiyun int err;
561*4882a593Smuzhiyun unsigned int dever;
562*4882a593Smuzhiyun static const struct snd_device_ops ops = {
563*4882a593Smuzhiyun .dev_free = lola_dev_free,
564*4882a593Smuzhiyun };
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun *rchip = NULL;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun err = pci_enable_device(pci);
569*4882a593Smuzhiyun if (err < 0)
570*4882a593Smuzhiyun return err;
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun chip = kzalloc(sizeof(*chip), GFP_KERNEL);
573*4882a593Smuzhiyun if (!chip) {
574*4882a593Smuzhiyun pci_disable_device(pci);
575*4882a593Smuzhiyun return -ENOMEM;
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun spin_lock_init(&chip->reg_lock);
579*4882a593Smuzhiyun mutex_init(&chip->open_mutex);
580*4882a593Smuzhiyun chip->card = card;
581*4882a593Smuzhiyun chip->pci = pci;
582*4882a593Smuzhiyun chip->irq = -1;
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun chip->granularity = granularity[dev];
585*4882a593Smuzhiyun switch (chip->granularity) {
586*4882a593Smuzhiyun case 8:
587*4882a593Smuzhiyun chip->sample_rate_max = 48000;
588*4882a593Smuzhiyun break;
589*4882a593Smuzhiyun case 16:
590*4882a593Smuzhiyun chip->sample_rate_max = 96000;
591*4882a593Smuzhiyun break;
592*4882a593Smuzhiyun case 32:
593*4882a593Smuzhiyun chip->sample_rate_max = 192000;
594*4882a593Smuzhiyun break;
595*4882a593Smuzhiyun default:
596*4882a593Smuzhiyun dev_warn(chip->card->dev,
597*4882a593Smuzhiyun "Invalid granularity %d, reset to %d\n",
598*4882a593Smuzhiyun chip->granularity, LOLA_GRANULARITY_MAX);
599*4882a593Smuzhiyun chip->granularity = LOLA_GRANULARITY_MAX;
600*4882a593Smuzhiyun chip->sample_rate_max = 192000;
601*4882a593Smuzhiyun break;
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun chip->sample_rate_min = sample_rate_min[dev];
604*4882a593Smuzhiyun if (chip->sample_rate_min > chip->sample_rate_max) {
605*4882a593Smuzhiyun dev_warn(chip->card->dev,
606*4882a593Smuzhiyun "Invalid sample_rate_min %d, reset to 16000\n",
607*4882a593Smuzhiyun chip->sample_rate_min);
608*4882a593Smuzhiyun chip->sample_rate_min = 16000;
609*4882a593Smuzhiyun }
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun err = pci_request_regions(pci, DRVNAME);
612*4882a593Smuzhiyun if (err < 0) {
613*4882a593Smuzhiyun kfree(chip);
614*4882a593Smuzhiyun pci_disable_device(pci);
615*4882a593Smuzhiyun return err;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun chip->bar[0].addr = pci_resource_start(pci, 0);
619*4882a593Smuzhiyun chip->bar[0].remap_addr = pci_ioremap_bar(pci, 0);
620*4882a593Smuzhiyun chip->bar[1].addr = pci_resource_start(pci, 2);
621*4882a593Smuzhiyun chip->bar[1].remap_addr = pci_ioremap_bar(pci, 2);
622*4882a593Smuzhiyun if (!chip->bar[0].remap_addr || !chip->bar[1].remap_addr) {
623*4882a593Smuzhiyun dev_err(chip->card->dev, "ioremap error\n");
624*4882a593Smuzhiyun err = -ENXIO;
625*4882a593Smuzhiyun goto errout;
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun pci_set_master(pci);
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun err = reset_controller(chip);
631*4882a593Smuzhiyun if (err < 0)
632*4882a593Smuzhiyun goto errout;
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun if (request_irq(pci->irq, lola_interrupt, IRQF_SHARED,
635*4882a593Smuzhiyun KBUILD_MODNAME, chip)) {
636*4882a593Smuzhiyun dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
637*4882a593Smuzhiyun err = -EBUSY;
638*4882a593Smuzhiyun goto errout;
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun chip->irq = pci->irq;
641*4882a593Smuzhiyun card->sync_irq = chip->irq;
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun dever = lola_readl(chip, BAR1, DEVER);
644*4882a593Smuzhiyun chip->pcm[CAPT].num_streams = (dever >> 0) & 0x3ff;
645*4882a593Smuzhiyun chip->pcm[PLAY].num_streams = (dever >> 10) & 0x3ff;
646*4882a593Smuzhiyun chip->version = (dever >> 24) & 0xff;
647*4882a593Smuzhiyun dev_dbg(chip->card->dev, "streams in=%d, out=%d, version=0x%x\n",
648*4882a593Smuzhiyun chip->pcm[CAPT].num_streams, chip->pcm[PLAY].num_streams,
649*4882a593Smuzhiyun chip->version);
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun /* Test LOLA_BAR1_DEVER */
652*4882a593Smuzhiyun if (chip->pcm[CAPT].num_streams > MAX_STREAM_IN_COUNT ||
653*4882a593Smuzhiyun chip->pcm[PLAY].num_streams > MAX_STREAM_OUT_COUNT ||
654*4882a593Smuzhiyun (!chip->pcm[CAPT].num_streams &&
655*4882a593Smuzhiyun !chip->pcm[PLAY].num_streams)) {
656*4882a593Smuzhiyun dev_err(chip->card->dev, "invalid DEVER = %x\n", dever);
657*4882a593Smuzhiyun err = -EINVAL;
658*4882a593Smuzhiyun goto errout;
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun err = setup_corb_rirb(chip);
662*4882a593Smuzhiyun if (err < 0)
663*4882a593Smuzhiyun goto errout;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
666*4882a593Smuzhiyun if (err < 0) {
667*4882a593Smuzhiyun dev_err(chip->card->dev, "Error creating device [card]!\n");
668*4882a593Smuzhiyun goto errout;
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun strcpy(card->driver, "Lola");
672*4882a593Smuzhiyun strlcpy(card->shortname, "Digigram Lola", sizeof(card->shortname));
673*4882a593Smuzhiyun snprintf(card->longname, sizeof(card->longname),
674*4882a593Smuzhiyun "%s at 0x%lx irq %i",
675*4882a593Smuzhiyun card->shortname, chip->bar[0].addr, chip->irq);
676*4882a593Smuzhiyun strcpy(card->mixername, card->shortname);
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun lola_irq_enable(chip);
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun chip->initialized = 1;
681*4882a593Smuzhiyun *rchip = chip;
682*4882a593Smuzhiyun return 0;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun errout:
685*4882a593Smuzhiyun lola_free(chip);
686*4882a593Smuzhiyun return err;
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun
lola_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)689*4882a593Smuzhiyun static int lola_probe(struct pci_dev *pci,
690*4882a593Smuzhiyun const struct pci_device_id *pci_id)
691*4882a593Smuzhiyun {
692*4882a593Smuzhiyun static int dev;
693*4882a593Smuzhiyun struct snd_card *card;
694*4882a593Smuzhiyun struct lola *chip;
695*4882a593Smuzhiyun int err;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun if (dev >= SNDRV_CARDS)
698*4882a593Smuzhiyun return -ENODEV;
699*4882a593Smuzhiyun if (!enable[dev]) {
700*4882a593Smuzhiyun dev++;
701*4882a593Smuzhiyun return -ENOENT;
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
705*4882a593Smuzhiyun 0, &card);
706*4882a593Smuzhiyun if (err < 0) {
707*4882a593Smuzhiyun dev_err(&pci->dev, "Error creating card!\n");
708*4882a593Smuzhiyun return err;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun err = lola_create(card, pci, dev, &chip);
712*4882a593Smuzhiyun if (err < 0)
713*4882a593Smuzhiyun goto out_free;
714*4882a593Smuzhiyun card->private_data = chip;
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun err = lola_parse_tree(chip);
717*4882a593Smuzhiyun if (err < 0)
718*4882a593Smuzhiyun goto out_free;
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun err = lola_create_pcm(chip);
721*4882a593Smuzhiyun if (err < 0)
722*4882a593Smuzhiyun goto out_free;
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun err = lola_create_mixer(chip);
725*4882a593Smuzhiyun if (err < 0)
726*4882a593Smuzhiyun goto out_free;
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun lola_proc_debug_new(chip);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun err = snd_card_register(card);
731*4882a593Smuzhiyun if (err < 0)
732*4882a593Smuzhiyun goto out_free;
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun pci_set_drvdata(pci, card);
735*4882a593Smuzhiyun dev++;
736*4882a593Smuzhiyun return err;
737*4882a593Smuzhiyun out_free:
738*4882a593Smuzhiyun snd_card_free(card);
739*4882a593Smuzhiyun return err;
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun
lola_remove(struct pci_dev * pci)742*4882a593Smuzhiyun static void lola_remove(struct pci_dev *pci)
743*4882a593Smuzhiyun {
744*4882a593Smuzhiyun snd_card_free(pci_get_drvdata(pci));
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun /* PCI IDs */
748*4882a593Smuzhiyun static const struct pci_device_id lola_ids[] = {
749*4882a593Smuzhiyun { PCI_VDEVICE(DIGIGRAM, 0x0001) },
750*4882a593Smuzhiyun { 0, }
751*4882a593Smuzhiyun };
752*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, lola_ids);
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun /* pci_driver definition */
755*4882a593Smuzhiyun static struct pci_driver lola_driver = {
756*4882a593Smuzhiyun .name = KBUILD_MODNAME,
757*4882a593Smuzhiyun .id_table = lola_ids,
758*4882a593Smuzhiyun .probe = lola_probe,
759*4882a593Smuzhiyun .remove = lola_remove,
760*4882a593Smuzhiyun };
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun module_pci_driver(lola_driver);
763