xref: /OK3568_Linux_fs/kernel/sound/pci/ice1712/wm8766.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *   ALSA driver for ICEnsemble VT17xx
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *   Lowlevel functions for WM8766 codec
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *	Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <sound/core.h>
12*4882a593Smuzhiyun #include <sound/control.h>
13*4882a593Smuzhiyun #include <sound/tlv.h>
14*4882a593Smuzhiyun #include "wm8766.h"
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /* low-level access */
17*4882a593Smuzhiyun 
snd_wm8766_write(struct snd_wm8766 * wm,u16 addr,u16 data)18*4882a593Smuzhiyun static void snd_wm8766_write(struct snd_wm8766 *wm, u16 addr, u16 data)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun 	if (addr < WM8766_REG_COUNT)
21*4882a593Smuzhiyun 		wm->regs[addr] = data;
22*4882a593Smuzhiyun 	wm->ops.write(wm, addr, data);
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /* mixer controls */
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(wm8766_tlv, -12750, 50, 1);
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static const struct snd_wm8766_ctl snd_wm8766_default_ctl[WM8766_CTL_COUNT] = {
30*4882a593Smuzhiyun 	[WM8766_CTL_CH1_VOL] = {
31*4882a593Smuzhiyun 		.name = "Channel 1 Playback Volume",
32*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
33*4882a593Smuzhiyun 		.tlv = wm8766_tlv,
34*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACL1,
35*4882a593Smuzhiyun 		.reg2 = WM8766_REG_DACR1,
36*4882a593Smuzhiyun 		.mask1 = WM8766_VOL_MASK,
37*4882a593Smuzhiyun 		.mask2 = WM8766_VOL_MASK,
38*4882a593Smuzhiyun 		.max = 0xff,
39*4882a593Smuzhiyun 		.flags = WM8766_FLAG_STEREO | WM8766_FLAG_VOL_UPDATE,
40*4882a593Smuzhiyun 	},
41*4882a593Smuzhiyun 	[WM8766_CTL_CH2_VOL] = {
42*4882a593Smuzhiyun 		.name = "Channel 2 Playback Volume",
43*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
44*4882a593Smuzhiyun 		.tlv = wm8766_tlv,
45*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACL2,
46*4882a593Smuzhiyun 		.reg2 = WM8766_REG_DACR2,
47*4882a593Smuzhiyun 		.mask1 = WM8766_VOL_MASK,
48*4882a593Smuzhiyun 		.mask2 = WM8766_VOL_MASK,
49*4882a593Smuzhiyun 		.max = 0xff,
50*4882a593Smuzhiyun 		.flags = WM8766_FLAG_STEREO | WM8766_FLAG_VOL_UPDATE,
51*4882a593Smuzhiyun 	},
52*4882a593Smuzhiyun 	[WM8766_CTL_CH3_VOL] = {
53*4882a593Smuzhiyun 		.name = "Channel 3 Playback Volume",
54*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
55*4882a593Smuzhiyun 		.tlv = wm8766_tlv,
56*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACL3,
57*4882a593Smuzhiyun 		.reg2 = WM8766_REG_DACR3,
58*4882a593Smuzhiyun 		.mask1 = WM8766_VOL_MASK,
59*4882a593Smuzhiyun 		.mask2 = WM8766_VOL_MASK,
60*4882a593Smuzhiyun 		.max = 0xff,
61*4882a593Smuzhiyun 		.flags = WM8766_FLAG_STEREO | WM8766_FLAG_VOL_UPDATE,
62*4882a593Smuzhiyun 	},
63*4882a593Smuzhiyun 	[WM8766_CTL_CH1_SW] = {
64*4882a593Smuzhiyun 		.name = "Channel 1 Playback Switch",
65*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
66*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACCTRL2,
67*4882a593Smuzhiyun 		.mask1 = WM8766_DAC2_MUTE1,
68*4882a593Smuzhiyun 		.flags = WM8766_FLAG_INVERT,
69*4882a593Smuzhiyun 	},
70*4882a593Smuzhiyun 	[WM8766_CTL_CH2_SW] = {
71*4882a593Smuzhiyun 		.name = "Channel 2 Playback Switch",
72*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
73*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACCTRL2,
74*4882a593Smuzhiyun 		.mask1 = WM8766_DAC2_MUTE2,
75*4882a593Smuzhiyun 		.flags = WM8766_FLAG_INVERT,
76*4882a593Smuzhiyun 	},
77*4882a593Smuzhiyun 	[WM8766_CTL_CH3_SW] = {
78*4882a593Smuzhiyun 		.name = "Channel 3 Playback Switch",
79*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
80*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACCTRL2,
81*4882a593Smuzhiyun 		.mask1 = WM8766_DAC2_MUTE3,
82*4882a593Smuzhiyun 		.flags = WM8766_FLAG_INVERT,
83*4882a593Smuzhiyun 	},
84*4882a593Smuzhiyun 	[WM8766_CTL_PHASE1_SW] = {
85*4882a593Smuzhiyun 		.name = "Channel 1 Phase Invert Playback Switch",
86*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
87*4882a593Smuzhiyun 		.reg1 = WM8766_REG_IFCTRL,
88*4882a593Smuzhiyun 		.mask1 = WM8766_PHASE_INVERT1,
89*4882a593Smuzhiyun 	},
90*4882a593Smuzhiyun 	[WM8766_CTL_PHASE2_SW] = {
91*4882a593Smuzhiyun 		.name = "Channel 2 Phase Invert Playback Switch",
92*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
93*4882a593Smuzhiyun 		.reg1 = WM8766_REG_IFCTRL,
94*4882a593Smuzhiyun 		.mask1 = WM8766_PHASE_INVERT2,
95*4882a593Smuzhiyun 	},
96*4882a593Smuzhiyun 	[WM8766_CTL_PHASE3_SW] = {
97*4882a593Smuzhiyun 		.name = "Channel 3 Phase Invert Playback Switch",
98*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
99*4882a593Smuzhiyun 		.reg1 = WM8766_REG_IFCTRL,
100*4882a593Smuzhiyun 		.mask1 = WM8766_PHASE_INVERT3,
101*4882a593Smuzhiyun 	},
102*4882a593Smuzhiyun 	[WM8766_CTL_DEEMPH1_SW] = {
103*4882a593Smuzhiyun 		.name = "Channel 1 Deemphasis Playback Switch",
104*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
105*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACCTRL2,
106*4882a593Smuzhiyun 		.mask1 = WM8766_DAC2_DEEMP1,
107*4882a593Smuzhiyun 	},
108*4882a593Smuzhiyun 	[WM8766_CTL_DEEMPH2_SW] = {
109*4882a593Smuzhiyun 		.name = "Channel 2 Deemphasis Playback Switch",
110*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
111*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACCTRL2,
112*4882a593Smuzhiyun 		.mask1 = WM8766_DAC2_DEEMP2,
113*4882a593Smuzhiyun 	},
114*4882a593Smuzhiyun 	[WM8766_CTL_DEEMPH3_SW] = {
115*4882a593Smuzhiyun 		.name = "Channel 3 Deemphasis Playback Switch",
116*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
117*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACCTRL2,
118*4882a593Smuzhiyun 		.mask1 = WM8766_DAC2_DEEMP3,
119*4882a593Smuzhiyun 	},
120*4882a593Smuzhiyun 	[WM8766_CTL_IZD_SW] = {
121*4882a593Smuzhiyun 		.name = "Infinite Zero Detect Playback Switch",
122*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
123*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACCTRL1,
124*4882a593Smuzhiyun 		.mask1 = WM8766_DAC_IZD,
125*4882a593Smuzhiyun 	},
126*4882a593Smuzhiyun 	[WM8766_CTL_ZC_SW] = {
127*4882a593Smuzhiyun 		.name = "Zero Cross Detect Playback Switch",
128*4882a593Smuzhiyun 		.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
129*4882a593Smuzhiyun 		.reg1 = WM8766_REG_DACCTRL2,
130*4882a593Smuzhiyun 		.mask1 = WM8766_DAC2_ZCD,
131*4882a593Smuzhiyun 		.flags = WM8766_FLAG_INVERT,
132*4882a593Smuzhiyun 	},
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /* exported functions */
136*4882a593Smuzhiyun 
snd_wm8766_init(struct snd_wm8766 * wm)137*4882a593Smuzhiyun void snd_wm8766_init(struct snd_wm8766 *wm)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	int i;
140*4882a593Smuzhiyun 	static const u16 default_values[] = {
141*4882a593Smuzhiyun 		0x000, 0x100,
142*4882a593Smuzhiyun 		0x120, 0x000,
143*4882a593Smuzhiyun 		0x000, 0x100, 0x000, 0x100, 0x000,
144*4882a593Smuzhiyun 		0x000, 0x080,
145*4882a593Smuzhiyun 	};
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	memcpy(wm->ctl, snd_wm8766_default_ctl, sizeof(wm->ctl));
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	snd_wm8766_write(wm, WM8766_REG_RESET, 0x00); /* reset */
150*4882a593Smuzhiyun 	udelay(10);
151*4882a593Smuzhiyun 	/* load defaults */
152*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(default_values); i++)
153*4882a593Smuzhiyun 		snd_wm8766_write(wm, i, default_values[i]);
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
snd_wm8766_resume(struct snd_wm8766 * wm)156*4882a593Smuzhiyun void snd_wm8766_resume(struct snd_wm8766 *wm)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	int i;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	for (i = 0; i < WM8766_REG_COUNT; i++)
161*4882a593Smuzhiyun 		snd_wm8766_write(wm, i, wm->regs[i]);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
snd_wm8766_set_if(struct snd_wm8766 * wm,u16 dac)164*4882a593Smuzhiyun void snd_wm8766_set_if(struct snd_wm8766 *wm, u16 dac)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	u16 val = wm->regs[WM8766_REG_IFCTRL] & ~WM8766_IF_MASK;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	dac &= WM8766_IF_MASK;
169*4882a593Smuzhiyun 	snd_wm8766_write(wm, WM8766_REG_IFCTRL, val | dac);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun 
snd_wm8766_volume_restore(struct snd_wm8766 * wm)172*4882a593Smuzhiyun void snd_wm8766_volume_restore(struct snd_wm8766 *wm)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun 	u16 val = wm->regs[WM8766_REG_DACR1];
175*4882a593Smuzhiyun 	/* restore volume after MCLK stopped */
176*4882a593Smuzhiyun 	snd_wm8766_write(wm, WM8766_REG_DACR1, val | WM8766_VOL_UPDATE);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun /* mixer callbacks */
180*4882a593Smuzhiyun 
snd_wm8766_volume_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)181*4882a593Smuzhiyun static int snd_wm8766_volume_info(struct snd_kcontrol *kcontrol,
182*4882a593Smuzhiyun 				   struct snd_ctl_elem_info *uinfo)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun 	struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol);
185*4882a593Smuzhiyun 	int n = kcontrol->private_value;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
188*4882a593Smuzhiyun 	uinfo->count = (wm->ctl[n].flags & WM8766_FLAG_STEREO) ? 2 : 1;
189*4882a593Smuzhiyun 	uinfo->value.integer.min = wm->ctl[n].min;
190*4882a593Smuzhiyun 	uinfo->value.integer.max = wm->ctl[n].max;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	return 0;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun 
snd_wm8766_enum_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)195*4882a593Smuzhiyun static int snd_wm8766_enum_info(struct snd_kcontrol *kcontrol,
196*4882a593Smuzhiyun 				      struct snd_ctl_elem_info *uinfo)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun 	struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol);
199*4882a593Smuzhiyun 	int n = kcontrol->private_value;
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	return snd_ctl_enum_info(uinfo, 1, wm->ctl[n].max,
202*4882a593Smuzhiyun 						wm->ctl[n].enum_names);
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
snd_wm8766_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)205*4882a593Smuzhiyun static int snd_wm8766_ctl_get(struct snd_kcontrol *kcontrol,
206*4882a593Smuzhiyun 				  struct snd_ctl_elem_value *ucontrol)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun 	struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol);
209*4882a593Smuzhiyun 	int n = kcontrol->private_value;
210*4882a593Smuzhiyun 	u16 val1, val2;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	if (wm->ctl[n].get)
213*4882a593Smuzhiyun 		wm->ctl[n].get(wm, &val1, &val2);
214*4882a593Smuzhiyun 	else {
215*4882a593Smuzhiyun 		val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1;
216*4882a593Smuzhiyun 		val1 >>= __ffs(wm->ctl[n].mask1);
217*4882a593Smuzhiyun 		if (wm->ctl[n].flags & WM8766_FLAG_STEREO) {
218*4882a593Smuzhiyun 			val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2;
219*4882a593Smuzhiyun 			val2 >>= __ffs(wm->ctl[n].mask2);
220*4882a593Smuzhiyun 			if (wm->ctl[n].flags & WM8766_FLAG_VOL_UPDATE)
221*4882a593Smuzhiyun 				val2 &= ~WM8766_VOL_UPDATE;
222*4882a593Smuzhiyun 		}
223*4882a593Smuzhiyun 	}
224*4882a593Smuzhiyun 	if (wm->ctl[n].flags & WM8766_FLAG_INVERT) {
225*4882a593Smuzhiyun 		val1 = wm->ctl[n].max - (val1 - wm->ctl[n].min);
226*4882a593Smuzhiyun 		if (wm->ctl[n].flags & WM8766_FLAG_STEREO)
227*4882a593Smuzhiyun 			val2 = wm->ctl[n].max - (val2 - wm->ctl[n].min);
228*4882a593Smuzhiyun 	}
229*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = val1;
230*4882a593Smuzhiyun 	if (wm->ctl[n].flags & WM8766_FLAG_STEREO)
231*4882a593Smuzhiyun 		ucontrol->value.integer.value[1] = val2;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	return 0;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun 
snd_wm8766_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)236*4882a593Smuzhiyun static int snd_wm8766_ctl_put(struct snd_kcontrol *kcontrol,
237*4882a593Smuzhiyun 				  struct snd_ctl_elem_value *ucontrol)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol);
240*4882a593Smuzhiyun 	int n = kcontrol->private_value;
241*4882a593Smuzhiyun 	u16 val, regval1, regval2;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	/* this also works for enum because value is a union */
244*4882a593Smuzhiyun 	regval1 = ucontrol->value.integer.value[0];
245*4882a593Smuzhiyun 	regval2 = ucontrol->value.integer.value[1];
246*4882a593Smuzhiyun 	if (wm->ctl[n].flags & WM8766_FLAG_INVERT) {
247*4882a593Smuzhiyun 		regval1 = wm->ctl[n].max - (regval1 - wm->ctl[n].min);
248*4882a593Smuzhiyun 		regval2 = wm->ctl[n].max - (regval2 - wm->ctl[n].min);
249*4882a593Smuzhiyun 	}
250*4882a593Smuzhiyun 	if (wm->ctl[n].set)
251*4882a593Smuzhiyun 		wm->ctl[n].set(wm, regval1, regval2);
252*4882a593Smuzhiyun 	else {
253*4882a593Smuzhiyun 		val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1;
254*4882a593Smuzhiyun 		val |= regval1 << __ffs(wm->ctl[n].mask1);
255*4882a593Smuzhiyun 		/* both stereo controls in one register */
256*4882a593Smuzhiyun 		if (wm->ctl[n].flags & WM8766_FLAG_STEREO &&
257*4882a593Smuzhiyun 				wm->ctl[n].reg1 == wm->ctl[n].reg2) {
258*4882a593Smuzhiyun 			val &= ~wm->ctl[n].mask2;
259*4882a593Smuzhiyun 			val |= regval2 << __ffs(wm->ctl[n].mask2);
260*4882a593Smuzhiyun 		}
261*4882a593Smuzhiyun 		snd_wm8766_write(wm, wm->ctl[n].reg1, val);
262*4882a593Smuzhiyun 		/* stereo controls in different registers */
263*4882a593Smuzhiyun 		if (wm->ctl[n].flags & WM8766_FLAG_STEREO &&
264*4882a593Smuzhiyun 				wm->ctl[n].reg1 != wm->ctl[n].reg2) {
265*4882a593Smuzhiyun 			val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2;
266*4882a593Smuzhiyun 			val |= regval2 << __ffs(wm->ctl[n].mask2);
267*4882a593Smuzhiyun 			if (wm->ctl[n].flags & WM8766_FLAG_VOL_UPDATE)
268*4882a593Smuzhiyun 				val |= WM8766_VOL_UPDATE;
269*4882a593Smuzhiyun 			snd_wm8766_write(wm, wm->ctl[n].reg2, val);
270*4882a593Smuzhiyun 		}
271*4882a593Smuzhiyun 	}
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	return 0;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun 
snd_wm8766_add_control(struct snd_wm8766 * wm,int num)276*4882a593Smuzhiyun static int snd_wm8766_add_control(struct snd_wm8766 *wm, int num)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun 	struct snd_kcontrol_new cont;
279*4882a593Smuzhiyun 	struct snd_kcontrol *ctl;
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	memset(&cont, 0, sizeof(cont));
282*4882a593Smuzhiyun 	cont.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
283*4882a593Smuzhiyun 	cont.private_value = num;
284*4882a593Smuzhiyun 	cont.name = wm->ctl[num].name;
285*4882a593Smuzhiyun 	cont.access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
286*4882a593Smuzhiyun 	if (wm->ctl[num].flags & WM8766_FLAG_LIM ||
287*4882a593Smuzhiyun 	    wm->ctl[num].flags & WM8766_FLAG_ALC)
288*4882a593Smuzhiyun 		cont.access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
289*4882a593Smuzhiyun 	cont.tlv.p = NULL;
290*4882a593Smuzhiyun 	cont.get = snd_wm8766_ctl_get;
291*4882a593Smuzhiyun 	cont.put = snd_wm8766_ctl_put;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	switch (wm->ctl[num].type) {
294*4882a593Smuzhiyun 	case SNDRV_CTL_ELEM_TYPE_INTEGER:
295*4882a593Smuzhiyun 		cont.info = snd_wm8766_volume_info;
296*4882a593Smuzhiyun 		cont.access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ;
297*4882a593Smuzhiyun 		cont.tlv.p = wm->ctl[num].tlv;
298*4882a593Smuzhiyun 		break;
299*4882a593Smuzhiyun 	case SNDRV_CTL_ELEM_TYPE_BOOLEAN:
300*4882a593Smuzhiyun 		wm->ctl[num].max = 1;
301*4882a593Smuzhiyun 		if (wm->ctl[num].flags & WM8766_FLAG_STEREO)
302*4882a593Smuzhiyun 			cont.info = snd_ctl_boolean_stereo_info;
303*4882a593Smuzhiyun 		else
304*4882a593Smuzhiyun 			cont.info = snd_ctl_boolean_mono_info;
305*4882a593Smuzhiyun 		break;
306*4882a593Smuzhiyun 	case SNDRV_CTL_ELEM_TYPE_ENUMERATED:
307*4882a593Smuzhiyun 		cont.info = snd_wm8766_enum_info;
308*4882a593Smuzhiyun 		break;
309*4882a593Smuzhiyun 	default:
310*4882a593Smuzhiyun 		return -EINVAL;
311*4882a593Smuzhiyun 	}
312*4882a593Smuzhiyun 	ctl = snd_ctl_new1(&cont, wm);
313*4882a593Smuzhiyun 	if (!ctl)
314*4882a593Smuzhiyun 		return -ENOMEM;
315*4882a593Smuzhiyun 	wm->ctl[num].kctl = ctl;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	return snd_ctl_add(wm->card, ctl);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun 
snd_wm8766_build_controls(struct snd_wm8766 * wm)320*4882a593Smuzhiyun int snd_wm8766_build_controls(struct snd_wm8766 *wm)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun 	int err, i;
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	for (i = 0; i < WM8766_CTL_COUNT; i++)
325*4882a593Smuzhiyun 		if (wm->ctl[i].name) {
326*4882a593Smuzhiyun 			err = snd_wm8766_add_control(wm, i);
327*4882a593Smuzhiyun 			if (err < 0)
328*4882a593Smuzhiyun 				return err;
329*4882a593Smuzhiyun 		}
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	return 0;
332*4882a593Smuzhiyun }
333