1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ALSA driver for ICEnsemble VT1724 (Envy24HT)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Lowlevel functions for Audiotrak Prodigy 7.1 Hifi
6*4882a593Smuzhiyun * based on pontis.c
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright (c) 2007 Julian Scheel <julian@jusst.de>
9*4882a593Smuzhiyun * Copyright (c) 2007 allank
10*4882a593Smuzhiyun * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/mutex.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <sound/core.h>
21*4882a593Smuzhiyun #include <sound/info.h>
22*4882a593Smuzhiyun #include <sound/tlv.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "ice1712.h"
25*4882a593Smuzhiyun #include "envy24ht.h"
26*4882a593Smuzhiyun #include "prodigy_hifi.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun struct prodigy_hifi_spec {
29*4882a593Smuzhiyun unsigned short master[2];
30*4882a593Smuzhiyun unsigned short vol[8];
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* I2C addresses */
34*4882a593Smuzhiyun #define WM_DEV 0x34
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* WM8776 registers */
37*4882a593Smuzhiyun #define WM_HP_ATTEN_L 0x00 /* headphone left attenuation */
38*4882a593Smuzhiyun #define WM_HP_ATTEN_R 0x01 /* headphone left attenuation */
39*4882a593Smuzhiyun #define WM_HP_MASTER 0x02 /* headphone master (both channels),
40*4882a593Smuzhiyun override LLR */
41*4882a593Smuzhiyun #define WM_DAC_ATTEN_L 0x03 /* digital left attenuation */
42*4882a593Smuzhiyun #define WM_DAC_ATTEN_R 0x04
43*4882a593Smuzhiyun #define WM_DAC_MASTER 0x05
44*4882a593Smuzhiyun #define WM_PHASE_SWAP 0x06 /* DAC phase swap */
45*4882a593Smuzhiyun #define WM_DAC_CTRL1 0x07
46*4882a593Smuzhiyun #define WM_DAC_MUTE 0x08
47*4882a593Smuzhiyun #define WM_DAC_CTRL2 0x09
48*4882a593Smuzhiyun #define WM_DAC_INT 0x0a
49*4882a593Smuzhiyun #define WM_ADC_INT 0x0b
50*4882a593Smuzhiyun #define WM_MASTER_CTRL 0x0c
51*4882a593Smuzhiyun #define WM_POWERDOWN 0x0d
52*4882a593Smuzhiyun #define WM_ADC_ATTEN_L 0x0e
53*4882a593Smuzhiyun #define WM_ADC_ATTEN_R 0x0f
54*4882a593Smuzhiyun #define WM_ALC_CTRL1 0x10
55*4882a593Smuzhiyun #define WM_ALC_CTRL2 0x11
56*4882a593Smuzhiyun #define WM_ALC_CTRL3 0x12
57*4882a593Smuzhiyun #define WM_NOISE_GATE 0x13
58*4882a593Smuzhiyun #define WM_LIMITER 0x14
59*4882a593Smuzhiyun #define WM_ADC_MUX 0x15
60*4882a593Smuzhiyun #define WM_OUT_MUX 0x16
61*4882a593Smuzhiyun #define WM_RESET 0x17
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Analog Recording Source :- Mic, LineIn, CD/Video, */
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* implement capture source select control for WM8776 */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define WM_AIN1 "AIN1"
68*4882a593Smuzhiyun #define WM_AIN2 "AIN2"
69*4882a593Smuzhiyun #define WM_AIN3 "AIN3"
70*4882a593Smuzhiyun #define WM_AIN4 "AIN4"
71*4882a593Smuzhiyun #define WM_AIN5 "AIN5"
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* GPIO pins of envy24ht connected to wm8766 */
74*4882a593Smuzhiyun #define WM8766_SPI_CLK (1<<17) /* CLK, Pin97 on ICE1724 */
75*4882a593Smuzhiyun #define WM8766_SPI_MD (1<<16) /* DATA VT1724 -> WM8766, Pin96 */
76*4882a593Smuzhiyun #define WM8766_SPI_ML (1<<18) /* Latch, Pin98 */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* WM8766 registers */
79*4882a593Smuzhiyun #define WM8766_DAC_CTRL 0x02 /* DAC Control */
80*4882a593Smuzhiyun #define WM8766_INT_CTRL 0x03 /* Interface Control */
81*4882a593Smuzhiyun #define WM8766_DAC_CTRL2 0x09
82*4882a593Smuzhiyun #define WM8766_DAC_CTRL3 0x0a
83*4882a593Smuzhiyun #define WM8766_RESET 0x1f
84*4882a593Smuzhiyun #define WM8766_LDA1 0x00
85*4882a593Smuzhiyun #define WM8766_LDA2 0x04
86*4882a593Smuzhiyun #define WM8766_LDA3 0x06
87*4882a593Smuzhiyun #define WM8766_RDA1 0x01
88*4882a593Smuzhiyun #define WM8766_RDA2 0x05
89*4882a593Smuzhiyun #define WM8766_RDA3 0x07
90*4882a593Smuzhiyun #define WM8766_MUTE1 0x0C
91*4882a593Smuzhiyun #define WM8766_MUTE2 0x0F
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /*
95*4882a593Smuzhiyun * Prodigy HD2
96*4882a593Smuzhiyun */
97*4882a593Smuzhiyun #define AK4396_ADDR 0x00
98*4882a593Smuzhiyun #define AK4396_CSN (1 << 8) /* CSN->GPIO8, pin 75 */
99*4882a593Smuzhiyun #define AK4396_CCLK (1 << 9) /* CCLK->GPIO9, pin 76 */
100*4882a593Smuzhiyun #define AK4396_CDTI (1 << 10) /* CDTI->GPIO10, pin 77 */
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* ak4396 registers */
103*4882a593Smuzhiyun #define AK4396_CTRL1 0x00
104*4882a593Smuzhiyun #define AK4396_CTRL2 0x01
105*4882a593Smuzhiyun #define AK4396_CTRL3 0x02
106*4882a593Smuzhiyun #define AK4396_LCH_ATT 0x03
107*4882a593Smuzhiyun #define AK4396_RCH_ATT 0x04
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /*
111*4882a593Smuzhiyun * get the current register value of WM codec
112*4882a593Smuzhiyun */
wm_get(struct snd_ice1712 * ice,int reg)113*4882a593Smuzhiyun static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun reg <<= 1;
116*4882a593Smuzhiyun return ((unsigned short)ice->akm[0].images[reg] << 8) |
117*4882a593Smuzhiyun ice->akm[0].images[reg + 1];
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /*
121*4882a593Smuzhiyun * set the register value of WM codec and remember it
122*4882a593Smuzhiyun */
wm_put_nocache(struct snd_ice1712 * ice,int reg,unsigned short val)123*4882a593Smuzhiyun static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun unsigned short cval;
126*4882a593Smuzhiyun cval = (reg << 9) | val;
127*4882a593Smuzhiyun snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
wm_put(struct snd_ice1712 * ice,int reg,unsigned short val)130*4882a593Smuzhiyun static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun wm_put_nocache(ice, reg, val);
133*4882a593Smuzhiyun reg <<= 1;
134*4882a593Smuzhiyun ice->akm[0].images[reg] = val >> 8;
135*4882a593Smuzhiyun ice->akm[0].images[reg + 1] = val;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /*
139*4882a593Smuzhiyun * write data in the SPI mode
140*4882a593Smuzhiyun */
141*4882a593Smuzhiyun
set_gpio_bit(struct snd_ice1712 * ice,unsigned int bit,int val)142*4882a593Smuzhiyun static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun unsigned int tmp = snd_ice1712_gpio_read(ice);
145*4882a593Smuzhiyun if (val)
146*4882a593Smuzhiyun tmp |= bit;
147*4882a593Smuzhiyun else
148*4882a593Smuzhiyun tmp &= ~bit;
149*4882a593Smuzhiyun snd_ice1712_gpio_write(ice, tmp);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /*
153*4882a593Smuzhiyun * SPI implementation for WM8766 codec - only writing supported, no readback
154*4882a593Smuzhiyun */
155*4882a593Smuzhiyun
wm8766_spi_send_word(struct snd_ice1712 * ice,unsigned int data)156*4882a593Smuzhiyun static void wm8766_spi_send_word(struct snd_ice1712 *ice, unsigned int data)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun int i;
159*4882a593Smuzhiyun for (i = 0; i < 16; i++) {
160*4882a593Smuzhiyun set_gpio_bit(ice, WM8766_SPI_CLK, 0);
161*4882a593Smuzhiyun udelay(1);
162*4882a593Smuzhiyun set_gpio_bit(ice, WM8766_SPI_MD, data & 0x8000);
163*4882a593Smuzhiyun udelay(1);
164*4882a593Smuzhiyun set_gpio_bit(ice, WM8766_SPI_CLK, 1);
165*4882a593Smuzhiyun udelay(1);
166*4882a593Smuzhiyun data <<= 1;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
wm8766_spi_write(struct snd_ice1712 * ice,unsigned int reg,unsigned int data)170*4882a593Smuzhiyun static void wm8766_spi_write(struct snd_ice1712 *ice, unsigned int reg,
171*4882a593Smuzhiyun unsigned int data)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun unsigned int block;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun snd_ice1712_gpio_set_dir(ice, WM8766_SPI_MD|
176*4882a593Smuzhiyun WM8766_SPI_CLK|WM8766_SPI_ML);
177*4882a593Smuzhiyun snd_ice1712_gpio_set_mask(ice, ~(WM8766_SPI_MD|
178*4882a593Smuzhiyun WM8766_SPI_CLK|WM8766_SPI_ML));
179*4882a593Smuzhiyun /* latch must be low when writing */
180*4882a593Smuzhiyun set_gpio_bit(ice, WM8766_SPI_ML, 0);
181*4882a593Smuzhiyun block = (reg << 9) | (data & 0x1ff);
182*4882a593Smuzhiyun wm8766_spi_send_word(ice, block); /* REGISTER ADDRESS */
183*4882a593Smuzhiyun /* release latch */
184*4882a593Smuzhiyun set_gpio_bit(ice, WM8766_SPI_ML, 1);
185*4882a593Smuzhiyun udelay(1);
186*4882a593Smuzhiyun /* restore */
187*4882a593Smuzhiyun snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
188*4882a593Smuzhiyun snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /*
193*4882a593Smuzhiyun * serial interface for ak4396 - only writing supported, no readback
194*4882a593Smuzhiyun */
195*4882a593Smuzhiyun
ak4396_send_word(struct snd_ice1712 * ice,unsigned int data)196*4882a593Smuzhiyun static void ak4396_send_word(struct snd_ice1712 *ice, unsigned int data)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun int i;
199*4882a593Smuzhiyun for (i = 0; i < 16; i++) {
200*4882a593Smuzhiyun set_gpio_bit(ice, AK4396_CCLK, 0);
201*4882a593Smuzhiyun udelay(1);
202*4882a593Smuzhiyun set_gpio_bit(ice, AK4396_CDTI, data & 0x8000);
203*4882a593Smuzhiyun udelay(1);
204*4882a593Smuzhiyun set_gpio_bit(ice, AK4396_CCLK, 1);
205*4882a593Smuzhiyun udelay(1);
206*4882a593Smuzhiyun data <<= 1;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
ak4396_write(struct snd_ice1712 * ice,unsigned int reg,unsigned int data)210*4882a593Smuzhiyun static void ak4396_write(struct snd_ice1712 *ice, unsigned int reg,
211*4882a593Smuzhiyun unsigned int data)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun unsigned int block;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun snd_ice1712_gpio_set_dir(ice, AK4396_CSN|AK4396_CCLK|AK4396_CDTI);
216*4882a593Smuzhiyun snd_ice1712_gpio_set_mask(ice, ~(AK4396_CSN|AK4396_CCLK|AK4396_CDTI));
217*4882a593Smuzhiyun /* latch must be low when writing */
218*4882a593Smuzhiyun set_gpio_bit(ice, AK4396_CSN, 0);
219*4882a593Smuzhiyun block = ((AK4396_ADDR & 0x03) << 14) | (1 << 13) |
220*4882a593Smuzhiyun ((reg & 0x1f) << 8) | (data & 0xff);
221*4882a593Smuzhiyun ak4396_send_word(ice, block); /* REGISTER ADDRESS */
222*4882a593Smuzhiyun /* release latch */
223*4882a593Smuzhiyun set_gpio_bit(ice, AK4396_CSN, 1);
224*4882a593Smuzhiyun udelay(1);
225*4882a593Smuzhiyun /* restore */
226*4882a593Smuzhiyun snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
227*4882a593Smuzhiyun snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /*
232*4882a593Smuzhiyun * ak4396 mixers
233*4882a593Smuzhiyun */
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /*
238*4882a593Smuzhiyun * DAC volume attenuation mixer control (-64dB to 0dB)
239*4882a593Smuzhiyun */
240*4882a593Smuzhiyun
ak4396_dac_vol_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)241*4882a593Smuzhiyun static int ak4396_dac_vol_info(struct snd_kcontrol *kcontrol,
242*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
245*4882a593Smuzhiyun uinfo->count = 2;
246*4882a593Smuzhiyun uinfo->value.integer.min = 0; /* mute */
247*4882a593Smuzhiyun uinfo->value.integer.max = 0xFF; /* linear */
248*4882a593Smuzhiyun return 0;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
ak4396_dac_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)251*4882a593Smuzhiyun static int ak4396_dac_vol_get(struct snd_kcontrol *kcontrol,
252*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
255*4882a593Smuzhiyun struct prodigy_hifi_spec *spec = ice->spec;
256*4882a593Smuzhiyun int i;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun for (i = 0; i < 2; i++)
259*4882a593Smuzhiyun ucontrol->value.integer.value[i] = spec->vol[i];
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun return 0;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
ak4396_dac_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)264*4882a593Smuzhiyun static int ak4396_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
267*4882a593Smuzhiyun struct prodigy_hifi_spec *spec = ice->spec;
268*4882a593Smuzhiyun int i;
269*4882a593Smuzhiyun int change = 0;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
272*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
273*4882a593Smuzhiyun if (ucontrol->value.integer.value[i] != spec->vol[i]) {
274*4882a593Smuzhiyun spec->vol[i] = ucontrol->value.integer.value[i];
275*4882a593Smuzhiyun ak4396_write(ice, AK4396_LCH_ATT + i,
276*4882a593Smuzhiyun spec->vol[i] & 0xff);
277*4882a593Smuzhiyun change = 1;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
281*4882a593Smuzhiyun return change;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
285*4882a593Smuzhiyun static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun static const struct snd_kcontrol_new prodigy_hd2_controls[] = {
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
290*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
291*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
292*4882a593Smuzhiyun .name = "Front Playback Volume",
293*4882a593Smuzhiyun .info = ak4396_dac_vol_info,
294*4882a593Smuzhiyun .get = ak4396_dac_vol_get,
295*4882a593Smuzhiyun .put = ak4396_dac_vol_put,
296*4882a593Smuzhiyun .tlv = { .p = ak4396_db_scale },
297*4882a593Smuzhiyun },
298*4882a593Smuzhiyun };
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun /* --------------- */
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun #define WM_VOL_MAX 255
304*4882a593Smuzhiyun #define WM_VOL_MUTE 0x8000
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun #define DAC_0dB 0xff
308*4882a593Smuzhiyun #define DAC_RES 128
309*4882a593Smuzhiyun #define DAC_MIN (DAC_0dB - DAC_RES)
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun
wm_set_vol(struct snd_ice1712 * ice,unsigned int index,unsigned short vol,unsigned short master)312*4882a593Smuzhiyun static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index,
313*4882a593Smuzhiyun unsigned short vol, unsigned short master)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun unsigned char nvol;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
318*4882a593Smuzhiyun nvol = 0;
319*4882a593Smuzhiyun else {
320*4882a593Smuzhiyun nvol = (((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 128)
321*4882a593Smuzhiyun & WM_VOL_MAX;
322*4882a593Smuzhiyun nvol = (nvol ? (nvol + DAC_MIN) : 0) & 0xff;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun wm_put(ice, index, nvol);
326*4882a593Smuzhiyun wm_put_nocache(ice, index, 0x100 | nvol);
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
wm8766_set_vol(struct snd_ice1712 * ice,unsigned int index,unsigned short vol,unsigned short master)329*4882a593Smuzhiyun static void wm8766_set_vol(struct snd_ice1712 *ice, unsigned int index,
330*4882a593Smuzhiyun unsigned short vol, unsigned short master)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun unsigned char nvol;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
335*4882a593Smuzhiyun nvol = 0;
336*4882a593Smuzhiyun else {
337*4882a593Smuzhiyun nvol = (((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 128)
338*4882a593Smuzhiyun & WM_VOL_MAX;
339*4882a593Smuzhiyun nvol = (nvol ? (nvol + DAC_MIN) : 0) & 0xff;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun wm8766_spi_write(ice, index, (0x0100 | nvol));
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun /*
347*4882a593Smuzhiyun * DAC volume attenuation mixer control (-64dB to 0dB)
348*4882a593Smuzhiyun */
349*4882a593Smuzhiyun
wm_dac_vol_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)350*4882a593Smuzhiyun static int wm_dac_vol_info(struct snd_kcontrol *kcontrol,
351*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
354*4882a593Smuzhiyun uinfo->count = 2;
355*4882a593Smuzhiyun uinfo->value.integer.min = 0; /* mute */
356*4882a593Smuzhiyun uinfo->value.integer.max = DAC_RES; /* 0dB, 0.5dB step */
357*4882a593Smuzhiyun return 0;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
wm_dac_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)360*4882a593Smuzhiyun static int wm_dac_vol_get(struct snd_kcontrol *kcontrol,
361*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
364*4882a593Smuzhiyun struct prodigy_hifi_spec *spec = ice->spec;
365*4882a593Smuzhiyun int i;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun for (i = 0; i < 2; i++)
368*4882a593Smuzhiyun ucontrol->value.integer.value[i] =
369*4882a593Smuzhiyun spec->vol[2 + i] & ~WM_VOL_MUTE;
370*4882a593Smuzhiyun return 0;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
wm_dac_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)373*4882a593Smuzhiyun static int wm_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
376*4882a593Smuzhiyun struct prodigy_hifi_spec *spec = ice->spec;
377*4882a593Smuzhiyun int i, idx, change = 0;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
380*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
381*4882a593Smuzhiyun if (ucontrol->value.integer.value[i] != spec->vol[2 + i]) {
382*4882a593Smuzhiyun idx = WM_DAC_ATTEN_L + i;
383*4882a593Smuzhiyun spec->vol[2 + i] &= WM_VOL_MUTE;
384*4882a593Smuzhiyun spec->vol[2 + i] |= ucontrol->value.integer.value[i];
385*4882a593Smuzhiyun wm_set_vol(ice, idx, spec->vol[2 + i], spec->master[i]);
386*4882a593Smuzhiyun change = 1;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
390*4882a593Smuzhiyun return change;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun /*
395*4882a593Smuzhiyun * WM8766 DAC volume attenuation mixer control
396*4882a593Smuzhiyun */
wm8766_vol_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)397*4882a593Smuzhiyun static int wm8766_vol_info(struct snd_kcontrol *kcontrol,
398*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
399*4882a593Smuzhiyun {
400*4882a593Smuzhiyun int voices = kcontrol->private_value >> 8;
401*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
402*4882a593Smuzhiyun uinfo->count = voices;
403*4882a593Smuzhiyun uinfo->value.integer.min = 0; /* mute */
404*4882a593Smuzhiyun uinfo->value.integer.max = DAC_RES; /* 0dB */
405*4882a593Smuzhiyun return 0;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
wm8766_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)408*4882a593Smuzhiyun static int wm8766_vol_get(struct snd_kcontrol *kcontrol,
409*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
412*4882a593Smuzhiyun struct prodigy_hifi_spec *spec = ice->spec;
413*4882a593Smuzhiyun int i, ofs, voices;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun voices = kcontrol->private_value >> 8;
416*4882a593Smuzhiyun ofs = kcontrol->private_value & 0xff;
417*4882a593Smuzhiyun for (i = 0; i < voices; i++)
418*4882a593Smuzhiyun ucontrol->value.integer.value[i] = spec->vol[ofs + i];
419*4882a593Smuzhiyun return 0;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun
wm8766_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)422*4882a593Smuzhiyun static int wm8766_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
423*4882a593Smuzhiyun {
424*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
425*4882a593Smuzhiyun struct prodigy_hifi_spec *spec = ice->spec;
426*4882a593Smuzhiyun int i, idx, ofs, voices;
427*4882a593Smuzhiyun int change = 0;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun voices = kcontrol->private_value >> 8;
430*4882a593Smuzhiyun ofs = kcontrol->private_value & 0xff;
431*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
432*4882a593Smuzhiyun for (i = 0; i < voices; i++) {
433*4882a593Smuzhiyun if (ucontrol->value.integer.value[i] != spec->vol[ofs + i]) {
434*4882a593Smuzhiyun idx = WM8766_LDA1 + ofs + i;
435*4882a593Smuzhiyun spec->vol[ofs + i] &= WM_VOL_MUTE;
436*4882a593Smuzhiyun spec->vol[ofs + i] |= ucontrol->value.integer.value[i];
437*4882a593Smuzhiyun wm8766_set_vol(ice, idx,
438*4882a593Smuzhiyun spec->vol[ofs + i], spec->master[i]);
439*4882a593Smuzhiyun change = 1;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
443*4882a593Smuzhiyun return change;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun /*
447*4882a593Smuzhiyun * Master volume attenuation mixer control / applied to WM8776+WM8766
448*4882a593Smuzhiyun */
wm_master_vol_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)449*4882a593Smuzhiyun static int wm_master_vol_info(struct snd_kcontrol *kcontrol,
450*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
453*4882a593Smuzhiyun uinfo->count = 2;
454*4882a593Smuzhiyun uinfo->value.integer.min = 0;
455*4882a593Smuzhiyun uinfo->value.integer.max = DAC_RES;
456*4882a593Smuzhiyun return 0;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
wm_master_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)459*4882a593Smuzhiyun static int wm_master_vol_get(struct snd_kcontrol *kcontrol,
460*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
461*4882a593Smuzhiyun {
462*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
463*4882a593Smuzhiyun struct prodigy_hifi_spec *spec = ice->spec;
464*4882a593Smuzhiyun int i;
465*4882a593Smuzhiyun for (i = 0; i < 2; i++)
466*4882a593Smuzhiyun ucontrol->value.integer.value[i] = spec->master[i];
467*4882a593Smuzhiyun return 0;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
wm_master_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)470*4882a593Smuzhiyun static int wm_master_vol_put(struct snd_kcontrol *kcontrol,
471*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
472*4882a593Smuzhiyun {
473*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
474*4882a593Smuzhiyun struct prodigy_hifi_spec *spec = ice->spec;
475*4882a593Smuzhiyun int ch, change = 0;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
478*4882a593Smuzhiyun for (ch = 0; ch < 2; ch++) {
479*4882a593Smuzhiyun if (ucontrol->value.integer.value[ch] != spec->master[ch]) {
480*4882a593Smuzhiyun spec->master[ch] = ucontrol->value.integer.value[ch];
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun /* Apply to front DAC */
483*4882a593Smuzhiyun wm_set_vol(ice, WM_DAC_ATTEN_L + ch,
484*4882a593Smuzhiyun spec->vol[2 + ch], spec->master[ch]);
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun wm8766_set_vol(ice, WM8766_LDA1 + ch,
487*4882a593Smuzhiyun spec->vol[0 + ch], spec->master[ch]);
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun wm8766_set_vol(ice, WM8766_LDA2 + ch,
490*4882a593Smuzhiyun spec->vol[4 + ch], spec->master[ch]);
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun wm8766_set_vol(ice, WM8766_LDA3 + ch,
493*4882a593Smuzhiyun spec->vol[6 + ch], spec->master[ch]);
494*4882a593Smuzhiyun change = 1;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
498*4882a593Smuzhiyun return change;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun /* KONSTI */
503*4882a593Smuzhiyun
wm_adc_mux_enum_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)504*4882a593Smuzhiyun static int wm_adc_mux_enum_info(struct snd_kcontrol *kcontrol,
505*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
506*4882a593Smuzhiyun {
507*4882a593Smuzhiyun static const char * const texts[32] = {
508*4882a593Smuzhiyun "NULL", WM_AIN1, WM_AIN2, WM_AIN1 "+" WM_AIN2,
509*4882a593Smuzhiyun WM_AIN3, WM_AIN1 "+" WM_AIN3, WM_AIN2 "+" WM_AIN3,
510*4882a593Smuzhiyun WM_AIN1 "+" WM_AIN2 "+" WM_AIN3,
511*4882a593Smuzhiyun WM_AIN4, WM_AIN1 "+" WM_AIN4, WM_AIN2 "+" WM_AIN4,
512*4882a593Smuzhiyun WM_AIN1 "+" WM_AIN2 "+" WM_AIN4,
513*4882a593Smuzhiyun WM_AIN3 "+" WM_AIN4, WM_AIN1 "+" WM_AIN3 "+" WM_AIN4,
514*4882a593Smuzhiyun WM_AIN2 "+" WM_AIN3 "+" WM_AIN4,
515*4882a593Smuzhiyun WM_AIN1 "+" WM_AIN2 "+" WM_AIN3 "+" WM_AIN4,
516*4882a593Smuzhiyun WM_AIN5, WM_AIN1 "+" WM_AIN5, WM_AIN2 "+" WM_AIN5,
517*4882a593Smuzhiyun WM_AIN1 "+" WM_AIN2 "+" WM_AIN5,
518*4882a593Smuzhiyun WM_AIN3 "+" WM_AIN5, WM_AIN1 "+" WM_AIN3 "+" WM_AIN5,
519*4882a593Smuzhiyun WM_AIN2 "+" WM_AIN3 "+" WM_AIN5,
520*4882a593Smuzhiyun WM_AIN1 "+" WM_AIN2 "+" WM_AIN3 "+" WM_AIN5,
521*4882a593Smuzhiyun WM_AIN4 "+" WM_AIN5, WM_AIN1 "+" WM_AIN4 "+" WM_AIN5,
522*4882a593Smuzhiyun WM_AIN2 "+" WM_AIN4 "+" WM_AIN5,
523*4882a593Smuzhiyun WM_AIN1 "+" WM_AIN2 "+" WM_AIN4 "+" WM_AIN5,
524*4882a593Smuzhiyun WM_AIN3 "+" WM_AIN4 "+" WM_AIN5,
525*4882a593Smuzhiyun WM_AIN1 "+" WM_AIN3 "+" WM_AIN4 "+" WM_AIN5,
526*4882a593Smuzhiyun WM_AIN2 "+" WM_AIN3 "+" WM_AIN4 "+" WM_AIN5,
527*4882a593Smuzhiyun WM_AIN1 "+" WM_AIN2 "+" WM_AIN3 "+" WM_AIN4 "+" WM_AIN5
528*4882a593Smuzhiyun };
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun return snd_ctl_enum_info(uinfo, 1, 32, texts);
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun
wm_adc_mux_enum_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)533*4882a593Smuzhiyun static int wm_adc_mux_enum_get(struct snd_kcontrol *kcontrol,
534*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
535*4882a593Smuzhiyun {
536*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
539*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = wm_get(ice, WM_ADC_MUX) & 0x1f;
540*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
541*4882a593Smuzhiyun return 0;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun
wm_adc_mux_enum_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)544*4882a593Smuzhiyun static int wm_adc_mux_enum_put(struct snd_kcontrol *kcontrol,
545*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
546*4882a593Smuzhiyun {
547*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
548*4882a593Smuzhiyun unsigned short oval, nval;
549*4882a593Smuzhiyun int change = 0;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
552*4882a593Smuzhiyun oval = wm_get(ice, WM_ADC_MUX);
553*4882a593Smuzhiyun nval = (oval & 0xe0) | ucontrol->value.enumerated.item[0];
554*4882a593Smuzhiyun if (nval != oval) {
555*4882a593Smuzhiyun wm_put(ice, WM_ADC_MUX, nval);
556*4882a593Smuzhiyun change = 1;
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
559*4882a593Smuzhiyun return change;
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun /* KONSTI */
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun /*
565*4882a593Smuzhiyun * ADC gain mixer control (-64dB to 0dB)
566*4882a593Smuzhiyun */
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun #define ADC_0dB 0xcf
569*4882a593Smuzhiyun #define ADC_RES 128
570*4882a593Smuzhiyun #define ADC_MIN (ADC_0dB - ADC_RES)
571*4882a593Smuzhiyun
wm_adc_vol_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)572*4882a593Smuzhiyun static int wm_adc_vol_info(struct snd_kcontrol *kcontrol,
573*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
576*4882a593Smuzhiyun uinfo->count = 2;
577*4882a593Smuzhiyun uinfo->value.integer.min = 0; /* mute (-64dB) */
578*4882a593Smuzhiyun uinfo->value.integer.max = ADC_RES; /* 0dB, 0.5dB step */
579*4882a593Smuzhiyun return 0;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
wm_adc_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)582*4882a593Smuzhiyun static int wm_adc_vol_get(struct snd_kcontrol *kcontrol,
583*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
584*4882a593Smuzhiyun {
585*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
586*4882a593Smuzhiyun unsigned short val;
587*4882a593Smuzhiyun int i;
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
590*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
591*4882a593Smuzhiyun val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
592*4882a593Smuzhiyun val = val > ADC_MIN ? (val - ADC_MIN) : 0;
593*4882a593Smuzhiyun ucontrol->value.integer.value[i] = val;
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
596*4882a593Smuzhiyun return 0;
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun
wm_adc_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)599*4882a593Smuzhiyun static int wm_adc_vol_put(struct snd_kcontrol *kcontrol,
600*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
601*4882a593Smuzhiyun {
602*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
603*4882a593Smuzhiyun unsigned short ovol, nvol;
604*4882a593Smuzhiyun int i, idx, change = 0;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
607*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
608*4882a593Smuzhiyun nvol = ucontrol->value.integer.value[i];
609*4882a593Smuzhiyun nvol = nvol ? (nvol + ADC_MIN) : 0;
610*4882a593Smuzhiyun idx = WM_ADC_ATTEN_L + i;
611*4882a593Smuzhiyun ovol = wm_get(ice, idx) & 0xff;
612*4882a593Smuzhiyun if (ovol != nvol) {
613*4882a593Smuzhiyun wm_put(ice, idx, nvol);
614*4882a593Smuzhiyun change = 1;
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
618*4882a593Smuzhiyun return change;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun /*
622*4882a593Smuzhiyun * ADC input mux mixer control
623*4882a593Smuzhiyun */
624*4882a593Smuzhiyun #define wm_adc_mux_info snd_ctl_boolean_mono_info
625*4882a593Smuzhiyun
wm_adc_mux_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)626*4882a593Smuzhiyun static int wm_adc_mux_get(struct snd_kcontrol *kcontrol,
627*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
628*4882a593Smuzhiyun {
629*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
630*4882a593Smuzhiyun int bit = kcontrol->private_value;
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
633*4882a593Smuzhiyun ucontrol->value.integer.value[0] =
634*4882a593Smuzhiyun (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
635*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
636*4882a593Smuzhiyun return 0;
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun
wm_adc_mux_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)639*4882a593Smuzhiyun static int wm_adc_mux_put(struct snd_kcontrol *kcontrol,
640*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
641*4882a593Smuzhiyun {
642*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
643*4882a593Smuzhiyun int bit = kcontrol->private_value;
644*4882a593Smuzhiyun unsigned short oval, nval;
645*4882a593Smuzhiyun int change;
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
648*4882a593Smuzhiyun nval = oval = wm_get(ice, WM_ADC_MUX);
649*4882a593Smuzhiyun if (ucontrol->value.integer.value[0])
650*4882a593Smuzhiyun nval |= (1 << bit);
651*4882a593Smuzhiyun else
652*4882a593Smuzhiyun nval &= ~(1 << bit);
653*4882a593Smuzhiyun change = nval != oval;
654*4882a593Smuzhiyun if (change) {
655*4882a593Smuzhiyun wm_put(ice, WM_ADC_MUX, nval);
656*4882a593Smuzhiyun }
657*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
658*4882a593Smuzhiyun return 0;
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun /*
662*4882a593Smuzhiyun * Analog bypass (In -> Out)
663*4882a593Smuzhiyun */
664*4882a593Smuzhiyun #define wm_bypass_info snd_ctl_boolean_mono_info
665*4882a593Smuzhiyun
wm_bypass_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)666*4882a593Smuzhiyun static int wm_bypass_get(struct snd_kcontrol *kcontrol,
667*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
668*4882a593Smuzhiyun {
669*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
672*4882a593Smuzhiyun ucontrol->value.integer.value[0] =
673*4882a593Smuzhiyun (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
674*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
675*4882a593Smuzhiyun return 0;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun
wm_bypass_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)678*4882a593Smuzhiyun static int wm_bypass_put(struct snd_kcontrol *kcontrol,
679*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
682*4882a593Smuzhiyun unsigned short val, oval;
683*4882a593Smuzhiyun int change = 0;
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
686*4882a593Smuzhiyun val = oval = wm_get(ice, WM_OUT_MUX);
687*4882a593Smuzhiyun if (ucontrol->value.integer.value[0])
688*4882a593Smuzhiyun val |= 0x04;
689*4882a593Smuzhiyun else
690*4882a593Smuzhiyun val &= ~0x04;
691*4882a593Smuzhiyun if (val != oval) {
692*4882a593Smuzhiyun wm_put(ice, WM_OUT_MUX, val);
693*4882a593Smuzhiyun change = 1;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
696*4882a593Smuzhiyun return change;
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun /*
700*4882a593Smuzhiyun * Left/Right swap
701*4882a593Smuzhiyun */
702*4882a593Smuzhiyun #define wm_chswap_info snd_ctl_boolean_mono_info
703*4882a593Smuzhiyun
wm_chswap_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)704*4882a593Smuzhiyun static int wm_chswap_get(struct snd_kcontrol *kcontrol,
705*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
706*4882a593Smuzhiyun {
707*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
710*4882a593Smuzhiyun ucontrol->value.integer.value[0] =
711*4882a593Smuzhiyun (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
712*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
713*4882a593Smuzhiyun return 0;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun
wm_chswap_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)716*4882a593Smuzhiyun static int wm_chswap_put(struct snd_kcontrol *kcontrol,
717*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
718*4882a593Smuzhiyun {
719*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
720*4882a593Smuzhiyun unsigned short val, oval;
721*4882a593Smuzhiyun int change = 0;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
724*4882a593Smuzhiyun oval = wm_get(ice, WM_DAC_CTRL1);
725*4882a593Smuzhiyun val = oval & 0x0f;
726*4882a593Smuzhiyun if (ucontrol->value.integer.value[0])
727*4882a593Smuzhiyun val |= 0x60;
728*4882a593Smuzhiyun else
729*4882a593Smuzhiyun val |= 0x90;
730*4882a593Smuzhiyun if (val != oval) {
731*4882a593Smuzhiyun wm_put(ice, WM_DAC_CTRL1, val);
732*4882a593Smuzhiyun wm_put_nocache(ice, WM_DAC_CTRL1, val);
733*4882a593Smuzhiyun change = 1;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
736*4882a593Smuzhiyun return change;
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun /*
741*4882a593Smuzhiyun * mixers
742*4882a593Smuzhiyun */
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun static const struct snd_kcontrol_new prodigy_hifi_controls[] = {
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
747*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
748*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
749*4882a593Smuzhiyun .name = "Master Playback Volume",
750*4882a593Smuzhiyun .info = wm_master_vol_info,
751*4882a593Smuzhiyun .get = wm_master_vol_get,
752*4882a593Smuzhiyun .put = wm_master_vol_put,
753*4882a593Smuzhiyun .tlv = { .p = db_scale_wm_dac }
754*4882a593Smuzhiyun },
755*4882a593Smuzhiyun {
756*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
757*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
758*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
759*4882a593Smuzhiyun .name = "Front Playback Volume",
760*4882a593Smuzhiyun .info = wm_dac_vol_info,
761*4882a593Smuzhiyun .get = wm_dac_vol_get,
762*4882a593Smuzhiyun .put = wm_dac_vol_put,
763*4882a593Smuzhiyun .tlv = { .p = db_scale_wm_dac },
764*4882a593Smuzhiyun },
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
767*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
768*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
769*4882a593Smuzhiyun .name = "Rear Playback Volume",
770*4882a593Smuzhiyun .info = wm8766_vol_info,
771*4882a593Smuzhiyun .get = wm8766_vol_get,
772*4882a593Smuzhiyun .put = wm8766_vol_put,
773*4882a593Smuzhiyun .private_value = (2 << 8) | 0,
774*4882a593Smuzhiyun .tlv = { .p = db_scale_wm_dac },
775*4882a593Smuzhiyun },
776*4882a593Smuzhiyun {
777*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
778*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
779*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
780*4882a593Smuzhiyun .name = "Center Playback Volume",
781*4882a593Smuzhiyun .info = wm8766_vol_info,
782*4882a593Smuzhiyun .get = wm8766_vol_get,
783*4882a593Smuzhiyun .put = wm8766_vol_put,
784*4882a593Smuzhiyun .private_value = (1 << 8) | 4,
785*4882a593Smuzhiyun .tlv = { .p = db_scale_wm_dac }
786*4882a593Smuzhiyun },
787*4882a593Smuzhiyun {
788*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
789*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
790*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
791*4882a593Smuzhiyun .name = "LFE Playback Volume",
792*4882a593Smuzhiyun .info = wm8766_vol_info,
793*4882a593Smuzhiyun .get = wm8766_vol_get,
794*4882a593Smuzhiyun .put = wm8766_vol_put,
795*4882a593Smuzhiyun .private_value = (1 << 8) | 5,
796*4882a593Smuzhiyun .tlv = { .p = db_scale_wm_dac }
797*4882a593Smuzhiyun },
798*4882a593Smuzhiyun {
799*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
800*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
801*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
802*4882a593Smuzhiyun .name = "Side Playback Volume",
803*4882a593Smuzhiyun .info = wm8766_vol_info,
804*4882a593Smuzhiyun .get = wm8766_vol_get,
805*4882a593Smuzhiyun .put = wm8766_vol_put,
806*4882a593Smuzhiyun .private_value = (2 << 8) | 6,
807*4882a593Smuzhiyun .tlv = { .p = db_scale_wm_dac },
808*4882a593Smuzhiyun },
809*4882a593Smuzhiyun {
810*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
811*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
812*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
813*4882a593Smuzhiyun .name = "Capture Volume",
814*4882a593Smuzhiyun .info = wm_adc_vol_info,
815*4882a593Smuzhiyun .get = wm_adc_vol_get,
816*4882a593Smuzhiyun .put = wm_adc_vol_put,
817*4882a593Smuzhiyun .tlv = { .p = db_scale_wm_dac },
818*4882a593Smuzhiyun },
819*4882a593Smuzhiyun {
820*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
821*4882a593Smuzhiyun .name = "CD Capture Switch",
822*4882a593Smuzhiyun .info = wm_adc_mux_info,
823*4882a593Smuzhiyun .get = wm_adc_mux_get,
824*4882a593Smuzhiyun .put = wm_adc_mux_put,
825*4882a593Smuzhiyun .private_value = 0,
826*4882a593Smuzhiyun },
827*4882a593Smuzhiyun {
828*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
829*4882a593Smuzhiyun .name = "Line Capture Switch",
830*4882a593Smuzhiyun .info = wm_adc_mux_info,
831*4882a593Smuzhiyun .get = wm_adc_mux_get,
832*4882a593Smuzhiyun .put = wm_adc_mux_put,
833*4882a593Smuzhiyun .private_value = 1,
834*4882a593Smuzhiyun },
835*4882a593Smuzhiyun {
836*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
837*4882a593Smuzhiyun .name = "Analog Bypass Switch",
838*4882a593Smuzhiyun .info = wm_bypass_info,
839*4882a593Smuzhiyun .get = wm_bypass_get,
840*4882a593Smuzhiyun .put = wm_bypass_put,
841*4882a593Smuzhiyun },
842*4882a593Smuzhiyun {
843*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
844*4882a593Smuzhiyun .name = "Swap Output Channels",
845*4882a593Smuzhiyun .info = wm_chswap_info,
846*4882a593Smuzhiyun .get = wm_chswap_get,
847*4882a593Smuzhiyun .put = wm_chswap_put,
848*4882a593Smuzhiyun },
849*4882a593Smuzhiyun {
850*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
851*4882a593Smuzhiyun .name = "Analog Capture Source",
852*4882a593Smuzhiyun .info = wm_adc_mux_enum_info,
853*4882a593Smuzhiyun .get = wm_adc_mux_enum_get,
854*4882a593Smuzhiyun .put = wm_adc_mux_enum_put,
855*4882a593Smuzhiyun },
856*4882a593Smuzhiyun };
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun /*
859*4882a593Smuzhiyun * WM codec registers
860*4882a593Smuzhiyun */
wm_proc_regs_write(struct snd_info_entry * entry,struct snd_info_buffer * buffer)861*4882a593Smuzhiyun static void wm_proc_regs_write(struct snd_info_entry *entry,
862*4882a593Smuzhiyun struct snd_info_buffer *buffer)
863*4882a593Smuzhiyun {
864*4882a593Smuzhiyun struct snd_ice1712 *ice = entry->private_data;
865*4882a593Smuzhiyun char line[64];
866*4882a593Smuzhiyun unsigned int reg, val;
867*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
868*4882a593Smuzhiyun while (!snd_info_get_line(buffer, line, sizeof(line))) {
869*4882a593Smuzhiyun if (sscanf(line, "%x %x", ®, &val) != 2)
870*4882a593Smuzhiyun continue;
871*4882a593Smuzhiyun if (reg <= 0x17 && val <= 0xffff)
872*4882a593Smuzhiyun wm_put(ice, reg, val);
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
875*4882a593Smuzhiyun }
876*4882a593Smuzhiyun
wm_proc_regs_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)877*4882a593Smuzhiyun static void wm_proc_regs_read(struct snd_info_entry *entry,
878*4882a593Smuzhiyun struct snd_info_buffer *buffer)
879*4882a593Smuzhiyun {
880*4882a593Smuzhiyun struct snd_ice1712 *ice = entry->private_data;
881*4882a593Smuzhiyun int reg, val;
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
884*4882a593Smuzhiyun for (reg = 0; reg <= 0x17; reg++) {
885*4882a593Smuzhiyun val = wm_get(ice, reg);
886*4882a593Smuzhiyun snd_iprintf(buffer, "%02x = %04x\n", reg, val);
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun
wm_proc_init(struct snd_ice1712 * ice)891*4882a593Smuzhiyun static void wm_proc_init(struct snd_ice1712 *ice)
892*4882a593Smuzhiyun {
893*4882a593Smuzhiyun snd_card_rw_proc_new(ice->card, "wm_codec", ice, wm_proc_regs_read,
894*4882a593Smuzhiyun wm_proc_regs_write);
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun
prodigy_hifi_add_controls(struct snd_ice1712 * ice)897*4882a593Smuzhiyun static int prodigy_hifi_add_controls(struct snd_ice1712 *ice)
898*4882a593Smuzhiyun {
899*4882a593Smuzhiyun unsigned int i;
900*4882a593Smuzhiyun int err;
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(prodigy_hifi_controls); i++) {
903*4882a593Smuzhiyun err = snd_ctl_add(ice->card,
904*4882a593Smuzhiyun snd_ctl_new1(&prodigy_hifi_controls[i], ice));
905*4882a593Smuzhiyun if (err < 0)
906*4882a593Smuzhiyun return err;
907*4882a593Smuzhiyun }
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun wm_proc_init(ice);
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun return 0;
912*4882a593Smuzhiyun }
913*4882a593Smuzhiyun
prodigy_hd2_add_controls(struct snd_ice1712 * ice)914*4882a593Smuzhiyun static int prodigy_hd2_add_controls(struct snd_ice1712 *ice)
915*4882a593Smuzhiyun {
916*4882a593Smuzhiyun unsigned int i;
917*4882a593Smuzhiyun int err;
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(prodigy_hd2_controls); i++) {
920*4882a593Smuzhiyun err = snd_ctl_add(ice->card,
921*4882a593Smuzhiyun snd_ctl_new1(&prodigy_hd2_controls[i], ice));
922*4882a593Smuzhiyun if (err < 0)
923*4882a593Smuzhiyun return err;
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun wm_proc_init(ice);
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun return 0;
929*4882a593Smuzhiyun }
930*4882a593Smuzhiyun
wm8766_init(struct snd_ice1712 * ice)931*4882a593Smuzhiyun static void wm8766_init(struct snd_ice1712 *ice)
932*4882a593Smuzhiyun {
933*4882a593Smuzhiyun static const unsigned short wm8766_inits[] = {
934*4882a593Smuzhiyun WM8766_RESET, 0x0000,
935*4882a593Smuzhiyun WM8766_DAC_CTRL, 0x0120,
936*4882a593Smuzhiyun WM8766_INT_CTRL, 0x0022, /* I2S Normal Mode, 24 bit */
937*4882a593Smuzhiyun WM8766_DAC_CTRL2, 0x0001,
938*4882a593Smuzhiyun WM8766_DAC_CTRL3, 0x0080,
939*4882a593Smuzhiyun WM8766_LDA1, 0x0100,
940*4882a593Smuzhiyun WM8766_LDA2, 0x0100,
941*4882a593Smuzhiyun WM8766_LDA3, 0x0100,
942*4882a593Smuzhiyun WM8766_RDA1, 0x0100,
943*4882a593Smuzhiyun WM8766_RDA2, 0x0100,
944*4882a593Smuzhiyun WM8766_RDA3, 0x0100,
945*4882a593Smuzhiyun WM8766_MUTE1, 0x0000,
946*4882a593Smuzhiyun WM8766_MUTE2, 0x0000,
947*4882a593Smuzhiyun };
948*4882a593Smuzhiyun unsigned int i;
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(wm8766_inits); i += 2)
951*4882a593Smuzhiyun wm8766_spi_write(ice, wm8766_inits[i], wm8766_inits[i + 1]);
952*4882a593Smuzhiyun }
953*4882a593Smuzhiyun
wm8776_init(struct snd_ice1712 * ice)954*4882a593Smuzhiyun static void wm8776_init(struct snd_ice1712 *ice)
955*4882a593Smuzhiyun {
956*4882a593Smuzhiyun static const unsigned short wm8776_inits[] = {
957*4882a593Smuzhiyun /* These come first to reduce init pop noise */
958*4882a593Smuzhiyun WM_ADC_MUX, 0x0003, /* ADC mute */
959*4882a593Smuzhiyun /* 0x00c0 replaced by 0x0003 */
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun WM_DAC_MUTE, 0x0001, /* DAC softmute */
962*4882a593Smuzhiyun WM_DAC_CTRL1, 0x0000, /* DAC mute */
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun WM_POWERDOWN, 0x0008, /* All power-up except HP */
965*4882a593Smuzhiyun WM_RESET, 0x0000, /* reset */
966*4882a593Smuzhiyun };
967*4882a593Smuzhiyun unsigned int i;
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(wm8776_inits); i += 2)
970*4882a593Smuzhiyun wm_put(ice, wm8776_inits[i], wm8776_inits[i + 1]);
971*4882a593Smuzhiyun }
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
prodigy_hifi_resume(struct snd_ice1712 * ice)974*4882a593Smuzhiyun static int prodigy_hifi_resume(struct snd_ice1712 *ice)
975*4882a593Smuzhiyun {
976*4882a593Smuzhiyun static const unsigned short wm8776_reinit_registers[] = {
977*4882a593Smuzhiyun WM_MASTER_CTRL,
978*4882a593Smuzhiyun WM_DAC_INT,
979*4882a593Smuzhiyun WM_ADC_INT,
980*4882a593Smuzhiyun WM_OUT_MUX,
981*4882a593Smuzhiyun WM_HP_ATTEN_L,
982*4882a593Smuzhiyun WM_HP_ATTEN_R,
983*4882a593Smuzhiyun WM_PHASE_SWAP,
984*4882a593Smuzhiyun WM_DAC_CTRL2,
985*4882a593Smuzhiyun WM_ADC_ATTEN_L,
986*4882a593Smuzhiyun WM_ADC_ATTEN_R,
987*4882a593Smuzhiyun WM_ALC_CTRL1,
988*4882a593Smuzhiyun WM_ALC_CTRL2,
989*4882a593Smuzhiyun WM_ALC_CTRL3,
990*4882a593Smuzhiyun WM_NOISE_GATE,
991*4882a593Smuzhiyun WM_ADC_MUX,
992*4882a593Smuzhiyun /* no DAC attenuation here */
993*4882a593Smuzhiyun };
994*4882a593Smuzhiyun struct prodigy_hifi_spec *spec = ice->spec;
995*4882a593Smuzhiyun int i, ch;
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun /* reinitialize WM8776 and re-apply old register values */
1000*4882a593Smuzhiyun wm8776_init(ice);
1001*4882a593Smuzhiyun schedule_timeout_uninterruptible(1);
1002*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(wm8776_reinit_registers); i++)
1003*4882a593Smuzhiyun wm_put(ice, wm8776_reinit_registers[i],
1004*4882a593Smuzhiyun wm_get(ice, wm8776_reinit_registers[i]));
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun /* reinitialize WM8766 and re-apply volumes for all DACs */
1007*4882a593Smuzhiyun wm8766_init(ice);
1008*4882a593Smuzhiyun for (ch = 0; ch < 2; ch++) {
1009*4882a593Smuzhiyun wm_set_vol(ice, WM_DAC_ATTEN_L + ch,
1010*4882a593Smuzhiyun spec->vol[2 + ch], spec->master[ch]);
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun wm8766_set_vol(ice, WM8766_LDA1 + ch,
1013*4882a593Smuzhiyun spec->vol[0 + ch], spec->master[ch]);
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun wm8766_set_vol(ice, WM8766_LDA2 + ch,
1016*4882a593Smuzhiyun spec->vol[4 + ch], spec->master[ch]);
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun wm8766_set_vol(ice, WM8766_LDA3 + ch,
1019*4882a593Smuzhiyun spec->vol[6 + ch], spec->master[ch]);
1020*4882a593Smuzhiyun }
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun /* unmute WM8776 DAC */
1023*4882a593Smuzhiyun wm_put(ice, WM_DAC_MUTE, 0x00);
1024*4882a593Smuzhiyun wm_put(ice, WM_DAC_CTRL1, 0x90);
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
1027*4882a593Smuzhiyun return 0;
1028*4882a593Smuzhiyun }
1029*4882a593Smuzhiyun #endif
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun /*
1032*4882a593Smuzhiyun * initialize the chip
1033*4882a593Smuzhiyun */
prodigy_hifi_init(struct snd_ice1712 * ice)1034*4882a593Smuzhiyun static int prodigy_hifi_init(struct snd_ice1712 *ice)
1035*4882a593Smuzhiyun {
1036*4882a593Smuzhiyun static const unsigned short wm8776_defaults[] = {
1037*4882a593Smuzhiyun WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
1038*4882a593Smuzhiyun WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
1039*4882a593Smuzhiyun WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
1040*4882a593Smuzhiyun WM_DAC_CTRL1, 0x0090, /* DAC L/R */
1041*4882a593Smuzhiyun WM_OUT_MUX, 0x0001, /* OUT DAC */
1042*4882a593Smuzhiyun WM_HP_ATTEN_L, 0x0179, /* HP 0dB */
1043*4882a593Smuzhiyun WM_HP_ATTEN_R, 0x0179, /* HP 0dB */
1044*4882a593Smuzhiyun WM_DAC_ATTEN_L, 0x0000, /* DAC 0dB */
1045*4882a593Smuzhiyun WM_DAC_ATTEN_L, 0x0100, /* DAC 0dB */
1046*4882a593Smuzhiyun WM_DAC_ATTEN_R, 0x0000, /* DAC 0dB */
1047*4882a593Smuzhiyun WM_DAC_ATTEN_R, 0x0100, /* DAC 0dB */
1048*4882a593Smuzhiyun WM_PHASE_SWAP, 0x0000, /* phase normal */
1049*4882a593Smuzhiyun #if 0
1050*4882a593Smuzhiyun WM_DAC_MASTER, 0x0100, /* DAC master muted */
1051*4882a593Smuzhiyun #endif
1052*4882a593Smuzhiyun WM_DAC_CTRL2, 0x0000, /* no deemphasis, no ZFLG */
1053*4882a593Smuzhiyun WM_ADC_ATTEN_L, 0x0000, /* ADC muted */
1054*4882a593Smuzhiyun WM_ADC_ATTEN_R, 0x0000, /* ADC muted */
1055*4882a593Smuzhiyun #if 1
1056*4882a593Smuzhiyun WM_ALC_CTRL1, 0x007b, /* */
1057*4882a593Smuzhiyun WM_ALC_CTRL2, 0x0000, /* */
1058*4882a593Smuzhiyun WM_ALC_CTRL3, 0x0000, /* */
1059*4882a593Smuzhiyun WM_NOISE_GATE, 0x0000, /* */
1060*4882a593Smuzhiyun #endif
1061*4882a593Smuzhiyun WM_DAC_MUTE, 0x0000, /* DAC unmute */
1062*4882a593Smuzhiyun WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
1063*4882a593Smuzhiyun };
1064*4882a593Smuzhiyun struct prodigy_hifi_spec *spec;
1065*4882a593Smuzhiyun unsigned int i;
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun ice->vt1720 = 0;
1068*4882a593Smuzhiyun ice->vt1724 = 1;
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun ice->num_total_dacs = 8;
1071*4882a593Smuzhiyun ice->num_total_adcs = 1;
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun /* HACK - use this as the SPDIF source.
1074*4882a593Smuzhiyun * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
1075*4882a593Smuzhiyun */
1076*4882a593Smuzhiyun ice->gpio.saved[0] = 0;
1077*4882a593Smuzhiyun /* to remember the register values */
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
1080*4882a593Smuzhiyun if (! ice->akm)
1081*4882a593Smuzhiyun return -ENOMEM;
1082*4882a593Smuzhiyun ice->akm_codecs = 1;
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1085*4882a593Smuzhiyun if (!spec)
1086*4882a593Smuzhiyun return -ENOMEM;
1087*4882a593Smuzhiyun ice->spec = spec;
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun /* initialize WM8776 codec */
1090*4882a593Smuzhiyun wm8776_init(ice);
1091*4882a593Smuzhiyun schedule_timeout_uninterruptible(1);
1092*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(wm8776_defaults); i += 2)
1093*4882a593Smuzhiyun wm_put(ice, wm8776_defaults[i], wm8776_defaults[i + 1]);
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun wm8766_init(ice);
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
1098*4882a593Smuzhiyun ice->pm_resume = &prodigy_hifi_resume;
1099*4882a593Smuzhiyun ice->pm_suspend_enabled = 1;
1100*4882a593Smuzhiyun #endif
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun return 0;
1103*4882a593Smuzhiyun }
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun /*
1107*4882a593Smuzhiyun * initialize the chip
1108*4882a593Smuzhiyun */
ak4396_init(struct snd_ice1712 * ice)1109*4882a593Smuzhiyun static void ak4396_init(struct snd_ice1712 *ice)
1110*4882a593Smuzhiyun {
1111*4882a593Smuzhiyun static const unsigned short ak4396_inits[] = {
1112*4882a593Smuzhiyun AK4396_CTRL1, 0x87, /* I2S Normal Mode, 24 bit */
1113*4882a593Smuzhiyun AK4396_CTRL2, 0x02,
1114*4882a593Smuzhiyun AK4396_CTRL3, 0x00,
1115*4882a593Smuzhiyun AK4396_LCH_ATT, 0x00,
1116*4882a593Smuzhiyun AK4396_RCH_ATT, 0x00,
1117*4882a593Smuzhiyun };
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun unsigned int i;
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun /* initialize ak4396 codec */
1122*4882a593Smuzhiyun /* reset codec */
1123*4882a593Smuzhiyun ak4396_write(ice, AK4396_CTRL1, 0x86);
1124*4882a593Smuzhiyun msleep(100);
1125*4882a593Smuzhiyun ak4396_write(ice, AK4396_CTRL1, 0x87);
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(ak4396_inits); i += 2)
1128*4882a593Smuzhiyun ak4396_write(ice, ak4396_inits[i], ak4396_inits[i+1]);
1129*4882a593Smuzhiyun }
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
prodigy_hd2_resume(struct snd_ice1712 * ice)1132*4882a593Smuzhiyun static int prodigy_hd2_resume(struct snd_ice1712 *ice)
1133*4882a593Smuzhiyun {
1134*4882a593Smuzhiyun /* initialize ak4396 codec and restore previous mixer volumes */
1135*4882a593Smuzhiyun struct prodigy_hifi_spec *spec = ice->spec;
1136*4882a593Smuzhiyun int i;
1137*4882a593Smuzhiyun mutex_lock(&ice->gpio_mutex);
1138*4882a593Smuzhiyun ak4396_init(ice);
1139*4882a593Smuzhiyun for (i = 0; i < 2; i++)
1140*4882a593Smuzhiyun ak4396_write(ice, AK4396_LCH_ATT + i, spec->vol[i] & 0xff);
1141*4882a593Smuzhiyun mutex_unlock(&ice->gpio_mutex);
1142*4882a593Smuzhiyun return 0;
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun #endif
1145*4882a593Smuzhiyun
prodigy_hd2_init(struct snd_ice1712 * ice)1146*4882a593Smuzhiyun static int prodigy_hd2_init(struct snd_ice1712 *ice)
1147*4882a593Smuzhiyun {
1148*4882a593Smuzhiyun struct prodigy_hifi_spec *spec;
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun ice->vt1720 = 0;
1151*4882a593Smuzhiyun ice->vt1724 = 1;
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun ice->num_total_dacs = 1;
1154*4882a593Smuzhiyun ice->num_total_adcs = 1;
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun /* HACK - use this as the SPDIF source.
1157*4882a593Smuzhiyun * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
1158*4882a593Smuzhiyun */
1159*4882a593Smuzhiyun ice->gpio.saved[0] = 0;
1160*4882a593Smuzhiyun /* to remember the register values */
1161*4882a593Smuzhiyun
1162*4882a593Smuzhiyun ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
1163*4882a593Smuzhiyun if (! ice->akm)
1164*4882a593Smuzhiyun return -ENOMEM;
1165*4882a593Smuzhiyun ice->akm_codecs = 1;
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1168*4882a593Smuzhiyun if (!spec)
1169*4882a593Smuzhiyun return -ENOMEM;
1170*4882a593Smuzhiyun ice->spec = spec;
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
1173*4882a593Smuzhiyun ice->pm_resume = &prodigy_hd2_resume;
1174*4882a593Smuzhiyun ice->pm_suspend_enabled = 1;
1175*4882a593Smuzhiyun #endif
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun ak4396_init(ice);
1178*4882a593Smuzhiyun
1179*4882a593Smuzhiyun return 0;
1180*4882a593Smuzhiyun }
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun static const unsigned char prodigy71hifi_eeprom[] = {
1184*4882a593Smuzhiyun 0x4b, /* SYSCONF: clock 512, spdif-in/ADC, 4DACs */
1185*4882a593Smuzhiyun 0x80, /* ACLINK: I2S */
1186*4882a593Smuzhiyun 0xfc, /* I2S: vol, 96k, 24bit, 192k */
1187*4882a593Smuzhiyun 0xc3, /* SPDIF: out-en, out-int, spdif-in */
1188*4882a593Smuzhiyun 0xff, /* GPIO_DIR */
1189*4882a593Smuzhiyun 0xff, /* GPIO_DIR1 */
1190*4882a593Smuzhiyun 0x5f, /* GPIO_DIR2 */
1191*4882a593Smuzhiyun 0x00, /* GPIO_MASK */
1192*4882a593Smuzhiyun 0x00, /* GPIO_MASK1 */
1193*4882a593Smuzhiyun 0x00, /* GPIO_MASK2 */
1194*4882a593Smuzhiyun 0x00, /* GPIO_STATE */
1195*4882a593Smuzhiyun 0x00, /* GPIO_STATE1 */
1196*4882a593Smuzhiyun 0x00, /* GPIO_STATE2 */
1197*4882a593Smuzhiyun };
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun static const unsigned char prodigyhd2_eeprom[] = {
1200*4882a593Smuzhiyun 0x4b, /* SYSCONF: clock 512, spdif-in/ADC, 4DACs */
1201*4882a593Smuzhiyun 0x80, /* ACLINK: I2S */
1202*4882a593Smuzhiyun 0xfc, /* I2S: vol, 96k, 24bit, 192k */
1203*4882a593Smuzhiyun 0xc3, /* SPDIF: out-en, out-int, spdif-in */
1204*4882a593Smuzhiyun 0xff, /* GPIO_DIR */
1205*4882a593Smuzhiyun 0xff, /* GPIO_DIR1 */
1206*4882a593Smuzhiyun 0x5f, /* GPIO_DIR2 */
1207*4882a593Smuzhiyun 0x00, /* GPIO_MASK */
1208*4882a593Smuzhiyun 0x00, /* GPIO_MASK1 */
1209*4882a593Smuzhiyun 0x00, /* GPIO_MASK2 */
1210*4882a593Smuzhiyun 0x00, /* GPIO_STATE */
1211*4882a593Smuzhiyun 0x00, /* GPIO_STATE1 */
1212*4882a593Smuzhiyun 0x00, /* GPIO_STATE2 */
1213*4882a593Smuzhiyun };
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun static const unsigned char fortissimo4_eeprom[] = {
1216*4882a593Smuzhiyun 0x43, /* SYSCONF: clock 512, ADC, 4DACs */
1217*4882a593Smuzhiyun 0x80, /* ACLINK: I2S */
1218*4882a593Smuzhiyun 0xfc, /* I2S: vol, 96k, 24bit, 192k */
1219*4882a593Smuzhiyun 0xc1, /* SPDIF: out-en, out-int */
1220*4882a593Smuzhiyun 0xff, /* GPIO_DIR */
1221*4882a593Smuzhiyun 0xff, /* GPIO_DIR1 */
1222*4882a593Smuzhiyun 0x5f, /* GPIO_DIR2 */
1223*4882a593Smuzhiyun 0x00, /* GPIO_MASK */
1224*4882a593Smuzhiyun 0x00, /* GPIO_MASK1 */
1225*4882a593Smuzhiyun 0x00, /* GPIO_MASK2 */
1226*4882a593Smuzhiyun 0x00, /* GPIO_STATE */
1227*4882a593Smuzhiyun 0x00, /* GPIO_STATE1 */
1228*4882a593Smuzhiyun 0x00, /* GPIO_STATE2 */
1229*4882a593Smuzhiyun };
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun /* entry point */
1232*4882a593Smuzhiyun struct snd_ice1712_card_info snd_vt1724_prodigy_hifi_cards[] = {
1233*4882a593Smuzhiyun {
1234*4882a593Smuzhiyun .subvendor = VT1724_SUBDEVICE_PRODIGY_HIFI,
1235*4882a593Smuzhiyun .name = "Audiotrak Prodigy 7.1 HiFi",
1236*4882a593Smuzhiyun .model = "prodigy71hifi",
1237*4882a593Smuzhiyun .chip_init = prodigy_hifi_init,
1238*4882a593Smuzhiyun .build_controls = prodigy_hifi_add_controls,
1239*4882a593Smuzhiyun .eeprom_size = sizeof(prodigy71hifi_eeprom),
1240*4882a593Smuzhiyun .eeprom_data = prodigy71hifi_eeprom,
1241*4882a593Smuzhiyun .driver = "Prodigy71HIFI",
1242*4882a593Smuzhiyun },
1243*4882a593Smuzhiyun {
1244*4882a593Smuzhiyun .subvendor = VT1724_SUBDEVICE_PRODIGY_HD2,
1245*4882a593Smuzhiyun .name = "Audiotrak Prodigy HD2",
1246*4882a593Smuzhiyun .model = "prodigyhd2",
1247*4882a593Smuzhiyun .chip_init = prodigy_hd2_init,
1248*4882a593Smuzhiyun .build_controls = prodigy_hd2_add_controls,
1249*4882a593Smuzhiyun .eeprom_size = sizeof(prodigyhd2_eeprom),
1250*4882a593Smuzhiyun .eeprom_data = prodigyhd2_eeprom,
1251*4882a593Smuzhiyun .driver = "Prodigy71HD2",
1252*4882a593Smuzhiyun },
1253*4882a593Smuzhiyun {
1254*4882a593Smuzhiyun .subvendor = VT1724_SUBDEVICE_FORTISSIMO4,
1255*4882a593Smuzhiyun .name = "Hercules Fortissimo IV",
1256*4882a593Smuzhiyun .model = "fortissimo4",
1257*4882a593Smuzhiyun .chip_init = prodigy_hifi_init,
1258*4882a593Smuzhiyun .build_controls = prodigy_hifi_add_controls,
1259*4882a593Smuzhiyun .eeprom_size = sizeof(fortissimo4_eeprom),
1260*4882a593Smuzhiyun .eeprom_data = fortissimo4_eeprom,
1261*4882a593Smuzhiyun .driver = "Fortissimo4",
1262*4882a593Smuzhiyun },
1263*4882a593Smuzhiyun { } /* terminator */
1264*4882a593Smuzhiyun };
1265*4882a593Smuzhiyun
1266