1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun #ifndef __SOUND_PHASE_H 3*4882a593Smuzhiyun #define __SOUND_PHASE_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * ALSA driver for ICEnsemble ICE1712 (Envy24) 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Lowlevel functions for Terratec PHASE 22 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com> 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define PHASE_DEVICE_DESC "{Terratec,Phase 22},"\ 14*4882a593Smuzhiyun "{Terratec,Phase 28},"\ 15*4882a593Smuzhiyun "{Terrasoniq,TS22}," 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define VT1724_SUBDEVICE_PHASE22 0x3b155011 18*4882a593Smuzhiyun #define VT1724_SUBDEVICE_PHASE28 0x3b154911 19*4882a593Smuzhiyun #define VT1724_SUBDEVICE_TS22 0x3b157b11 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* entry point */ 22*4882a593Smuzhiyun extern struct snd_ice1712_card_info snd_vt1724_phase_cards[]; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* PHASE28 GPIO bits */ 25*4882a593Smuzhiyun #define PHASE28_SPI_MISO (1 << 21) 26*4882a593Smuzhiyun #define PHASE28_WM_RESET (1 << 20) 27*4882a593Smuzhiyun #define PHASE28_SPI_CLK (1 << 19) 28*4882a593Smuzhiyun #define PHASE28_SPI_MOSI (1 << 18) 29*4882a593Smuzhiyun #define PHASE28_WM_RW (1 << 17) 30*4882a593Smuzhiyun #define PHASE28_AC97_RESET (1 << 16) 31*4882a593Smuzhiyun #define PHASE28_DIGITAL_SEL1 (1 << 15) 32*4882a593Smuzhiyun #define PHASE28_HP_SEL (1 << 14) 33*4882a593Smuzhiyun #define PHASE28_WM_CS (1 << 12) 34*4882a593Smuzhiyun #define PHASE28_AC97_COMMIT (1 << 11) 35*4882a593Smuzhiyun #define PHASE28_AC97_ADDR (1 << 10) 36*4882a593Smuzhiyun #define PHASE28_AC97_DATA_LOW (1 << 9) 37*4882a593Smuzhiyun #define PHASE28_AC97_DATA_HIGH (1 << 8) 38*4882a593Smuzhiyun #define PHASE28_AC97_DATA_MASK 0xFF 39*4882a593Smuzhiyun #endif /* __SOUND_PHASE */ 40