1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
4*4882a593Smuzhiyun * VIA VT1720 (Envy24PT)
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
7*4882a593Smuzhiyun * 2002 James Stafford <jstafford@ampltd.com>
8*4882a593Smuzhiyun * 2003 Takashi Iwai <tiwai@suse.de>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/mutex.h>
18*4882a593Smuzhiyun #include <sound/core.h>
19*4882a593Smuzhiyun #include <sound/info.h>
20*4882a593Smuzhiyun #include <sound/rawmidi.h>
21*4882a593Smuzhiyun #include <sound/initval.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <sound/asoundef.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include "ice1712.h"
26*4882a593Smuzhiyun #include "envy24ht.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* lowlevel routines */
29*4882a593Smuzhiyun #include "amp.h"
30*4882a593Smuzhiyun #include "revo.h"
31*4882a593Smuzhiyun #include "aureon.h"
32*4882a593Smuzhiyun #include "vt1720_mobo.h"
33*4882a593Smuzhiyun #include "pontis.h"
34*4882a593Smuzhiyun #include "prodigy192.h"
35*4882a593Smuzhiyun #include "prodigy_hifi.h"
36*4882a593Smuzhiyun #include "juli.h"
37*4882a593Smuzhiyun #include "maya44.h"
38*4882a593Smuzhiyun #include "phase.h"
39*4882a593Smuzhiyun #include "wtm.h"
40*4882a593Smuzhiyun #include "se.h"
41*4882a593Smuzhiyun #include "quartet.h"
42*4882a593Smuzhiyun #include "psc724.h"
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
45*4882a593Smuzhiyun MODULE_DESCRIPTION("VIA ICEnsemble ICE1724/1720 (Envy24HT/PT)");
46*4882a593Smuzhiyun MODULE_LICENSE("GPL");
47*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{"
48*4882a593Smuzhiyun REVO_DEVICE_DESC
49*4882a593Smuzhiyun AMP_AUDIO2000_DEVICE_DESC
50*4882a593Smuzhiyun AUREON_DEVICE_DESC
51*4882a593Smuzhiyun VT1720_MOBO_DEVICE_DESC
52*4882a593Smuzhiyun PONTIS_DEVICE_DESC
53*4882a593Smuzhiyun PRODIGY192_DEVICE_DESC
54*4882a593Smuzhiyun PRODIGY_HIFI_DEVICE_DESC
55*4882a593Smuzhiyun JULI_DEVICE_DESC
56*4882a593Smuzhiyun MAYA44_DEVICE_DESC
57*4882a593Smuzhiyun PHASE_DEVICE_DESC
58*4882a593Smuzhiyun WTM_DEVICE_DESC
59*4882a593Smuzhiyun SE_DEVICE_DESC
60*4882a593Smuzhiyun QTET_DEVICE_DESC
61*4882a593Smuzhiyun "{VIA,VT1720},"
62*4882a593Smuzhiyun "{VIA,VT1724},"
63*4882a593Smuzhiyun "{ICEnsemble,Generic ICE1724},"
64*4882a593Smuzhiyun "{ICEnsemble,Generic Envy24HT}"
65*4882a593Smuzhiyun "{ICEnsemble,Generic Envy24PT}}");
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
68*4882a593Smuzhiyun static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
69*4882a593Smuzhiyun static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
70*4882a593Smuzhiyun static char *model[SNDRV_CARDS];
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun module_param_array(index, int, NULL, 0444);
73*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for ICE1724 soundcard.");
74*4882a593Smuzhiyun module_param_array(id, charp, NULL, 0444);
75*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for ICE1724 soundcard.");
76*4882a593Smuzhiyun module_param_array(enable, bool, NULL, 0444);
77*4882a593Smuzhiyun MODULE_PARM_DESC(enable, "Enable ICE1724 soundcard.");
78*4882a593Smuzhiyun module_param_array(model, charp, NULL, 0444);
79*4882a593Smuzhiyun MODULE_PARM_DESC(model, "Use the given board model.");
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Both VT1720 and VT1724 have the same PCI IDs */
83*4882a593Smuzhiyun static const struct pci_device_id snd_vt1724_ids[] = {
84*4882a593Smuzhiyun { PCI_VDEVICE(ICE, PCI_DEVICE_ID_VT1724), 0 },
85*4882a593Smuzhiyun { 0, }
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, snd_vt1724_ids);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static int PRO_RATE_LOCKED;
92*4882a593Smuzhiyun static int PRO_RATE_RESET = 1;
93*4882a593Smuzhiyun static unsigned int PRO_RATE_DEFAULT = 44100;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun static const char * const ext_clock_names[1] = { "IEC958 In" };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun * Basic I/O
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun * default rates, default clock routines
103*4882a593Smuzhiyun */
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* check whether the clock mode is spdif-in */
stdclock_is_spdif_master(struct snd_ice1712 * ice)106*4882a593Smuzhiyun static inline int stdclock_is_spdif_master(struct snd_ice1712 *ice)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun * locking rate makes sense only for internal clock mode
113*4882a593Smuzhiyun */
is_pro_rate_locked(struct snd_ice1712 * ice)114*4882a593Smuzhiyun static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun return (!ice->is_spdif_master(ice)) && PRO_RATE_LOCKED;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /*
120*4882a593Smuzhiyun * ac97 section
121*4882a593Smuzhiyun */
122*4882a593Smuzhiyun
snd_vt1724_ac97_ready(struct snd_ice1712 * ice)123*4882a593Smuzhiyun static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun unsigned char old_cmd;
126*4882a593Smuzhiyun int tm;
127*4882a593Smuzhiyun for (tm = 0; tm < 0x10000; tm++) {
128*4882a593Smuzhiyun old_cmd = inb(ICEMT1724(ice, AC97_CMD));
129*4882a593Smuzhiyun if (old_cmd & (VT1724_AC97_WRITE | VT1724_AC97_READ))
130*4882a593Smuzhiyun continue;
131*4882a593Smuzhiyun if (!(old_cmd & VT1724_AC97_READY))
132*4882a593Smuzhiyun continue;
133*4882a593Smuzhiyun return old_cmd;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun dev_dbg(ice->card->dev, "snd_vt1724_ac97_ready: timeout\n");
136*4882a593Smuzhiyun return old_cmd;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
snd_vt1724_ac97_wait_bit(struct snd_ice1712 * ice,unsigned char bit)139*4882a593Smuzhiyun static int snd_vt1724_ac97_wait_bit(struct snd_ice1712 *ice, unsigned char bit)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun int tm;
142*4882a593Smuzhiyun for (tm = 0; tm < 0x10000; tm++)
143*4882a593Smuzhiyun if ((inb(ICEMT1724(ice, AC97_CMD)) & bit) == 0)
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun dev_dbg(ice->card->dev, "snd_vt1724_ac97_wait_bit: timeout\n");
146*4882a593Smuzhiyun return -EIO;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
snd_vt1724_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)149*4882a593Smuzhiyun static void snd_vt1724_ac97_write(struct snd_ac97 *ac97,
150*4882a593Smuzhiyun unsigned short reg,
151*4882a593Smuzhiyun unsigned short val)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun struct snd_ice1712 *ice = ac97->private_data;
154*4882a593Smuzhiyun unsigned char old_cmd;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun old_cmd = snd_vt1724_ac97_ready(ice);
157*4882a593Smuzhiyun old_cmd &= ~VT1724_AC97_ID_MASK;
158*4882a593Smuzhiyun old_cmd |= ac97->num;
159*4882a593Smuzhiyun outb(reg, ICEMT1724(ice, AC97_INDEX));
160*4882a593Smuzhiyun outw(val, ICEMT1724(ice, AC97_DATA));
161*4882a593Smuzhiyun outb(old_cmd | VT1724_AC97_WRITE, ICEMT1724(ice, AC97_CMD));
162*4882a593Smuzhiyun snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_WRITE);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
snd_vt1724_ac97_read(struct snd_ac97 * ac97,unsigned short reg)165*4882a593Smuzhiyun static unsigned short snd_vt1724_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun struct snd_ice1712 *ice = ac97->private_data;
168*4882a593Smuzhiyun unsigned char old_cmd;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun old_cmd = snd_vt1724_ac97_ready(ice);
171*4882a593Smuzhiyun old_cmd &= ~VT1724_AC97_ID_MASK;
172*4882a593Smuzhiyun old_cmd |= ac97->num;
173*4882a593Smuzhiyun outb(reg, ICEMT1724(ice, AC97_INDEX));
174*4882a593Smuzhiyun outb(old_cmd | VT1724_AC97_READ, ICEMT1724(ice, AC97_CMD));
175*4882a593Smuzhiyun if (snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_READ) < 0)
176*4882a593Smuzhiyun return ~0;
177*4882a593Smuzhiyun return inw(ICEMT1724(ice, AC97_DATA));
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /*
182*4882a593Smuzhiyun * GPIO operations
183*4882a593Smuzhiyun */
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* set gpio direction 0 = read, 1 = write */
snd_vt1724_set_gpio_dir(struct snd_ice1712 * ice,unsigned int data)186*4882a593Smuzhiyun static void snd_vt1724_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun outl(data, ICEREG1724(ice, GPIO_DIRECTION));
189*4882a593Smuzhiyun inw(ICEREG1724(ice, GPIO_DIRECTION)); /* dummy read for pci-posting */
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /* get gpio direction 0 = read, 1 = write */
snd_vt1724_get_gpio_dir(struct snd_ice1712 * ice)193*4882a593Smuzhiyun static unsigned int snd_vt1724_get_gpio_dir(struct snd_ice1712 *ice)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun return inl(ICEREG1724(ice, GPIO_DIRECTION));
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* set the gpio mask (0 = writable) */
snd_vt1724_set_gpio_mask(struct snd_ice1712 * ice,unsigned int data)199*4882a593Smuzhiyun static void snd_vt1724_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun outw(data, ICEREG1724(ice, GPIO_WRITE_MASK));
202*4882a593Smuzhiyun if (!ice->vt1720) /* VT1720 supports only 16 GPIO bits */
203*4882a593Smuzhiyun outb((data >> 16) & 0xff, ICEREG1724(ice, GPIO_WRITE_MASK_22));
204*4882a593Smuzhiyun inw(ICEREG1724(ice, GPIO_WRITE_MASK)); /* dummy read for pci-posting */
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
snd_vt1724_get_gpio_mask(struct snd_ice1712 * ice)207*4882a593Smuzhiyun static unsigned int snd_vt1724_get_gpio_mask(struct snd_ice1712 *ice)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun unsigned int mask;
210*4882a593Smuzhiyun if (!ice->vt1720)
211*4882a593Smuzhiyun mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22));
212*4882a593Smuzhiyun else
213*4882a593Smuzhiyun mask = 0;
214*4882a593Smuzhiyun mask = (mask << 16) | inw(ICEREG1724(ice, GPIO_WRITE_MASK));
215*4882a593Smuzhiyun return mask;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
snd_vt1724_set_gpio_data(struct snd_ice1712 * ice,unsigned int data)218*4882a593Smuzhiyun static void snd_vt1724_set_gpio_data(struct snd_ice1712 *ice, unsigned int data)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun outw(data, ICEREG1724(ice, GPIO_DATA));
221*4882a593Smuzhiyun if (!ice->vt1720)
222*4882a593Smuzhiyun outb(data >> 16, ICEREG1724(ice, GPIO_DATA_22));
223*4882a593Smuzhiyun inw(ICEREG1724(ice, GPIO_DATA)); /* dummy read for pci-posting */
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
snd_vt1724_get_gpio_data(struct snd_ice1712 * ice)226*4882a593Smuzhiyun static unsigned int snd_vt1724_get_gpio_data(struct snd_ice1712 *ice)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun unsigned int data;
229*4882a593Smuzhiyun if (!ice->vt1720)
230*4882a593Smuzhiyun data = (unsigned int)inb(ICEREG1724(ice, GPIO_DATA_22));
231*4882a593Smuzhiyun else
232*4882a593Smuzhiyun data = 0;
233*4882a593Smuzhiyun data = (data << 16) | inw(ICEREG1724(ice, GPIO_DATA));
234*4882a593Smuzhiyun return data;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /*
238*4882a593Smuzhiyun * MIDI
239*4882a593Smuzhiyun */
240*4882a593Smuzhiyun
vt1724_midi_clear_rx(struct snd_ice1712 * ice)241*4882a593Smuzhiyun static void vt1724_midi_clear_rx(struct snd_ice1712 *ice)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun unsigned int count;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun for (count = inb(ICEREG1724(ice, MPU_RXFIFO)); count > 0; --count)
246*4882a593Smuzhiyun inb(ICEREG1724(ice, MPU_DATA));
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun static inline struct snd_rawmidi_substream *
get_rawmidi_substream(struct snd_ice1712 * ice,unsigned int stream)250*4882a593Smuzhiyun get_rawmidi_substream(struct snd_ice1712 *ice, unsigned int stream)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun return list_first_entry(&ice->rmidi[0]->streams[stream].substreams,
253*4882a593Smuzhiyun struct snd_rawmidi_substream, list);
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable);
257*4882a593Smuzhiyun
vt1724_midi_write(struct snd_ice1712 * ice)258*4882a593Smuzhiyun static void vt1724_midi_write(struct snd_ice1712 *ice)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun struct snd_rawmidi_substream *s;
261*4882a593Smuzhiyun int count, i;
262*4882a593Smuzhiyun u8 buffer[32];
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_OUTPUT);
265*4882a593Smuzhiyun count = 31 - inb(ICEREG1724(ice, MPU_TXFIFO));
266*4882a593Smuzhiyun if (count > 0) {
267*4882a593Smuzhiyun count = snd_rawmidi_transmit(s, buffer, count);
268*4882a593Smuzhiyun for (i = 0; i < count; ++i)
269*4882a593Smuzhiyun outb(buffer[i], ICEREG1724(ice, MPU_DATA));
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun /* mask irq when all bytes have been transmitted.
272*4882a593Smuzhiyun * enabled again in output_trigger when the new data comes in.
273*4882a593Smuzhiyun */
274*4882a593Smuzhiyun enable_midi_irq(ice, VT1724_IRQ_MPU_TX,
275*4882a593Smuzhiyun !snd_rawmidi_transmit_empty(s));
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
vt1724_midi_read(struct snd_ice1712 * ice)278*4882a593Smuzhiyun static void vt1724_midi_read(struct snd_ice1712 *ice)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun struct snd_rawmidi_substream *s;
281*4882a593Smuzhiyun int count, i;
282*4882a593Smuzhiyun u8 buffer[32];
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_INPUT);
285*4882a593Smuzhiyun count = inb(ICEREG1724(ice, MPU_RXFIFO));
286*4882a593Smuzhiyun if (count > 0) {
287*4882a593Smuzhiyun count = min(count, 32);
288*4882a593Smuzhiyun for (i = 0; i < count; ++i)
289*4882a593Smuzhiyun buffer[i] = inb(ICEREG1724(ice, MPU_DATA));
290*4882a593Smuzhiyun snd_rawmidi_receive(s, buffer, count);
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /* call with ice->reg_lock */
enable_midi_irq(struct snd_ice1712 * ice,u8 flag,int enable)295*4882a593Smuzhiyun static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun u8 mask = inb(ICEREG1724(ice, IRQMASK));
298*4882a593Smuzhiyun if (enable)
299*4882a593Smuzhiyun mask &= ~flag;
300*4882a593Smuzhiyun else
301*4882a593Smuzhiyun mask |= flag;
302*4882a593Smuzhiyun outb(mask, ICEREG1724(ice, IRQMASK));
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
vt1724_enable_midi_irq(struct snd_rawmidi_substream * substream,u8 flag,int enable)305*4882a593Smuzhiyun static void vt1724_enable_midi_irq(struct snd_rawmidi_substream *substream,
306*4882a593Smuzhiyun u8 flag, int enable)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun struct snd_ice1712 *ice = substream->rmidi->private_data;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
311*4882a593Smuzhiyun enable_midi_irq(ice, flag, enable);
312*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
vt1724_midi_output_open(struct snd_rawmidi_substream * s)315*4882a593Smuzhiyun static int vt1724_midi_output_open(struct snd_rawmidi_substream *s)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun return 0;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
vt1724_midi_output_close(struct snd_rawmidi_substream * s)320*4882a593Smuzhiyun static int vt1724_midi_output_close(struct snd_rawmidi_substream *s)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun return 0;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
vt1724_midi_output_trigger(struct snd_rawmidi_substream * s,int up)325*4882a593Smuzhiyun static void vt1724_midi_output_trigger(struct snd_rawmidi_substream *s, int up)
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun struct snd_ice1712 *ice = s->rmidi->private_data;
328*4882a593Smuzhiyun unsigned long flags;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun spin_lock_irqsave(&ice->reg_lock, flags);
331*4882a593Smuzhiyun if (up) {
332*4882a593Smuzhiyun ice->midi_output = 1;
333*4882a593Smuzhiyun vt1724_midi_write(ice);
334*4882a593Smuzhiyun } else {
335*4882a593Smuzhiyun ice->midi_output = 0;
336*4882a593Smuzhiyun enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun spin_unlock_irqrestore(&ice->reg_lock, flags);
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
vt1724_midi_output_drain(struct snd_rawmidi_substream * s)341*4882a593Smuzhiyun static void vt1724_midi_output_drain(struct snd_rawmidi_substream *s)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun struct snd_ice1712 *ice = s->rmidi->private_data;
344*4882a593Smuzhiyun unsigned long timeout;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_TX, 0);
347*4882a593Smuzhiyun /* 32 bytes should be transmitted in less than about 12 ms */
348*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(15);
349*4882a593Smuzhiyun do {
350*4882a593Smuzhiyun if (inb(ICEREG1724(ice, MPU_CTRL)) & VT1724_MPU_TX_EMPTY)
351*4882a593Smuzhiyun break;
352*4882a593Smuzhiyun schedule_timeout_uninterruptible(1);
353*4882a593Smuzhiyun } while (time_after(timeout, jiffies));
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun static const struct snd_rawmidi_ops vt1724_midi_output_ops = {
357*4882a593Smuzhiyun .open = vt1724_midi_output_open,
358*4882a593Smuzhiyun .close = vt1724_midi_output_close,
359*4882a593Smuzhiyun .trigger = vt1724_midi_output_trigger,
360*4882a593Smuzhiyun .drain = vt1724_midi_output_drain,
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun
vt1724_midi_input_open(struct snd_rawmidi_substream * s)363*4882a593Smuzhiyun static int vt1724_midi_input_open(struct snd_rawmidi_substream *s)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun vt1724_midi_clear_rx(s->rmidi->private_data);
366*4882a593Smuzhiyun vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 1);
367*4882a593Smuzhiyun return 0;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
vt1724_midi_input_close(struct snd_rawmidi_substream * s)370*4882a593Smuzhiyun static int vt1724_midi_input_close(struct snd_rawmidi_substream *s)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 0);
373*4882a593Smuzhiyun return 0;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
vt1724_midi_input_trigger(struct snd_rawmidi_substream * s,int up)376*4882a593Smuzhiyun static void vt1724_midi_input_trigger(struct snd_rawmidi_substream *s, int up)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun struct snd_ice1712 *ice = s->rmidi->private_data;
379*4882a593Smuzhiyun unsigned long flags;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun spin_lock_irqsave(&ice->reg_lock, flags);
382*4882a593Smuzhiyun if (up) {
383*4882a593Smuzhiyun ice->midi_input = 1;
384*4882a593Smuzhiyun vt1724_midi_read(ice);
385*4882a593Smuzhiyun } else {
386*4882a593Smuzhiyun ice->midi_input = 0;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun spin_unlock_irqrestore(&ice->reg_lock, flags);
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun static const struct snd_rawmidi_ops vt1724_midi_input_ops = {
392*4882a593Smuzhiyun .open = vt1724_midi_input_open,
393*4882a593Smuzhiyun .close = vt1724_midi_input_close,
394*4882a593Smuzhiyun .trigger = vt1724_midi_input_trigger,
395*4882a593Smuzhiyun };
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun /*
399*4882a593Smuzhiyun * Interrupt handler
400*4882a593Smuzhiyun */
401*4882a593Smuzhiyun
snd_vt1724_interrupt(int irq,void * dev_id)402*4882a593Smuzhiyun static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun struct snd_ice1712 *ice = dev_id;
405*4882a593Smuzhiyun unsigned char status;
406*4882a593Smuzhiyun unsigned char status_mask =
407*4882a593Smuzhiyun VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX | VT1724_IRQ_MTPCM;
408*4882a593Smuzhiyun int handled = 0;
409*4882a593Smuzhiyun int timeout = 0;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun while (1) {
412*4882a593Smuzhiyun status = inb(ICEREG1724(ice, IRQSTAT));
413*4882a593Smuzhiyun status &= status_mask;
414*4882a593Smuzhiyun if (status == 0)
415*4882a593Smuzhiyun break;
416*4882a593Smuzhiyun spin_lock(&ice->reg_lock);
417*4882a593Smuzhiyun if (++timeout > 10) {
418*4882a593Smuzhiyun status = inb(ICEREG1724(ice, IRQSTAT));
419*4882a593Smuzhiyun dev_err(ice->card->dev,
420*4882a593Smuzhiyun "Too long irq loop, status = 0x%x\n", status);
421*4882a593Smuzhiyun if (status & VT1724_IRQ_MPU_TX) {
422*4882a593Smuzhiyun dev_err(ice->card->dev, "Disabling MPU_TX\n");
423*4882a593Smuzhiyun enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun spin_unlock(&ice->reg_lock);
426*4882a593Smuzhiyun break;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun handled = 1;
429*4882a593Smuzhiyun if (status & VT1724_IRQ_MPU_TX) {
430*4882a593Smuzhiyun if (ice->midi_output)
431*4882a593Smuzhiyun vt1724_midi_write(ice);
432*4882a593Smuzhiyun else
433*4882a593Smuzhiyun enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
434*4882a593Smuzhiyun /* Due to mysterical reasons, MPU_TX is always
435*4882a593Smuzhiyun * generated (and can't be cleared) when a PCM
436*4882a593Smuzhiyun * playback is going. So let's ignore at the
437*4882a593Smuzhiyun * next loop.
438*4882a593Smuzhiyun */
439*4882a593Smuzhiyun status_mask &= ~VT1724_IRQ_MPU_TX;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun if (status & VT1724_IRQ_MPU_RX) {
442*4882a593Smuzhiyun if (ice->midi_input)
443*4882a593Smuzhiyun vt1724_midi_read(ice);
444*4882a593Smuzhiyun else
445*4882a593Smuzhiyun vt1724_midi_clear_rx(ice);
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun /* ack MPU irq */
448*4882a593Smuzhiyun outb(status, ICEREG1724(ice, IRQSTAT));
449*4882a593Smuzhiyun spin_unlock(&ice->reg_lock);
450*4882a593Smuzhiyun if (status & VT1724_IRQ_MTPCM) {
451*4882a593Smuzhiyun /*
452*4882a593Smuzhiyun * Multi-track PCM
453*4882a593Smuzhiyun * PCM assignment are:
454*4882a593Smuzhiyun * Playback DMA0 (M/C) = playback_pro_substream
455*4882a593Smuzhiyun * Playback DMA1 = playback_con_substream_ds[0]
456*4882a593Smuzhiyun * Playback DMA2 = playback_con_substream_ds[1]
457*4882a593Smuzhiyun * Playback DMA3 = playback_con_substream_ds[2]
458*4882a593Smuzhiyun * Playback DMA4 (SPDIF) = playback_con_substream
459*4882a593Smuzhiyun * Record DMA0 = capture_pro_substream
460*4882a593Smuzhiyun * Record DMA1 = capture_con_substream
461*4882a593Smuzhiyun */
462*4882a593Smuzhiyun unsigned char mtstat = inb(ICEMT1724(ice, IRQ));
463*4882a593Smuzhiyun if (mtstat & VT1724_MULTI_PDMA0) {
464*4882a593Smuzhiyun if (ice->playback_pro_substream)
465*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->playback_pro_substream);
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun if (mtstat & VT1724_MULTI_RDMA0) {
468*4882a593Smuzhiyun if (ice->capture_pro_substream)
469*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->capture_pro_substream);
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun if (mtstat & VT1724_MULTI_PDMA1) {
472*4882a593Smuzhiyun if (ice->playback_con_substream_ds[0])
473*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->playback_con_substream_ds[0]);
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun if (mtstat & VT1724_MULTI_PDMA2) {
476*4882a593Smuzhiyun if (ice->playback_con_substream_ds[1])
477*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->playback_con_substream_ds[1]);
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun if (mtstat & VT1724_MULTI_PDMA3) {
480*4882a593Smuzhiyun if (ice->playback_con_substream_ds[2])
481*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->playback_con_substream_ds[2]);
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun if (mtstat & VT1724_MULTI_PDMA4) {
484*4882a593Smuzhiyun if (ice->playback_con_substream)
485*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->playback_con_substream);
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun if (mtstat & VT1724_MULTI_RDMA1) {
488*4882a593Smuzhiyun if (ice->capture_con_substream)
489*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->capture_con_substream);
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun /* ack anyway to avoid freeze */
492*4882a593Smuzhiyun outb(mtstat, ICEMT1724(ice, IRQ));
493*4882a593Smuzhiyun /* ought to really handle this properly */
494*4882a593Smuzhiyun if (mtstat & VT1724_MULTI_FIFO_ERR) {
495*4882a593Smuzhiyun unsigned char fstat = inb(ICEMT1724(ice, DMA_FIFO_ERR));
496*4882a593Smuzhiyun outb(fstat, ICEMT1724(ice, DMA_FIFO_ERR));
497*4882a593Smuzhiyun outb(VT1724_MULTI_FIFO_ERR | inb(ICEMT1724(ice, DMA_INT_MASK)), ICEMT1724(ice, DMA_INT_MASK));
498*4882a593Smuzhiyun /* If I don't do this, I get machine lockup due to continual interrupts */
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun return IRQ_RETVAL(handled);
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun /*
507*4882a593Smuzhiyun * PCM code - professional part (multitrack)
508*4882a593Smuzhiyun */
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun static const unsigned int rates[] = {
511*4882a593Smuzhiyun 8000, 9600, 11025, 12000, 16000, 22050, 24000,
512*4882a593Smuzhiyun 32000, 44100, 48000, 64000, 88200, 96000,
513*4882a593Smuzhiyun 176400, 192000,
514*4882a593Smuzhiyun };
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list hw_constraints_rates_96 = {
517*4882a593Smuzhiyun .count = ARRAY_SIZE(rates) - 2, /* up to 96000 */
518*4882a593Smuzhiyun .list = rates,
519*4882a593Smuzhiyun .mask = 0,
520*4882a593Smuzhiyun };
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list hw_constraints_rates_48 = {
523*4882a593Smuzhiyun .count = ARRAY_SIZE(rates) - 5, /* up to 48000 */
524*4882a593Smuzhiyun .list = rates,
525*4882a593Smuzhiyun .mask = 0,
526*4882a593Smuzhiyun };
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list hw_constraints_rates_192 = {
529*4882a593Smuzhiyun .count = ARRAY_SIZE(rates),
530*4882a593Smuzhiyun .list = rates,
531*4882a593Smuzhiyun .mask = 0,
532*4882a593Smuzhiyun };
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun struct vt1724_pcm_reg {
535*4882a593Smuzhiyun unsigned int addr; /* ADDR register offset */
536*4882a593Smuzhiyun unsigned int size; /* SIZE register offset */
537*4882a593Smuzhiyun unsigned int count; /* COUNT register offset */
538*4882a593Smuzhiyun unsigned int start; /* start & pause bit */
539*4882a593Smuzhiyun };
540*4882a593Smuzhiyun
snd_vt1724_pcm_trigger(struct snd_pcm_substream * substream,int cmd)541*4882a593Smuzhiyun static int snd_vt1724_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
544*4882a593Smuzhiyun unsigned char what;
545*4882a593Smuzhiyun unsigned char old;
546*4882a593Smuzhiyun struct snd_pcm_substream *s;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun what = 0;
549*4882a593Smuzhiyun snd_pcm_group_for_each_entry(s, substream) {
550*4882a593Smuzhiyun if (snd_pcm_substream_chip(s) == ice) {
551*4882a593Smuzhiyun const struct vt1724_pcm_reg *reg;
552*4882a593Smuzhiyun reg = s->runtime->private_data;
553*4882a593Smuzhiyun what |= reg->start;
554*4882a593Smuzhiyun snd_pcm_trigger_done(s, substream);
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun switch (cmd) {
559*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
560*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
561*4882a593Smuzhiyun spin_lock(&ice->reg_lock);
562*4882a593Smuzhiyun old = inb(ICEMT1724(ice, DMA_PAUSE));
563*4882a593Smuzhiyun if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
564*4882a593Smuzhiyun old |= what;
565*4882a593Smuzhiyun else
566*4882a593Smuzhiyun old &= ~what;
567*4882a593Smuzhiyun outb(old, ICEMT1724(ice, DMA_PAUSE));
568*4882a593Smuzhiyun spin_unlock(&ice->reg_lock);
569*4882a593Smuzhiyun break;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
572*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
573*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
574*4882a593Smuzhiyun spin_lock(&ice->reg_lock);
575*4882a593Smuzhiyun old = inb(ICEMT1724(ice, DMA_CONTROL));
576*4882a593Smuzhiyun if (cmd == SNDRV_PCM_TRIGGER_START)
577*4882a593Smuzhiyun old |= what;
578*4882a593Smuzhiyun else
579*4882a593Smuzhiyun old &= ~what;
580*4882a593Smuzhiyun outb(old, ICEMT1724(ice, DMA_CONTROL));
581*4882a593Smuzhiyun spin_unlock(&ice->reg_lock);
582*4882a593Smuzhiyun break;
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
585*4882a593Smuzhiyun /* apps will have to restart stream */
586*4882a593Smuzhiyun break;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun default:
589*4882a593Smuzhiyun return -EINVAL;
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun return 0;
592*4882a593Smuzhiyun }
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun /*
595*4882a593Smuzhiyun */
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun #define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
598*4882a593Smuzhiyun VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
599*4882a593Smuzhiyun #define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
600*4882a593Smuzhiyun VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun static const unsigned int stdclock_rate_list[16] = {
603*4882a593Smuzhiyun 48000, 24000, 12000, 9600, 32000, 16000, 8000, 96000, 44100,
604*4882a593Smuzhiyun 22050, 11025, 88200, 176400, 0, 192000, 64000
605*4882a593Smuzhiyun };
606*4882a593Smuzhiyun
stdclock_get_rate(struct snd_ice1712 * ice)607*4882a593Smuzhiyun static unsigned int stdclock_get_rate(struct snd_ice1712 *ice)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun return stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15];
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun
stdclock_set_rate(struct snd_ice1712 * ice,unsigned int rate)612*4882a593Smuzhiyun static void stdclock_set_rate(struct snd_ice1712 *ice, unsigned int rate)
613*4882a593Smuzhiyun {
614*4882a593Smuzhiyun int i;
615*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(stdclock_rate_list); i++) {
616*4882a593Smuzhiyun if (stdclock_rate_list[i] == rate) {
617*4882a593Smuzhiyun outb(i, ICEMT1724(ice, RATE));
618*4882a593Smuzhiyun return;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun
stdclock_set_mclk(struct snd_ice1712 * ice,unsigned int rate)623*4882a593Smuzhiyun static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
624*4882a593Smuzhiyun unsigned int rate)
625*4882a593Smuzhiyun {
626*4882a593Smuzhiyun unsigned char val, old;
627*4882a593Smuzhiyun /* check MT02 */
628*4882a593Smuzhiyun if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
629*4882a593Smuzhiyun val = old = inb(ICEMT1724(ice, I2S_FORMAT));
630*4882a593Smuzhiyun if (rate > 96000)
631*4882a593Smuzhiyun val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
632*4882a593Smuzhiyun else
633*4882a593Smuzhiyun val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
634*4882a593Smuzhiyun if (val != old) {
635*4882a593Smuzhiyun outb(val, ICEMT1724(ice, I2S_FORMAT));
636*4882a593Smuzhiyun /* master clock changed */
637*4882a593Smuzhiyun return 1;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun /* no change in master clock */
641*4882a593Smuzhiyun return 0;
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun
snd_vt1724_set_pro_rate(struct snd_ice1712 * ice,unsigned int rate,int force)644*4882a593Smuzhiyun static int snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
645*4882a593Smuzhiyun int force)
646*4882a593Smuzhiyun {
647*4882a593Smuzhiyun unsigned long flags;
648*4882a593Smuzhiyun unsigned char mclk_change;
649*4882a593Smuzhiyun unsigned int i, old_rate;
650*4882a593Smuzhiyun bool call_set_rate = false;
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
653*4882a593Smuzhiyun return -EINVAL;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun spin_lock_irqsave(&ice->reg_lock, flags);
656*4882a593Smuzhiyun if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
657*4882a593Smuzhiyun (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
658*4882a593Smuzhiyun /* running? we cannot change the rate now... */
659*4882a593Smuzhiyun spin_unlock_irqrestore(&ice->reg_lock, flags);
660*4882a593Smuzhiyun return ((rate == ice->cur_rate) && !force) ? 0 : -EBUSY;
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun if (!force && is_pro_rate_locked(ice)) {
663*4882a593Smuzhiyun /* comparing required and current rate - makes sense for
664*4882a593Smuzhiyun * internal clock only */
665*4882a593Smuzhiyun spin_unlock_irqrestore(&ice->reg_lock, flags);
666*4882a593Smuzhiyun return (rate == ice->cur_rate) ? 0 : -EBUSY;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun if (force || !ice->is_spdif_master(ice)) {
670*4882a593Smuzhiyun /* force means the rate was switched by ucontrol, otherwise
671*4882a593Smuzhiyun * setting clock rate for internal clock mode */
672*4882a593Smuzhiyun old_rate = ice->get_rate(ice);
673*4882a593Smuzhiyun if (force || (old_rate != rate))
674*4882a593Smuzhiyun call_set_rate = true;
675*4882a593Smuzhiyun else if (rate == ice->cur_rate) {
676*4882a593Smuzhiyun spin_unlock_irqrestore(&ice->reg_lock, flags);
677*4882a593Smuzhiyun return 0;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun ice->cur_rate = rate;
682*4882a593Smuzhiyun spin_unlock_irqrestore(&ice->reg_lock, flags);
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun if (call_set_rate)
685*4882a593Smuzhiyun ice->set_rate(ice, rate);
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun /* setting master clock */
688*4882a593Smuzhiyun mclk_change = ice->set_mclk(ice, rate);
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun if (mclk_change && ice->gpio.i2s_mclk_changed)
691*4882a593Smuzhiyun ice->gpio.i2s_mclk_changed(ice);
692*4882a593Smuzhiyun if (ice->gpio.set_pro_rate)
693*4882a593Smuzhiyun ice->gpio.set_pro_rate(ice, rate);
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun /* set up codecs */
696*4882a593Smuzhiyun for (i = 0; i < ice->akm_codecs; i++) {
697*4882a593Smuzhiyun if (ice->akm[i].ops.set_rate_val)
698*4882a593Smuzhiyun ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun if (ice->spdif.ops.setup_rate)
701*4882a593Smuzhiyun ice->spdif.ops.setup_rate(ice, rate);
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun return 0;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun
snd_vt1724_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)706*4882a593Smuzhiyun static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
707*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params)
708*4882a593Smuzhiyun {
709*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
710*4882a593Smuzhiyun int i, chs;
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun chs = params_channels(hw_params);
713*4882a593Smuzhiyun mutex_lock(&ice->open_mutex);
714*4882a593Smuzhiyun /* mark surround channels */
715*4882a593Smuzhiyun if (substream == ice->playback_pro_substream) {
716*4882a593Smuzhiyun /* PDMA0 can be multi-channel up to 8 */
717*4882a593Smuzhiyun chs = chs / 2 - 1;
718*4882a593Smuzhiyun for (i = 0; i < chs; i++) {
719*4882a593Smuzhiyun if (ice->pcm_reserved[i] &&
720*4882a593Smuzhiyun ice->pcm_reserved[i] != substream) {
721*4882a593Smuzhiyun mutex_unlock(&ice->open_mutex);
722*4882a593Smuzhiyun return -EBUSY;
723*4882a593Smuzhiyun }
724*4882a593Smuzhiyun ice->pcm_reserved[i] = substream;
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun for (; i < 3; i++) {
727*4882a593Smuzhiyun if (ice->pcm_reserved[i] == substream)
728*4882a593Smuzhiyun ice->pcm_reserved[i] = NULL;
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun } else {
731*4882a593Smuzhiyun for (i = 0; i < 3; i++) {
732*4882a593Smuzhiyun /* check individual playback stream */
733*4882a593Smuzhiyun if (ice->playback_con_substream_ds[i] == substream) {
734*4882a593Smuzhiyun if (ice->pcm_reserved[i] &&
735*4882a593Smuzhiyun ice->pcm_reserved[i] != substream) {
736*4882a593Smuzhiyun mutex_unlock(&ice->open_mutex);
737*4882a593Smuzhiyun return -EBUSY;
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun ice->pcm_reserved[i] = substream;
740*4882a593Smuzhiyun break;
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun mutex_unlock(&ice->open_mutex);
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun return snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0);
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun
snd_vt1724_pcm_hw_free(struct snd_pcm_substream * substream)749*4882a593Smuzhiyun static int snd_vt1724_pcm_hw_free(struct snd_pcm_substream *substream)
750*4882a593Smuzhiyun {
751*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
752*4882a593Smuzhiyun int i;
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun mutex_lock(&ice->open_mutex);
755*4882a593Smuzhiyun /* unmark surround channels */
756*4882a593Smuzhiyun for (i = 0; i < 3; i++)
757*4882a593Smuzhiyun if (ice->pcm_reserved[i] == substream)
758*4882a593Smuzhiyun ice->pcm_reserved[i] = NULL;
759*4882a593Smuzhiyun mutex_unlock(&ice->open_mutex);
760*4882a593Smuzhiyun return 0;
761*4882a593Smuzhiyun }
762*4882a593Smuzhiyun
snd_vt1724_playback_pro_prepare(struct snd_pcm_substream * substream)763*4882a593Smuzhiyun static int snd_vt1724_playback_pro_prepare(struct snd_pcm_substream *substream)
764*4882a593Smuzhiyun {
765*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
766*4882a593Smuzhiyun unsigned char val;
767*4882a593Smuzhiyun unsigned int size;
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
770*4882a593Smuzhiyun val = (8 - substream->runtime->channels) >> 1;
771*4882a593Smuzhiyun outb(val, ICEMT1724(ice, BURST));
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun outl(substream->runtime->dma_addr, ICEMT1724(ice, PLAYBACK_ADDR));
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun size = (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1;
776*4882a593Smuzhiyun /* outl(size, ICEMT1724(ice, PLAYBACK_SIZE)); */
777*4882a593Smuzhiyun outw(size, ICEMT1724(ice, PLAYBACK_SIZE));
778*4882a593Smuzhiyun outb(size >> 16, ICEMT1724(ice, PLAYBACK_SIZE) + 2);
779*4882a593Smuzhiyun size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
780*4882a593Smuzhiyun /* outl(size, ICEMT1724(ice, PLAYBACK_COUNT)); */
781*4882a593Smuzhiyun outw(size, ICEMT1724(ice, PLAYBACK_COUNT));
782*4882a593Smuzhiyun outb(size >> 16, ICEMT1724(ice, PLAYBACK_COUNT) + 2);
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun /*
787*4882a593Smuzhiyun dev_dbg(ice->card->dev, "pro prepare: ch = %d, addr = 0x%x, "
788*4882a593Smuzhiyun "buffer = 0x%x, period = 0x%x\n",
789*4882a593Smuzhiyun substream->runtime->channels,
790*4882a593Smuzhiyun (unsigned int)substream->runtime->dma_addr,
791*4882a593Smuzhiyun snd_pcm_lib_buffer_bytes(substream),
792*4882a593Smuzhiyun snd_pcm_lib_period_bytes(substream));
793*4882a593Smuzhiyun */
794*4882a593Smuzhiyun return 0;
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun
snd_vt1724_playback_pro_pointer(struct snd_pcm_substream * substream)797*4882a593Smuzhiyun static snd_pcm_uframes_t snd_vt1724_playback_pro_pointer(struct snd_pcm_substream *substream)
798*4882a593Smuzhiyun {
799*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
800*4882a593Smuzhiyun size_t ptr;
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & VT1724_PDMA0_START))
803*4882a593Smuzhiyun return 0;
804*4882a593Smuzhiyun #if 0 /* read PLAYBACK_ADDR */
805*4882a593Smuzhiyun ptr = inl(ICEMT1724(ice, PLAYBACK_ADDR));
806*4882a593Smuzhiyun if (ptr < substream->runtime->dma_addr) {
807*4882a593Smuzhiyun dev_dbg(ice->card->dev, "invalid negative ptr\n");
808*4882a593Smuzhiyun return 0;
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun ptr -= substream->runtime->dma_addr;
811*4882a593Smuzhiyun ptr = bytes_to_frames(substream->runtime, ptr);
812*4882a593Smuzhiyun if (ptr >= substream->runtime->buffer_size) {
813*4882a593Smuzhiyun dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
814*4882a593Smuzhiyun (int)ptr, (int)substream->runtime->period_size);
815*4882a593Smuzhiyun return 0;
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun #else /* read PLAYBACK_SIZE */
818*4882a593Smuzhiyun ptr = inl(ICEMT1724(ice, PLAYBACK_SIZE)) & 0xffffff;
819*4882a593Smuzhiyun ptr = (ptr + 1) << 2;
820*4882a593Smuzhiyun ptr = bytes_to_frames(substream->runtime, ptr);
821*4882a593Smuzhiyun if (!ptr)
822*4882a593Smuzhiyun ;
823*4882a593Smuzhiyun else if (ptr <= substream->runtime->buffer_size)
824*4882a593Smuzhiyun ptr = substream->runtime->buffer_size - ptr;
825*4882a593Smuzhiyun else {
826*4882a593Smuzhiyun dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
827*4882a593Smuzhiyun (int)ptr, (int)substream->runtime->buffer_size);
828*4882a593Smuzhiyun ptr = 0;
829*4882a593Smuzhiyun }
830*4882a593Smuzhiyun #endif
831*4882a593Smuzhiyun return ptr;
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun
snd_vt1724_pcm_prepare(struct snd_pcm_substream * substream)834*4882a593Smuzhiyun static int snd_vt1724_pcm_prepare(struct snd_pcm_substream *substream)
835*4882a593Smuzhiyun {
836*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
837*4882a593Smuzhiyun const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
840*4882a593Smuzhiyun outl(substream->runtime->dma_addr, ice->profi_port + reg->addr);
841*4882a593Smuzhiyun outw((snd_pcm_lib_buffer_bytes(substream) >> 2) - 1,
842*4882a593Smuzhiyun ice->profi_port + reg->size);
843*4882a593Smuzhiyun outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1,
844*4882a593Smuzhiyun ice->profi_port + reg->count);
845*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
846*4882a593Smuzhiyun return 0;
847*4882a593Smuzhiyun }
848*4882a593Smuzhiyun
snd_vt1724_pcm_pointer(struct snd_pcm_substream * substream)849*4882a593Smuzhiyun static snd_pcm_uframes_t snd_vt1724_pcm_pointer(struct snd_pcm_substream *substream)
850*4882a593Smuzhiyun {
851*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
852*4882a593Smuzhiyun const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
853*4882a593Smuzhiyun size_t ptr;
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start))
856*4882a593Smuzhiyun return 0;
857*4882a593Smuzhiyun #if 0 /* use ADDR register */
858*4882a593Smuzhiyun ptr = inl(ice->profi_port + reg->addr);
859*4882a593Smuzhiyun ptr -= substream->runtime->dma_addr;
860*4882a593Smuzhiyun return bytes_to_frames(substream->runtime, ptr);
861*4882a593Smuzhiyun #else /* use SIZE register */
862*4882a593Smuzhiyun ptr = inw(ice->profi_port + reg->size);
863*4882a593Smuzhiyun ptr = (ptr + 1) << 2;
864*4882a593Smuzhiyun ptr = bytes_to_frames(substream->runtime, ptr);
865*4882a593Smuzhiyun if (!ptr)
866*4882a593Smuzhiyun ;
867*4882a593Smuzhiyun else if (ptr <= substream->runtime->buffer_size)
868*4882a593Smuzhiyun ptr = substream->runtime->buffer_size - ptr;
869*4882a593Smuzhiyun else {
870*4882a593Smuzhiyun dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
871*4882a593Smuzhiyun (int)ptr, (int)substream->runtime->buffer_size);
872*4882a593Smuzhiyun ptr = 0;
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun return ptr;
875*4882a593Smuzhiyun #endif
876*4882a593Smuzhiyun }
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun static const struct vt1724_pcm_reg vt1724_pdma0_reg = {
879*4882a593Smuzhiyun .addr = VT1724_MT_PLAYBACK_ADDR,
880*4882a593Smuzhiyun .size = VT1724_MT_PLAYBACK_SIZE,
881*4882a593Smuzhiyun .count = VT1724_MT_PLAYBACK_COUNT,
882*4882a593Smuzhiyun .start = VT1724_PDMA0_START,
883*4882a593Smuzhiyun };
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun static const struct vt1724_pcm_reg vt1724_pdma4_reg = {
886*4882a593Smuzhiyun .addr = VT1724_MT_PDMA4_ADDR,
887*4882a593Smuzhiyun .size = VT1724_MT_PDMA4_SIZE,
888*4882a593Smuzhiyun .count = VT1724_MT_PDMA4_COUNT,
889*4882a593Smuzhiyun .start = VT1724_PDMA4_START,
890*4882a593Smuzhiyun };
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun static const struct vt1724_pcm_reg vt1724_rdma0_reg = {
893*4882a593Smuzhiyun .addr = VT1724_MT_CAPTURE_ADDR,
894*4882a593Smuzhiyun .size = VT1724_MT_CAPTURE_SIZE,
895*4882a593Smuzhiyun .count = VT1724_MT_CAPTURE_COUNT,
896*4882a593Smuzhiyun .start = VT1724_RDMA0_START,
897*4882a593Smuzhiyun };
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun static const struct vt1724_pcm_reg vt1724_rdma1_reg = {
900*4882a593Smuzhiyun .addr = VT1724_MT_RDMA1_ADDR,
901*4882a593Smuzhiyun .size = VT1724_MT_RDMA1_SIZE,
902*4882a593Smuzhiyun .count = VT1724_MT_RDMA1_COUNT,
903*4882a593Smuzhiyun .start = VT1724_RDMA1_START,
904*4882a593Smuzhiyun };
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun #define vt1724_playback_pro_reg vt1724_pdma0_reg
907*4882a593Smuzhiyun #define vt1724_playback_spdif_reg vt1724_pdma4_reg
908*4882a593Smuzhiyun #define vt1724_capture_pro_reg vt1724_rdma0_reg
909*4882a593Smuzhiyun #define vt1724_capture_spdif_reg vt1724_rdma1_reg
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_vt1724_playback_pro = {
912*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
913*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
914*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
915*4882a593Smuzhiyun SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
916*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S32_LE,
917*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
918*4882a593Smuzhiyun .rate_min = 8000,
919*4882a593Smuzhiyun .rate_max = 192000,
920*4882a593Smuzhiyun .channels_min = 2,
921*4882a593Smuzhiyun .channels_max = 8,
922*4882a593Smuzhiyun .buffer_bytes_max = (1UL << 21), /* 19bits dword */
923*4882a593Smuzhiyun .period_bytes_min = 8 * 4 * 2, /* FIXME: constraints needed */
924*4882a593Smuzhiyun .period_bytes_max = (1UL << 21),
925*4882a593Smuzhiyun .periods_min = 2,
926*4882a593Smuzhiyun .periods_max = 1024,
927*4882a593Smuzhiyun };
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_vt1724_spdif = {
930*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
931*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
932*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
933*4882a593Smuzhiyun SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
934*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S32_LE,
935*4882a593Smuzhiyun .rates = (SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|
936*4882a593Smuzhiyun SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_88200|
937*4882a593Smuzhiyun SNDRV_PCM_RATE_96000|SNDRV_PCM_RATE_176400|
938*4882a593Smuzhiyun SNDRV_PCM_RATE_192000),
939*4882a593Smuzhiyun .rate_min = 32000,
940*4882a593Smuzhiyun .rate_max = 192000,
941*4882a593Smuzhiyun .channels_min = 2,
942*4882a593Smuzhiyun .channels_max = 2,
943*4882a593Smuzhiyun .buffer_bytes_max = (1UL << 18), /* 16bits dword */
944*4882a593Smuzhiyun .period_bytes_min = 2 * 4 * 2,
945*4882a593Smuzhiyun .period_bytes_max = (1UL << 18),
946*4882a593Smuzhiyun .periods_min = 2,
947*4882a593Smuzhiyun .periods_max = 1024,
948*4882a593Smuzhiyun };
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_vt1724_2ch_stereo = {
951*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
952*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
953*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
954*4882a593Smuzhiyun SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
955*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S32_LE,
956*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
957*4882a593Smuzhiyun .rate_min = 8000,
958*4882a593Smuzhiyun .rate_max = 192000,
959*4882a593Smuzhiyun .channels_min = 2,
960*4882a593Smuzhiyun .channels_max = 2,
961*4882a593Smuzhiyun .buffer_bytes_max = (1UL << 18), /* 16bits dword */
962*4882a593Smuzhiyun .period_bytes_min = 2 * 4 * 2,
963*4882a593Smuzhiyun .period_bytes_max = (1UL << 18),
964*4882a593Smuzhiyun .periods_min = 2,
965*4882a593Smuzhiyun .periods_max = 1024,
966*4882a593Smuzhiyun };
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun /*
969*4882a593Smuzhiyun * set rate constraints
970*4882a593Smuzhiyun */
set_std_hw_rates(struct snd_ice1712 * ice)971*4882a593Smuzhiyun static void set_std_hw_rates(struct snd_ice1712 *ice)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
974*4882a593Smuzhiyun /* I2S */
975*4882a593Smuzhiyun /* VT1720 doesn't support more than 96kHz */
976*4882a593Smuzhiyun if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
977*4882a593Smuzhiyun ice->hw_rates = &hw_constraints_rates_192;
978*4882a593Smuzhiyun else
979*4882a593Smuzhiyun ice->hw_rates = &hw_constraints_rates_96;
980*4882a593Smuzhiyun } else {
981*4882a593Smuzhiyun /* ACLINK */
982*4882a593Smuzhiyun ice->hw_rates = &hw_constraints_rates_48;
983*4882a593Smuzhiyun }
984*4882a593Smuzhiyun }
985*4882a593Smuzhiyun
set_rate_constraints(struct snd_ice1712 * ice,struct snd_pcm_substream * substream)986*4882a593Smuzhiyun static int set_rate_constraints(struct snd_ice1712 *ice,
987*4882a593Smuzhiyun struct snd_pcm_substream *substream)
988*4882a593Smuzhiyun {
989*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun runtime->hw.rate_min = ice->hw_rates->list[0];
992*4882a593Smuzhiyun runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
993*4882a593Smuzhiyun runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
994*4882a593Smuzhiyun return snd_pcm_hw_constraint_list(runtime, 0,
995*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE,
996*4882a593Smuzhiyun ice->hw_rates);
997*4882a593Smuzhiyun }
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun /* if the card has the internal rate locked (is_pro_locked), limit runtime
1000*4882a593Smuzhiyun hw rates to the current internal rate only.
1001*4882a593Smuzhiyun */
constrain_rate_if_locked(struct snd_pcm_substream * substream)1002*4882a593Smuzhiyun static void constrain_rate_if_locked(struct snd_pcm_substream *substream)
1003*4882a593Smuzhiyun {
1004*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1005*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
1006*4882a593Smuzhiyun unsigned int rate;
1007*4882a593Smuzhiyun if (is_pro_rate_locked(ice)) {
1008*4882a593Smuzhiyun rate = ice->get_rate(ice);
1009*4882a593Smuzhiyun if (rate >= runtime->hw.rate_min
1010*4882a593Smuzhiyun && rate <= runtime->hw.rate_max) {
1011*4882a593Smuzhiyun runtime->hw.rate_min = rate;
1012*4882a593Smuzhiyun runtime->hw.rate_max = rate;
1013*4882a593Smuzhiyun }
1014*4882a593Smuzhiyun }
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun /* multi-channel playback needs alignment 8x32bit regardless of the channels
1019*4882a593Smuzhiyun * actually used
1020*4882a593Smuzhiyun */
1021*4882a593Smuzhiyun #define VT1724_BUFFER_ALIGN 0x20
1022*4882a593Smuzhiyun
snd_vt1724_playback_pro_open(struct snd_pcm_substream * substream)1023*4882a593Smuzhiyun static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
1024*4882a593Smuzhiyun {
1025*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
1026*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1027*4882a593Smuzhiyun int chs, num_indeps;
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun runtime->private_data = (void *)&vt1724_playback_pro_reg;
1030*4882a593Smuzhiyun ice->playback_pro_substream = substream;
1031*4882a593Smuzhiyun runtime->hw = snd_vt1724_playback_pro;
1032*4882a593Smuzhiyun snd_pcm_set_sync(substream);
1033*4882a593Smuzhiyun snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1034*4882a593Smuzhiyun set_rate_constraints(ice, substream);
1035*4882a593Smuzhiyun mutex_lock(&ice->open_mutex);
1036*4882a593Smuzhiyun /* calculate the currently available channels */
1037*4882a593Smuzhiyun num_indeps = ice->num_total_dacs / 2 - 1;
1038*4882a593Smuzhiyun for (chs = 0; chs < num_indeps; chs++) {
1039*4882a593Smuzhiyun if (ice->pcm_reserved[chs])
1040*4882a593Smuzhiyun break;
1041*4882a593Smuzhiyun }
1042*4882a593Smuzhiyun chs = (chs + 1) * 2;
1043*4882a593Smuzhiyun runtime->hw.channels_max = chs;
1044*4882a593Smuzhiyun if (chs > 2) /* channels must be even */
1045*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1046*4882a593Smuzhiyun mutex_unlock(&ice->open_mutex);
1047*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1048*4882a593Smuzhiyun VT1724_BUFFER_ALIGN);
1049*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1050*4882a593Smuzhiyun VT1724_BUFFER_ALIGN);
1051*4882a593Smuzhiyun constrain_rate_if_locked(substream);
1052*4882a593Smuzhiyun if (ice->pro_open)
1053*4882a593Smuzhiyun ice->pro_open(ice, substream);
1054*4882a593Smuzhiyun return 0;
1055*4882a593Smuzhiyun }
1056*4882a593Smuzhiyun
snd_vt1724_capture_pro_open(struct snd_pcm_substream * substream)1057*4882a593Smuzhiyun static int snd_vt1724_capture_pro_open(struct snd_pcm_substream *substream)
1058*4882a593Smuzhiyun {
1059*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1060*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun runtime->private_data = (void *)&vt1724_capture_pro_reg;
1063*4882a593Smuzhiyun ice->capture_pro_substream = substream;
1064*4882a593Smuzhiyun runtime->hw = snd_vt1724_2ch_stereo;
1065*4882a593Smuzhiyun snd_pcm_set_sync(substream);
1066*4882a593Smuzhiyun snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1067*4882a593Smuzhiyun set_rate_constraints(ice, substream);
1068*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1069*4882a593Smuzhiyun VT1724_BUFFER_ALIGN);
1070*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1071*4882a593Smuzhiyun VT1724_BUFFER_ALIGN);
1072*4882a593Smuzhiyun constrain_rate_if_locked(substream);
1073*4882a593Smuzhiyun if (ice->pro_open)
1074*4882a593Smuzhiyun ice->pro_open(ice, substream);
1075*4882a593Smuzhiyun return 0;
1076*4882a593Smuzhiyun }
1077*4882a593Smuzhiyun
snd_vt1724_playback_pro_close(struct snd_pcm_substream * substream)1078*4882a593Smuzhiyun static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
1079*4882a593Smuzhiyun {
1080*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun if (PRO_RATE_RESET)
1083*4882a593Smuzhiyun snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1084*4882a593Smuzhiyun ice->playback_pro_substream = NULL;
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun return 0;
1087*4882a593Smuzhiyun }
1088*4882a593Smuzhiyun
snd_vt1724_capture_pro_close(struct snd_pcm_substream * substream)1089*4882a593Smuzhiyun static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
1090*4882a593Smuzhiyun {
1091*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun if (PRO_RATE_RESET)
1094*4882a593Smuzhiyun snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1095*4882a593Smuzhiyun ice->capture_pro_substream = NULL;
1096*4882a593Smuzhiyun return 0;
1097*4882a593Smuzhiyun }
1098*4882a593Smuzhiyun
1099*4882a593Smuzhiyun static const struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
1100*4882a593Smuzhiyun .open = snd_vt1724_playback_pro_open,
1101*4882a593Smuzhiyun .close = snd_vt1724_playback_pro_close,
1102*4882a593Smuzhiyun .hw_params = snd_vt1724_pcm_hw_params,
1103*4882a593Smuzhiyun .hw_free = snd_vt1724_pcm_hw_free,
1104*4882a593Smuzhiyun .prepare = snd_vt1724_playback_pro_prepare,
1105*4882a593Smuzhiyun .trigger = snd_vt1724_pcm_trigger,
1106*4882a593Smuzhiyun .pointer = snd_vt1724_playback_pro_pointer,
1107*4882a593Smuzhiyun };
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun static const struct snd_pcm_ops snd_vt1724_capture_pro_ops = {
1110*4882a593Smuzhiyun .open = snd_vt1724_capture_pro_open,
1111*4882a593Smuzhiyun .close = snd_vt1724_capture_pro_close,
1112*4882a593Smuzhiyun .hw_params = snd_vt1724_pcm_hw_params,
1113*4882a593Smuzhiyun .hw_free = snd_vt1724_pcm_hw_free,
1114*4882a593Smuzhiyun .prepare = snd_vt1724_pcm_prepare,
1115*4882a593Smuzhiyun .trigger = snd_vt1724_pcm_trigger,
1116*4882a593Smuzhiyun .pointer = snd_vt1724_pcm_pointer,
1117*4882a593Smuzhiyun };
1118*4882a593Smuzhiyun
snd_vt1724_pcm_profi(struct snd_ice1712 * ice,int device)1119*4882a593Smuzhiyun static int snd_vt1724_pcm_profi(struct snd_ice1712 *ice, int device)
1120*4882a593Smuzhiyun {
1121*4882a593Smuzhiyun struct snd_pcm *pcm;
1122*4882a593Smuzhiyun int capt, err;
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun if ((ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_ADC_MASK) ==
1125*4882a593Smuzhiyun VT1724_CFG_ADC_NONE)
1126*4882a593Smuzhiyun capt = 0;
1127*4882a593Smuzhiyun else
1128*4882a593Smuzhiyun capt = 1;
1129*4882a593Smuzhiyun err = snd_pcm_new(ice->card, "ICE1724", device, 1, capt, &pcm);
1130*4882a593Smuzhiyun if (err < 0)
1131*4882a593Smuzhiyun return err;
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_vt1724_playback_pro_ops);
1134*4882a593Smuzhiyun if (capt)
1135*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1136*4882a593Smuzhiyun &snd_vt1724_capture_pro_ops);
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun pcm->private_data = ice;
1139*4882a593Smuzhiyun pcm->info_flags = 0;
1140*4882a593Smuzhiyun strcpy(pcm->name, "ICE1724");
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1143*4882a593Smuzhiyun &ice->pci->dev, 256*1024, 256*1024);
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun ice->pcm_pro = pcm;
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun return 0;
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun /*
1152*4882a593Smuzhiyun * SPDIF PCM
1153*4882a593Smuzhiyun */
1154*4882a593Smuzhiyun
1155*4882a593Smuzhiyun /* update spdif control bits; call with reg_lock */
update_spdif_bits(struct snd_ice1712 * ice,unsigned int val)1156*4882a593Smuzhiyun static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val)
1157*4882a593Smuzhiyun {
1158*4882a593Smuzhiyun unsigned char cbit, disabled;
1159*4882a593Smuzhiyun
1160*4882a593Smuzhiyun cbit = inb(ICEREG1724(ice, SPDIF_CFG));
1161*4882a593Smuzhiyun disabled = cbit & ~VT1724_CFG_SPDIF_OUT_EN;
1162*4882a593Smuzhiyun if (cbit != disabled)
1163*4882a593Smuzhiyun outb(disabled, ICEREG1724(ice, SPDIF_CFG));
1164*4882a593Smuzhiyun outw(val, ICEMT1724(ice, SPDIF_CTRL));
1165*4882a593Smuzhiyun if (cbit != disabled)
1166*4882a593Smuzhiyun outb(cbit, ICEREG1724(ice, SPDIF_CFG));
1167*4882a593Smuzhiyun outw(val, ICEMT1724(ice, SPDIF_CTRL));
1168*4882a593Smuzhiyun }
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun /* update SPDIF control bits according to the given rate */
update_spdif_rate(struct snd_ice1712 * ice,unsigned int rate)1171*4882a593Smuzhiyun static void update_spdif_rate(struct snd_ice1712 *ice, unsigned int rate)
1172*4882a593Smuzhiyun {
1173*4882a593Smuzhiyun unsigned int val, nval;
1174*4882a593Smuzhiyun unsigned long flags;
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun spin_lock_irqsave(&ice->reg_lock, flags);
1177*4882a593Smuzhiyun nval = val = inw(ICEMT1724(ice, SPDIF_CTRL));
1178*4882a593Smuzhiyun nval &= ~(7 << 12);
1179*4882a593Smuzhiyun switch (rate) {
1180*4882a593Smuzhiyun case 44100: break;
1181*4882a593Smuzhiyun case 48000: nval |= 2 << 12; break;
1182*4882a593Smuzhiyun case 32000: nval |= 3 << 12; break;
1183*4882a593Smuzhiyun case 88200: nval |= 4 << 12; break;
1184*4882a593Smuzhiyun case 96000: nval |= 5 << 12; break;
1185*4882a593Smuzhiyun case 192000: nval |= 6 << 12; break;
1186*4882a593Smuzhiyun case 176400: nval |= 7 << 12; break;
1187*4882a593Smuzhiyun }
1188*4882a593Smuzhiyun if (val != nval)
1189*4882a593Smuzhiyun update_spdif_bits(ice, nval);
1190*4882a593Smuzhiyun spin_unlock_irqrestore(&ice->reg_lock, flags);
1191*4882a593Smuzhiyun }
1192*4882a593Smuzhiyun
snd_vt1724_playback_spdif_prepare(struct snd_pcm_substream * substream)1193*4882a593Smuzhiyun static int snd_vt1724_playback_spdif_prepare(struct snd_pcm_substream *substream)
1194*4882a593Smuzhiyun {
1195*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1196*4882a593Smuzhiyun if (!ice->force_pdma4)
1197*4882a593Smuzhiyun update_spdif_rate(ice, substream->runtime->rate);
1198*4882a593Smuzhiyun return snd_vt1724_pcm_prepare(substream);
1199*4882a593Smuzhiyun }
1200*4882a593Smuzhiyun
snd_vt1724_playback_spdif_open(struct snd_pcm_substream * substream)1201*4882a593Smuzhiyun static int snd_vt1724_playback_spdif_open(struct snd_pcm_substream *substream)
1202*4882a593Smuzhiyun {
1203*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1204*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun runtime->private_data = (void *)&vt1724_playback_spdif_reg;
1207*4882a593Smuzhiyun ice->playback_con_substream = substream;
1208*4882a593Smuzhiyun if (ice->force_pdma4) {
1209*4882a593Smuzhiyun runtime->hw = snd_vt1724_2ch_stereo;
1210*4882a593Smuzhiyun set_rate_constraints(ice, substream);
1211*4882a593Smuzhiyun } else
1212*4882a593Smuzhiyun runtime->hw = snd_vt1724_spdif;
1213*4882a593Smuzhiyun snd_pcm_set_sync(substream);
1214*4882a593Smuzhiyun snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1215*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1216*4882a593Smuzhiyun VT1724_BUFFER_ALIGN);
1217*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1218*4882a593Smuzhiyun VT1724_BUFFER_ALIGN);
1219*4882a593Smuzhiyun constrain_rate_if_locked(substream);
1220*4882a593Smuzhiyun if (ice->spdif.ops.open)
1221*4882a593Smuzhiyun ice->spdif.ops.open(ice, substream);
1222*4882a593Smuzhiyun return 0;
1223*4882a593Smuzhiyun }
1224*4882a593Smuzhiyun
snd_vt1724_playback_spdif_close(struct snd_pcm_substream * substream)1225*4882a593Smuzhiyun static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
1226*4882a593Smuzhiyun {
1227*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1228*4882a593Smuzhiyun
1229*4882a593Smuzhiyun if (PRO_RATE_RESET)
1230*4882a593Smuzhiyun snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1231*4882a593Smuzhiyun ice->playback_con_substream = NULL;
1232*4882a593Smuzhiyun if (ice->spdif.ops.close)
1233*4882a593Smuzhiyun ice->spdif.ops.close(ice, substream);
1234*4882a593Smuzhiyun
1235*4882a593Smuzhiyun return 0;
1236*4882a593Smuzhiyun }
1237*4882a593Smuzhiyun
snd_vt1724_capture_spdif_open(struct snd_pcm_substream * substream)1238*4882a593Smuzhiyun static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)
1239*4882a593Smuzhiyun {
1240*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1241*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun runtime->private_data = (void *)&vt1724_capture_spdif_reg;
1244*4882a593Smuzhiyun ice->capture_con_substream = substream;
1245*4882a593Smuzhiyun if (ice->force_rdma1) {
1246*4882a593Smuzhiyun runtime->hw = snd_vt1724_2ch_stereo;
1247*4882a593Smuzhiyun set_rate_constraints(ice, substream);
1248*4882a593Smuzhiyun } else
1249*4882a593Smuzhiyun runtime->hw = snd_vt1724_spdif;
1250*4882a593Smuzhiyun snd_pcm_set_sync(substream);
1251*4882a593Smuzhiyun snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1252*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1253*4882a593Smuzhiyun VT1724_BUFFER_ALIGN);
1254*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1255*4882a593Smuzhiyun VT1724_BUFFER_ALIGN);
1256*4882a593Smuzhiyun constrain_rate_if_locked(substream);
1257*4882a593Smuzhiyun if (ice->spdif.ops.open)
1258*4882a593Smuzhiyun ice->spdif.ops.open(ice, substream);
1259*4882a593Smuzhiyun return 0;
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun
snd_vt1724_capture_spdif_close(struct snd_pcm_substream * substream)1262*4882a593Smuzhiyun static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
1263*4882a593Smuzhiyun {
1264*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun if (PRO_RATE_RESET)
1267*4882a593Smuzhiyun snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1268*4882a593Smuzhiyun ice->capture_con_substream = NULL;
1269*4882a593Smuzhiyun if (ice->spdif.ops.close)
1270*4882a593Smuzhiyun ice->spdif.ops.close(ice, substream);
1271*4882a593Smuzhiyun
1272*4882a593Smuzhiyun return 0;
1273*4882a593Smuzhiyun }
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun static const struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {
1276*4882a593Smuzhiyun .open = snd_vt1724_playback_spdif_open,
1277*4882a593Smuzhiyun .close = snd_vt1724_playback_spdif_close,
1278*4882a593Smuzhiyun .hw_params = snd_vt1724_pcm_hw_params,
1279*4882a593Smuzhiyun .hw_free = snd_vt1724_pcm_hw_free,
1280*4882a593Smuzhiyun .prepare = snd_vt1724_playback_spdif_prepare,
1281*4882a593Smuzhiyun .trigger = snd_vt1724_pcm_trigger,
1282*4882a593Smuzhiyun .pointer = snd_vt1724_pcm_pointer,
1283*4882a593Smuzhiyun };
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun static const struct snd_pcm_ops snd_vt1724_capture_spdif_ops = {
1286*4882a593Smuzhiyun .open = snd_vt1724_capture_spdif_open,
1287*4882a593Smuzhiyun .close = snd_vt1724_capture_spdif_close,
1288*4882a593Smuzhiyun .hw_params = snd_vt1724_pcm_hw_params,
1289*4882a593Smuzhiyun .hw_free = snd_vt1724_pcm_hw_free,
1290*4882a593Smuzhiyun .prepare = snd_vt1724_pcm_prepare,
1291*4882a593Smuzhiyun .trigger = snd_vt1724_pcm_trigger,
1292*4882a593Smuzhiyun .pointer = snd_vt1724_pcm_pointer,
1293*4882a593Smuzhiyun };
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun
snd_vt1724_pcm_spdif(struct snd_ice1712 * ice,int device)1296*4882a593Smuzhiyun static int snd_vt1724_pcm_spdif(struct snd_ice1712 *ice, int device)
1297*4882a593Smuzhiyun {
1298*4882a593Smuzhiyun char *name;
1299*4882a593Smuzhiyun struct snd_pcm *pcm;
1300*4882a593Smuzhiyun int play, capt;
1301*4882a593Smuzhiyun int err;
1302*4882a593Smuzhiyun
1303*4882a593Smuzhiyun if (ice->force_pdma4 ||
1304*4882a593Smuzhiyun (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_OUT_INT)) {
1305*4882a593Smuzhiyun play = 1;
1306*4882a593Smuzhiyun ice->has_spdif = 1;
1307*4882a593Smuzhiyun } else
1308*4882a593Smuzhiyun play = 0;
1309*4882a593Smuzhiyun if (ice->force_rdma1 ||
1310*4882a593Smuzhiyun (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN)) {
1311*4882a593Smuzhiyun capt = 1;
1312*4882a593Smuzhiyun ice->has_spdif = 1;
1313*4882a593Smuzhiyun } else
1314*4882a593Smuzhiyun capt = 0;
1315*4882a593Smuzhiyun if (!play && !capt)
1316*4882a593Smuzhiyun return 0; /* no spdif device */
1317*4882a593Smuzhiyun
1318*4882a593Smuzhiyun if (ice->force_pdma4 || ice->force_rdma1)
1319*4882a593Smuzhiyun name = "ICE1724 Secondary";
1320*4882a593Smuzhiyun else
1321*4882a593Smuzhiyun name = "ICE1724 IEC958";
1322*4882a593Smuzhiyun err = snd_pcm_new(ice->card, name, device, play, capt, &pcm);
1323*4882a593Smuzhiyun if (err < 0)
1324*4882a593Smuzhiyun return err;
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun if (play)
1327*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1328*4882a593Smuzhiyun &snd_vt1724_playback_spdif_ops);
1329*4882a593Smuzhiyun if (capt)
1330*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1331*4882a593Smuzhiyun &snd_vt1724_capture_spdif_ops);
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun pcm->private_data = ice;
1334*4882a593Smuzhiyun pcm->info_flags = 0;
1335*4882a593Smuzhiyun strcpy(pcm->name, name);
1336*4882a593Smuzhiyun
1337*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1338*4882a593Smuzhiyun &ice->pci->dev, 256*1024, 256*1024);
1339*4882a593Smuzhiyun
1340*4882a593Smuzhiyun ice->pcm = pcm;
1341*4882a593Smuzhiyun
1342*4882a593Smuzhiyun return 0;
1343*4882a593Smuzhiyun }
1344*4882a593Smuzhiyun
1345*4882a593Smuzhiyun
1346*4882a593Smuzhiyun /*
1347*4882a593Smuzhiyun * independent surround PCMs
1348*4882a593Smuzhiyun */
1349*4882a593Smuzhiyun
1350*4882a593Smuzhiyun static const struct vt1724_pcm_reg vt1724_playback_dma_regs[3] = {
1351*4882a593Smuzhiyun {
1352*4882a593Smuzhiyun .addr = VT1724_MT_PDMA1_ADDR,
1353*4882a593Smuzhiyun .size = VT1724_MT_PDMA1_SIZE,
1354*4882a593Smuzhiyun .count = VT1724_MT_PDMA1_COUNT,
1355*4882a593Smuzhiyun .start = VT1724_PDMA1_START,
1356*4882a593Smuzhiyun },
1357*4882a593Smuzhiyun {
1358*4882a593Smuzhiyun .addr = VT1724_MT_PDMA2_ADDR,
1359*4882a593Smuzhiyun .size = VT1724_MT_PDMA2_SIZE,
1360*4882a593Smuzhiyun .count = VT1724_MT_PDMA2_COUNT,
1361*4882a593Smuzhiyun .start = VT1724_PDMA2_START,
1362*4882a593Smuzhiyun },
1363*4882a593Smuzhiyun {
1364*4882a593Smuzhiyun .addr = VT1724_MT_PDMA3_ADDR,
1365*4882a593Smuzhiyun .size = VT1724_MT_PDMA3_SIZE,
1366*4882a593Smuzhiyun .count = VT1724_MT_PDMA3_COUNT,
1367*4882a593Smuzhiyun .start = VT1724_PDMA3_START,
1368*4882a593Smuzhiyun },
1369*4882a593Smuzhiyun };
1370*4882a593Smuzhiyun
snd_vt1724_playback_indep_prepare(struct snd_pcm_substream * substream)1371*4882a593Smuzhiyun static int snd_vt1724_playback_indep_prepare(struct snd_pcm_substream *substream)
1372*4882a593Smuzhiyun {
1373*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1374*4882a593Smuzhiyun unsigned char val;
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1377*4882a593Smuzhiyun val = 3 - substream->number;
1378*4882a593Smuzhiyun if (inb(ICEMT1724(ice, BURST)) < val)
1379*4882a593Smuzhiyun outb(val, ICEMT1724(ice, BURST));
1380*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1381*4882a593Smuzhiyun return snd_vt1724_pcm_prepare(substream);
1382*4882a593Smuzhiyun }
1383*4882a593Smuzhiyun
snd_vt1724_playback_indep_open(struct snd_pcm_substream * substream)1384*4882a593Smuzhiyun static int snd_vt1724_playback_indep_open(struct snd_pcm_substream *substream)
1385*4882a593Smuzhiyun {
1386*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1387*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun mutex_lock(&ice->open_mutex);
1390*4882a593Smuzhiyun /* already used by PDMA0? */
1391*4882a593Smuzhiyun if (ice->pcm_reserved[substream->number]) {
1392*4882a593Smuzhiyun mutex_unlock(&ice->open_mutex);
1393*4882a593Smuzhiyun return -EBUSY; /* FIXME: should handle blocking mode properly */
1394*4882a593Smuzhiyun }
1395*4882a593Smuzhiyun mutex_unlock(&ice->open_mutex);
1396*4882a593Smuzhiyun runtime->private_data = (void *)&vt1724_playback_dma_regs[substream->number];
1397*4882a593Smuzhiyun ice->playback_con_substream_ds[substream->number] = substream;
1398*4882a593Smuzhiyun runtime->hw = snd_vt1724_2ch_stereo;
1399*4882a593Smuzhiyun snd_pcm_set_sync(substream);
1400*4882a593Smuzhiyun snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1401*4882a593Smuzhiyun set_rate_constraints(ice, substream);
1402*4882a593Smuzhiyun return 0;
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun
snd_vt1724_playback_indep_close(struct snd_pcm_substream * substream)1405*4882a593Smuzhiyun static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
1406*4882a593Smuzhiyun {
1407*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1408*4882a593Smuzhiyun
1409*4882a593Smuzhiyun if (PRO_RATE_RESET)
1410*4882a593Smuzhiyun snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1411*4882a593Smuzhiyun ice->playback_con_substream_ds[substream->number] = NULL;
1412*4882a593Smuzhiyun ice->pcm_reserved[substream->number] = NULL;
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun return 0;
1415*4882a593Smuzhiyun }
1416*4882a593Smuzhiyun
1417*4882a593Smuzhiyun static const struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
1418*4882a593Smuzhiyun .open = snd_vt1724_playback_indep_open,
1419*4882a593Smuzhiyun .close = snd_vt1724_playback_indep_close,
1420*4882a593Smuzhiyun .hw_params = snd_vt1724_pcm_hw_params,
1421*4882a593Smuzhiyun .hw_free = snd_vt1724_pcm_hw_free,
1422*4882a593Smuzhiyun .prepare = snd_vt1724_playback_indep_prepare,
1423*4882a593Smuzhiyun .trigger = snd_vt1724_pcm_trigger,
1424*4882a593Smuzhiyun .pointer = snd_vt1724_pcm_pointer,
1425*4882a593Smuzhiyun };
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun
snd_vt1724_pcm_indep(struct snd_ice1712 * ice,int device)1428*4882a593Smuzhiyun static int snd_vt1724_pcm_indep(struct snd_ice1712 *ice, int device)
1429*4882a593Smuzhiyun {
1430*4882a593Smuzhiyun struct snd_pcm *pcm;
1431*4882a593Smuzhiyun int play;
1432*4882a593Smuzhiyun int err;
1433*4882a593Smuzhiyun
1434*4882a593Smuzhiyun play = ice->num_total_dacs / 2 - 1;
1435*4882a593Smuzhiyun if (play <= 0)
1436*4882a593Smuzhiyun return 0;
1437*4882a593Smuzhiyun
1438*4882a593Smuzhiyun err = snd_pcm_new(ice->card, "ICE1724 Surrounds", device, play, 0, &pcm);
1439*4882a593Smuzhiyun if (err < 0)
1440*4882a593Smuzhiyun return err;
1441*4882a593Smuzhiyun
1442*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1443*4882a593Smuzhiyun &snd_vt1724_playback_indep_ops);
1444*4882a593Smuzhiyun
1445*4882a593Smuzhiyun pcm->private_data = ice;
1446*4882a593Smuzhiyun pcm->info_flags = 0;
1447*4882a593Smuzhiyun strcpy(pcm->name, "ICE1724 Surround PCM");
1448*4882a593Smuzhiyun
1449*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1450*4882a593Smuzhiyun &ice->pci->dev, 256*1024, 256*1024);
1451*4882a593Smuzhiyun
1452*4882a593Smuzhiyun ice->pcm_ds = pcm;
1453*4882a593Smuzhiyun
1454*4882a593Smuzhiyun return 0;
1455*4882a593Smuzhiyun }
1456*4882a593Smuzhiyun
1457*4882a593Smuzhiyun
1458*4882a593Smuzhiyun /*
1459*4882a593Smuzhiyun * Mixer section
1460*4882a593Smuzhiyun */
1461*4882a593Smuzhiyun
snd_vt1724_ac97_mixer(struct snd_ice1712 * ice)1462*4882a593Smuzhiyun static int snd_vt1724_ac97_mixer(struct snd_ice1712 *ice)
1463*4882a593Smuzhiyun {
1464*4882a593Smuzhiyun int err;
1465*4882a593Smuzhiyun
1466*4882a593Smuzhiyun if (!(ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S)) {
1467*4882a593Smuzhiyun struct snd_ac97_bus *pbus;
1468*4882a593Smuzhiyun struct snd_ac97_template ac97;
1469*4882a593Smuzhiyun static const struct snd_ac97_bus_ops ops = {
1470*4882a593Smuzhiyun .write = snd_vt1724_ac97_write,
1471*4882a593Smuzhiyun .read = snd_vt1724_ac97_read,
1472*4882a593Smuzhiyun };
1473*4882a593Smuzhiyun
1474*4882a593Smuzhiyun /* cold reset */
1475*4882a593Smuzhiyun outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
1476*4882a593Smuzhiyun mdelay(5); /* FIXME */
1477*4882a593Smuzhiyun outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
1478*4882a593Smuzhiyun
1479*4882a593Smuzhiyun err = snd_ac97_bus(ice->card, 0, &ops, NULL, &pbus);
1480*4882a593Smuzhiyun if (err < 0)
1481*4882a593Smuzhiyun return err;
1482*4882a593Smuzhiyun memset(&ac97, 0, sizeof(ac97));
1483*4882a593Smuzhiyun ac97.private_data = ice;
1484*4882a593Smuzhiyun err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
1485*4882a593Smuzhiyun if (err < 0)
1486*4882a593Smuzhiyun dev_warn(ice->card->dev,
1487*4882a593Smuzhiyun "cannot initialize pro ac97, skipped\n");
1488*4882a593Smuzhiyun else
1489*4882a593Smuzhiyun return 0;
1490*4882a593Smuzhiyun }
1491*4882a593Smuzhiyun /* I2S mixer only */
1492*4882a593Smuzhiyun strcat(ice->card->mixername, "ICE1724 - multitrack");
1493*4882a593Smuzhiyun return 0;
1494*4882a593Smuzhiyun }
1495*4882a593Smuzhiyun
1496*4882a593Smuzhiyun /*
1497*4882a593Smuzhiyun *
1498*4882a593Smuzhiyun */
1499*4882a593Smuzhiyun
eeprom_triple(struct snd_ice1712 * ice,int idx)1500*4882a593Smuzhiyun static inline unsigned int eeprom_triple(struct snd_ice1712 *ice, int idx)
1501*4882a593Smuzhiyun {
1502*4882a593Smuzhiyun return (unsigned int)ice->eeprom.data[idx] | \
1503*4882a593Smuzhiyun ((unsigned int)ice->eeprom.data[idx + 1] << 8) | \
1504*4882a593Smuzhiyun ((unsigned int)ice->eeprom.data[idx + 2] << 16);
1505*4882a593Smuzhiyun }
1506*4882a593Smuzhiyun
snd_vt1724_proc_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1507*4882a593Smuzhiyun static void snd_vt1724_proc_read(struct snd_info_entry *entry,
1508*4882a593Smuzhiyun struct snd_info_buffer *buffer)
1509*4882a593Smuzhiyun {
1510*4882a593Smuzhiyun struct snd_ice1712 *ice = entry->private_data;
1511*4882a593Smuzhiyun unsigned int idx;
1512*4882a593Smuzhiyun
1513*4882a593Smuzhiyun snd_iprintf(buffer, "%s\n\n", ice->card->longname);
1514*4882a593Smuzhiyun snd_iprintf(buffer, "EEPROM:\n");
1515*4882a593Smuzhiyun
1516*4882a593Smuzhiyun snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
1517*4882a593Smuzhiyun snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
1518*4882a593Smuzhiyun snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
1519*4882a593Smuzhiyun snd_iprintf(buffer, " System Config : 0x%x\n",
1520*4882a593Smuzhiyun ice->eeprom.data[ICE_EEP2_SYSCONF]);
1521*4882a593Smuzhiyun snd_iprintf(buffer, " ACLink : 0x%x\n",
1522*4882a593Smuzhiyun ice->eeprom.data[ICE_EEP2_ACLINK]);
1523*4882a593Smuzhiyun snd_iprintf(buffer, " I2S : 0x%x\n",
1524*4882a593Smuzhiyun ice->eeprom.data[ICE_EEP2_I2S]);
1525*4882a593Smuzhiyun snd_iprintf(buffer, " S/PDIF : 0x%x\n",
1526*4882a593Smuzhiyun ice->eeprom.data[ICE_EEP2_SPDIF]);
1527*4882a593Smuzhiyun snd_iprintf(buffer, " GPIO direction : 0x%x\n",
1528*4882a593Smuzhiyun ice->eeprom.gpiodir);
1529*4882a593Smuzhiyun snd_iprintf(buffer, " GPIO mask : 0x%x\n",
1530*4882a593Smuzhiyun ice->eeprom.gpiomask);
1531*4882a593Smuzhiyun snd_iprintf(buffer, " GPIO state : 0x%x\n",
1532*4882a593Smuzhiyun ice->eeprom.gpiostate);
1533*4882a593Smuzhiyun for (idx = 0x12; idx < ice->eeprom.size; idx++)
1534*4882a593Smuzhiyun snd_iprintf(buffer, " Extra #%02i : 0x%x\n",
1535*4882a593Smuzhiyun idx, ice->eeprom.data[idx]);
1536*4882a593Smuzhiyun
1537*4882a593Smuzhiyun snd_iprintf(buffer, "\nRegisters:\n");
1538*4882a593Smuzhiyun
1539*4882a593Smuzhiyun snd_iprintf(buffer, " PSDOUT03 : 0x%08x\n",
1540*4882a593Smuzhiyun (unsigned)inl(ICEMT1724(ice, ROUTE_PLAYBACK)));
1541*4882a593Smuzhiyun for (idx = 0x0; idx < 0x20 ; idx++)
1542*4882a593Smuzhiyun snd_iprintf(buffer, " CCS%02x : 0x%02x\n",
1543*4882a593Smuzhiyun idx, inb(ice->port+idx));
1544*4882a593Smuzhiyun for (idx = 0x0; idx < 0x30 ; idx++)
1545*4882a593Smuzhiyun snd_iprintf(buffer, " MT%02x : 0x%02x\n",
1546*4882a593Smuzhiyun idx, inb(ice->profi_port+idx));
1547*4882a593Smuzhiyun }
1548*4882a593Smuzhiyun
snd_vt1724_proc_init(struct snd_ice1712 * ice)1549*4882a593Smuzhiyun static void snd_vt1724_proc_init(struct snd_ice1712 *ice)
1550*4882a593Smuzhiyun {
1551*4882a593Smuzhiyun snd_card_ro_proc_new(ice->card, "ice1724", ice, snd_vt1724_proc_read);
1552*4882a593Smuzhiyun }
1553*4882a593Smuzhiyun
1554*4882a593Smuzhiyun /*
1555*4882a593Smuzhiyun *
1556*4882a593Smuzhiyun */
1557*4882a593Smuzhiyun
snd_vt1724_eeprom_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1558*4882a593Smuzhiyun static int snd_vt1724_eeprom_info(struct snd_kcontrol *kcontrol,
1559*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1560*4882a593Smuzhiyun {
1561*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1562*4882a593Smuzhiyun uinfo->count = sizeof(struct snd_ice1712_eeprom);
1563*4882a593Smuzhiyun return 0;
1564*4882a593Smuzhiyun }
1565*4882a593Smuzhiyun
snd_vt1724_eeprom_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1566*4882a593Smuzhiyun static int snd_vt1724_eeprom_get(struct snd_kcontrol *kcontrol,
1567*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1568*4882a593Smuzhiyun {
1569*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1570*4882a593Smuzhiyun
1571*4882a593Smuzhiyun memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
1572*4882a593Smuzhiyun return 0;
1573*4882a593Smuzhiyun }
1574*4882a593Smuzhiyun
1575*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_eeprom = {
1576*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_CARD,
1577*4882a593Smuzhiyun .name = "ICE1724 EEPROM",
1578*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ,
1579*4882a593Smuzhiyun .info = snd_vt1724_eeprom_info,
1580*4882a593Smuzhiyun .get = snd_vt1724_eeprom_get
1581*4882a593Smuzhiyun };
1582*4882a593Smuzhiyun
1583*4882a593Smuzhiyun /*
1584*4882a593Smuzhiyun */
snd_vt1724_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1585*4882a593Smuzhiyun static int snd_vt1724_spdif_info(struct snd_kcontrol *kcontrol,
1586*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1587*4882a593Smuzhiyun {
1588*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1589*4882a593Smuzhiyun uinfo->count = 1;
1590*4882a593Smuzhiyun return 0;
1591*4882a593Smuzhiyun }
1592*4882a593Smuzhiyun
encode_spdif_bits(struct snd_aes_iec958 * diga)1593*4882a593Smuzhiyun static unsigned int encode_spdif_bits(struct snd_aes_iec958 *diga)
1594*4882a593Smuzhiyun {
1595*4882a593Smuzhiyun unsigned int val, rbits;
1596*4882a593Smuzhiyun
1597*4882a593Smuzhiyun val = diga->status[0] & 0x03; /* professional, non-audio */
1598*4882a593Smuzhiyun if (val & 0x01) {
1599*4882a593Smuzhiyun /* professional */
1600*4882a593Smuzhiyun if ((diga->status[0] & IEC958_AES0_PRO_EMPHASIS) ==
1601*4882a593Smuzhiyun IEC958_AES0_PRO_EMPHASIS_5015)
1602*4882a593Smuzhiyun val |= 1U << 3;
1603*4882a593Smuzhiyun rbits = (diga->status[4] >> 3) & 0x0f;
1604*4882a593Smuzhiyun if (rbits) {
1605*4882a593Smuzhiyun switch (rbits) {
1606*4882a593Smuzhiyun case 2: val |= 5 << 12; break; /* 96k */
1607*4882a593Smuzhiyun case 3: val |= 6 << 12; break; /* 192k */
1608*4882a593Smuzhiyun case 10: val |= 4 << 12; break; /* 88.2k */
1609*4882a593Smuzhiyun case 11: val |= 7 << 12; break; /* 176.4k */
1610*4882a593Smuzhiyun }
1611*4882a593Smuzhiyun } else {
1612*4882a593Smuzhiyun switch (diga->status[0] & IEC958_AES0_PRO_FS) {
1613*4882a593Smuzhiyun case IEC958_AES0_PRO_FS_44100:
1614*4882a593Smuzhiyun break;
1615*4882a593Smuzhiyun case IEC958_AES0_PRO_FS_32000:
1616*4882a593Smuzhiyun val |= 3U << 12;
1617*4882a593Smuzhiyun break;
1618*4882a593Smuzhiyun default:
1619*4882a593Smuzhiyun val |= 2U << 12;
1620*4882a593Smuzhiyun break;
1621*4882a593Smuzhiyun }
1622*4882a593Smuzhiyun }
1623*4882a593Smuzhiyun } else {
1624*4882a593Smuzhiyun /* consumer */
1625*4882a593Smuzhiyun val |= diga->status[1] & 0x04; /* copyright */
1626*4882a593Smuzhiyun if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) ==
1627*4882a593Smuzhiyun IEC958_AES0_CON_EMPHASIS_5015)
1628*4882a593Smuzhiyun val |= 1U << 3;
1629*4882a593Smuzhiyun val |= (unsigned int)(diga->status[1] & 0x3f) << 4; /* category */
1630*4882a593Smuzhiyun val |= (unsigned int)(diga->status[3] & IEC958_AES3_CON_FS) << 12; /* fs */
1631*4882a593Smuzhiyun }
1632*4882a593Smuzhiyun return val;
1633*4882a593Smuzhiyun }
1634*4882a593Smuzhiyun
decode_spdif_bits(struct snd_aes_iec958 * diga,unsigned int val)1635*4882a593Smuzhiyun static void decode_spdif_bits(struct snd_aes_iec958 *diga, unsigned int val)
1636*4882a593Smuzhiyun {
1637*4882a593Smuzhiyun memset(diga->status, 0, sizeof(diga->status));
1638*4882a593Smuzhiyun diga->status[0] = val & 0x03; /* professional, non-audio */
1639*4882a593Smuzhiyun if (val & 0x01) {
1640*4882a593Smuzhiyun /* professional */
1641*4882a593Smuzhiyun if (val & (1U << 3))
1642*4882a593Smuzhiyun diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015;
1643*4882a593Smuzhiyun switch ((val >> 12) & 0x7) {
1644*4882a593Smuzhiyun case 0:
1645*4882a593Smuzhiyun break;
1646*4882a593Smuzhiyun case 2:
1647*4882a593Smuzhiyun diga->status[0] |= IEC958_AES0_PRO_FS_32000;
1648*4882a593Smuzhiyun break;
1649*4882a593Smuzhiyun default:
1650*4882a593Smuzhiyun diga->status[0] |= IEC958_AES0_PRO_FS_48000;
1651*4882a593Smuzhiyun break;
1652*4882a593Smuzhiyun }
1653*4882a593Smuzhiyun } else {
1654*4882a593Smuzhiyun /* consumer */
1655*4882a593Smuzhiyun diga->status[0] |= val & (1U << 2); /* copyright */
1656*4882a593Smuzhiyun if (val & (1U << 3))
1657*4882a593Smuzhiyun diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
1658*4882a593Smuzhiyun diga->status[1] |= (val >> 4) & 0x3f; /* category */
1659*4882a593Smuzhiyun diga->status[3] |= (val >> 12) & 0x07; /* fs */
1660*4882a593Smuzhiyun }
1661*4882a593Smuzhiyun }
1662*4882a593Smuzhiyun
snd_vt1724_spdif_default_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1663*4882a593Smuzhiyun static int snd_vt1724_spdif_default_get(struct snd_kcontrol *kcontrol,
1664*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1665*4882a593Smuzhiyun {
1666*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1667*4882a593Smuzhiyun unsigned int val;
1668*4882a593Smuzhiyun val = inw(ICEMT1724(ice, SPDIF_CTRL));
1669*4882a593Smuzhiyun decode_spdif_bits(&ucontrol->value.iec958, val);
1670*4882a593Smuzhiyun return 0;
1671*4882a593Smuzhiyun }
1672*4882a593Smuzhiyun
snd_vt1724_spdif_default_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1673*4882a593Smuzhiyun static int snd_vt1724_spdif_default_put(struct snd_kcontrol *kcontrol,
1674*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1675*4882a593Smuzhiyun {
1676*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1677*4882a593Smuzhiyun unsigned int val, old;
1678*4882a593Smuzhiyun
1679*4882a593Smuzhiyun val = encode_spdif_bits(&ucontrol->value.iec958);
1680*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1681*4882a593Smuzhiyun old = inw(ICEMT1724(ice, SPDIF_CTRL));
1682*4882a593Smuzhiyun if (val != old)
1683*4882a593Smuzhiyun update_spdif_bits(ice, val);
1684*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1685*4882a593Smuzhiyun return val != old;
1686*4882a593Smuzhiyun }
1687*4882a593Smuzhiyun
1688*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_spdif_default =
1689*4882a593Smuzhiyun {
1690*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1691*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1692*4882a593Smuzhiyun .info = snd_vt1724_spdif_info,
1693*4882a593Smuzhiyun .get = snd_vt1724_spdif_default_get,
1694*4882a593Smuzhiyun .put = snd_vt1724_spdif_default_put
1695*4882a593Smuzhiyun };
1696*4882a593Smuzhiyun
snd_vt1724_spdif_maskc_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1697*4882a593Smuzhiyun static int snd_vt1724_spdif_maskc_get(struct snd_kcontrol *kcontrol,
1698*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1699*4882a593Smuzhiyun {
1700*4882a593Smuzhiyun ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1701*4882a593Smuzhiyun IEC958_AES0_PROFESSIONAL |
1702*4882a593Smuzhiyun IEC958_AES0_CON_NOT_COPYRIGHT |
1703*4882a593Smuzhiyun IEC958_AES0_CON_EMPHASIS;
1704*4882a593Smuzhiyun ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
1705*4882a593Smuzhiyun IEC958_AES1_CON_CATEGORY;
1706*4882a593Smuzhiyun ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
1707*4882a593Smuzhiyun return 0;
1708*4882a593Smuzhiyun }
1709*4882a593Smuzhiyun
snd_vt1724_spdif_maskp_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1710*4882a593Smuzhiyun static int snd_vt1724_spdif_maskp_get(struct snd_kcontrol *kcontrol,
1711*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1712*4882a593Smuzhiyun {
1713*4882a593Smuzhiyun ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1714*4882a593Smuzhiyun IEC958_AES0_PROFESSIONAL |
1715*4882a593Smuzhiyun IEC958_AES0_PRO_FS |
1716*4882a593Smuzhiyun IEC958_AES0_PRO_EMPHASIS;
1717*4882a593Smuzhiyun return 0;
1718*4882a593Smuzhiyun }
1719*4882a593Smuzhiyun
1720*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_spdif_maskc =
1721*4882a593Smuzhiyun {
1722*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ,
1723*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1724*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1725*4882a593Smuzhiyun .info = snd_vt1724_spdif_info,
1726*4882a593Smuzhiyun .get = snd_vt1724_spdif_maskc_get,
1727*4882a593Smuzhiyun };
1728*4882a593Smuzhiyun
1729*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_spdif_maskp =
1730*4882a593Smuzhiyun {
1731*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ,
1732*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1733*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1734*4882a593Smuzhiyun .info = snd_vt1724_spdif_info,
1735*4882a593Smuzhiyun .get = snd_vt1724_spdif_maskp_get,
1736*4882a593Smuzhiyun };
1737*4882a593Smuzhiyun
1738*4882a593Smuzhiyun #define snd_vt1724_spdif_sw_info snd_ctl_boolean_mono_info
1739*4882a593Smuzhiyun
snd_vt1724_spdif_sw_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1740*4882a593Smuzhiyun static int snd_vt1724_spdif_sw_get(struct snd_kcontrol *kcontrol,
1741*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1742*4882a593Smuzhiyun {
1743*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1744*4882a593Smuzhiyun ucontrol->value.integer.value[0] = inb(ICEREG1724(ice, SPDIF_CFG)) &
1745*4882a593Smuzhiyun VT1724_CFG_SPDIF_OUT_EN ? 1 : 0;
1746*4882a593Smuzhiyun return 0;
1747*4882a593Smuzhiyun }
1748*4882a593Smuzhiyun
snd_vt1724_spdif_sw_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1749*4882a593Smuzhiyun static int snd_vt1724_spdif_sw_put(struct snd_kcontrol *kcontrol,
1750*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1751*4882a593Smuzhiyun {
1752*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1753*4882a593Smuzhiyun unsigned char old, val;
1754*4882a593Smuzhiyun
1755*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1756*4882a593Smuzhiyun old = val = inb(ICEREG1724(ice, SPDIF_CFG));
1757*4882a593Smuzhiyun val &= ~VT1724_CFG_SPDIF_OUT_EN;
1758*4882a593Smuzhiyun if (ucontrol->value.integer.value[0])
1759*4882a593Smuzhiyun val |= VT1724_CFG_SPDIF_OUT_EN;
1760*4882a593Smuzhiyun if (old != val)
1761*4882a593Smuzhiyun outb(val, ICEREG1724(ice, SPDIF_CFG));
1762*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1763*4882a593Smuzhiyun return old != val;
1764*4882a593Smuzhiyun }
1765*4882a593Smuzhiyun
1766*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_spdif_switch =
1767*4882a593Smuzhiyun {
1768*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1769*4882a593Smuzhiyun /* FIXME: the following conflict with IEC958 Playback Route */
1770*4882a593Smuzhiyun /* .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), */
1771*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("Output ", NONE, SWITCH),
1772*4882a593Smuzhiyun .info = snd_vt1724_spdif_sw_info,
1773*4882a593Smuzhiyun .get = snd_vt1724_spdif_sw_get,
1774*4882a593Smuzhiyun .put = snd_vt1724_spdif_sw_put
1775*4882a593Smuzhiyun };
1776*4882a593Smuzhiyun
1777*4882a593Smuzhiyun
1778*4882a593Smuzhiyun #if 0 /* NOT USED YET */
1779*4882a593Smuzhiyun /*
1780*4882a593Smuzhiyun * GPIO access from extern
1781*4882a593Smuzhiyun */
1782*4882a593Smuzhiyun
1783*4882a593Smuzhiyun #define snd_vt1724_gpio_info snd_ctl_boolean_mono_info
1784*4882a593Smuzhiyun
1785*4882a593Smuzhiyun int snd_vt1724_gpio_get(struct snd_kcontrol *kcontrol,
1786*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1787*4882a593Smuzhiyun {
1788*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1789*4882a593Smuzhiyun int shift = kcontrol->private_value & 0xff;
1790*4882a593Smuzhiyun int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
1791*4882a593Smuzhiyun
1792*4882a593Smuzhiyun snd_ice1712_save_gpio_status(ice);
1793*4882a593Smuzhiyun ucontrol->value.integer.value[0] =
1794*4882a593Smuzhiyun (snd_ice1712_gpio_read(ice) & (1 << shift) ? 1 : 0) ^ invert;
1795*4882a593Smuzhiyun snd_ice1712_restore_gpio_status(ice);
1796*4882a593Smuzhiyun return 0;
1797*4882a593Smuzhiyun }
1798*4882a593Smuzhiyun
1799*4882a593Smuzhiyun int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
1800*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1801*4882a593Smuzhiyun {
1802*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1803*4882a593Smuzhiyun int shift = kcontrol->private_value & 0xff;
1804*4882a593Smuzhiyun int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
1805*4882a593Smuzhiyun unsigned int val, nval;
1806*4882a593Smuzhiyun
1807*4882a593Smuzhiyun if (kcontrol->private_value & (1 << 31))
1808*4882a593Smuzhiyun return -EPERM;
1809*4882a593Smuzhiyun nval = (ucontrol->value.integer.value[0] ? (1 << shift) : 0) ^ invert;
1810*4882a593Smuzhiyun snd_ice1712_save_gpio_status(ice);
1811*4882a593Smuzhiyun val = snd_ice1712_gpio_read(ice);
1812*4882a593Smuzhiyun nval |= val & ~(1 << shift);
1813*4882a593Smuzhiyun if (val != nval)
1814*4882a593Smuzhiyun snd_ice1712_gpio_write(ice, nval);
1815*4882a593Smuzhiyun snd_ice1712_restore_gpio_status(ice);
1816*4882a593Smuzhiyun return val != nval;
1817*4882a593Smuzhiyun }
1818*4882a593Smuzhiyun #endif /* NOT USED YET */
1819*4882a593Smuzhiyun
1820*4882a593Smuzhiyun /*
1821*4882a593Smuzhiyun * rate
1822*4882a593Smuzhiyun */
snd_vt1724_pro_internal_clock_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1823*4882a593Smuzhiyun static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
1824*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1825*4882a593Smuzhiyun {
1826*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1827*4882a593Smuzhiyun int hw_rates_count = ice->hw_rates->count;
1828*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1829*4882a593Smuzhiyun uinfo->count = 1;
1830*4882a593Smuzhiyun
1831*4882a593Smuzhiyun /* internal clocks */
1832*4882a593Smuzhiyun uinfo->value.enumerated.items = hw_rates_count;
1833*4882a593Smuzhiyun /* external clocks */
1834*4882a593Smuzhiyun if (ice->force_rdma1 ||
1835*4882a593Smuzhiyun (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN))
1836*4882a593Smuzhiyun uinfo->value.enumerated.items += ice->ext_clock_count;
1837*4882a593Smuzhiyun /* upper limit - keep at top */
1838*4882a593Smuzhiyun if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1839*4882a593Smuzhiyun uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1840*4882a593Smuzhiyun if (uinfo->value.enumerated.item >= hw_rates_count)
1841*4882a593Smuzhiyun /* ext_clock items */
1842*4882a593Smuzhiyun strcpy(uinfo->value.enumerated.name,
1843*4882a593Smuzhiyun ice->ext_clock_names[
1844*4882a593Smuzhiyun uinfo->value.enumerated.item - hw_rates_count]);
1845*4882a593Smuzhiyun else
1846*4882a593Smuzhiyun /* int clock items */
1847*4882a593Smuzhiyun sprintf(uinfo->value.enumerated.name, "%d",
1848*4882a593Smuzhiyun ice->hw_rates->list[uinfo->value.enumerated.item]);
1849*4882a593Smuzhiyun return 0;
1850*4882a593Smuzhiyun }
1851*4882a593Smuzhiyun
snd_vt1724_pro_internal_clock_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1852*4882a593Smuzhiyun static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
1853*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1854*4882a593Smuzhiyun {
1855*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1856*4882a593Smuzhiyun unsigned int i, rate;
1857*4882a593Smuzhiyun
1858*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1859*4882a593Smuzhiyun if (ice->is_spdif_master(ice)) {
1860*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = ice->hw_rates->count +
1861*4882a593Smuzhiyun ice->get_spdif_master_type(ice);
1862*4882a593Smuzhiyun } else {
1863*4882a593Smuzhiyun rate = ice->get_rate(ice);
1864*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = 0;
1865*4882a593Smuzhiyun for (i = 0; i < ice->hw_rates->count; i++) {
1866*4882a593Smuzhiyun if (ice->hw_rates->list[i] == rate) {
1867*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = i;
1868*4882a593Smuzhiyun break;
1869*4882a593Smuzhiyun }
1870*4882a593Smuzhiyun }
1871*4882a593Smuzhiyun }
1872*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1873*4882a593Smuzhiyun return 0;
1874*4882a593Smuzhiyun }
1875*4882a593Smuzhiyun
stdclock_get_spdif_master_type(struct snd_ice1712 * ice)1876*4882a593Smuzhiyun static int stdclock_get_spdif_master_type(struct snd_ice1712 *ice)
1877*4882a593Smuzhiyun {
1878*4882a593Smuzhiyun /* standard external clock - only single type - SPDIF IN */
1879*4882a593Smuzhiyun return 0;
1880*4882a593Smuzhiyun }
1881*4882a593Smuzhiyun
1882*4882a593Smuzhiyun /* setting clock to external - SPDIF */
stdclock_set_spdif_clock(struct snd_ice1712 * ice,int type)1883*4882a593Smuzhiyun static int stdclock_set_spdif_clock(struct snd_ice1712 *ice, int type)
1884*4882a593Smuzhiyun {
1885*4882a593Smuzhiyun unsigned char oval;
1886*4882a593Smuzhiyun unsigned char i2s_oval;
1887*4882a593Smuzhiyun oval = inb(ICEMT1724(ice, RATE));
1888*4882a593Smuzhiyun outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1889*4882a593Smuzhiyun /* setting 256fs */
1890*4882a593Smuzhiyun i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
1891*4882a593Smuzhiyun outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
1892*4882a593Smuzhiyun return 0;
1893*4882a593Smuzhiyun }
1894*4882a593Smuzhiyun
1895*4882a593Smuzhiyun
snd_vt1724_pro_internal_clock_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1896*4882a593Smuzhiyun static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
1897*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1898*4882a593Smuzhiyun {
1899*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1900*4882a593Smuzhiyun unsigned int old_rate, new_rate;
1901*4882a593Smuzhiyun unsigned int item = ucontrol->value.enumerated.item[0];
1902*4882a593Smuzhiyun unsigned int first_ext_clock = ice->hw_rates->count;
1903*4882a593Smuzhiyun
1904*4882a593Smuzhiyun if (item > first_ext_clock + ice->ext_clock_count - 1)
1905*4882a593Smuzhiyun return -EINVAL;
1906*4882a593Smuzhiyun
1907*4882a593Smuzhiyun /* if rate = 0 => external clock */
1908*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1909*4882a593Smuzhiyun if (ice->is_spdif_master(ice))
1910*4882a593Smuzhiyun old_rate = 0;
1911*4882a593Smuzhiyun else
1912*4882a593Smuzhiyun old_rate = ice->get_rate(ice);
1913*4882a593Smuzhiyun if (item >= first_ext_clock) {
1914*4882a593Smuzhiyun /* switching to external clock */
1915*4882a593Smuzhiyun ice->set_spdif_clock(ice, item - first_ext_clock);
1916*4882a593Smuzhiyun new_rate = 0;
1917*4882a593Smuzhiyun } else {
1918*4882a593Smuzhiyun /* internal on-card clock */
1919*4882a593Smuzhiyun new_rate = ice->hw_rates->list[item];
1920*4882a593Smuzhiyun ice->pro_rate_default = new_rate;
1921*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1922*4882a593Smuzhiyun snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
1923*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1924*4882a593Smuzhiyun }
1925*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1926*4882a593Smuzhiyun
1927*4882a593Smuzhiyun /* the first switch to the ext. clock mode? */
1928*4882a593Smuzhiyun if (old_rate != new_rate && !new_rate) {
1929*4882a593Smuzhiyun /* notify akm chips as well */
1930*4882a593Smuzhiyun unsigned int i;
1931*4882a593Smuzhiyun if (ice->gpio.set_pro_rate)
1932*4882a593Smuzhiyun ice->gpio.set_pro_rate(ice, 0);
1933*4882a593Smuzhiyun for (i = 0; i < ice->akm_codecs; i++) {
1934*4882a593Smuzhiyun if (ice->akm[i].ops.set_rate_val)
1935*4882a593Smuzhiyun ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
1936*4882a593Smuzhiyun }
1937*4882a593Smuzhiyun }
1938*4882a593Smuzhiyun return old_rate != new_rate;
1939*4882a593Smuzhiyun }
1940*4882a593Smuzhiyun
1941*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_pro_internal_clock = {
1942*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1943*4882a593Smuzhiyun .name = "Multi Track Internal Clock",
1944*4882a593Smuzhiyun .info = snd_vt1724_pro_internal_clock_info,
1945*4882a593Smuzhiyun .get = snd_vt1724_pro_internal_clock_get,
1946*4882a593Smuzhiyun .put = snd_vt1724_pro_internal_clock_put
1947*4882a593Smuzhiyun };
1948*4882a593Smuzhiyun
1949*4882a593Smuzhiyun #define snd_vt1724_pro_rate_locking_info snd_ctl_boolean_mono_info
1950*4882a593Smuzhiyun
snd_vt1724_pro_rate_locking_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1951*4882a593Smuzhiyun static int snd_vt1724_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
1952*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1953*4882a593Smuzhiyun {
1954*4882a593Smuzhiyun ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
1955*4882a593Smuzhiyun return 0;
1956*4882a593Smuzhiyun }
1957*4882a593Smuzhiyun
snd_vt1724_pro_rate_locking_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1958*4882a593Smuzhiyun static int snd_vt1724_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
1959*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1960*4882a593Smuzhiyun {
1961*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1962*4882a593Smuzhiyun int change = 0, nval;
1963*4882a593Smuzhiyun
1964*4882a593Smuzhiyun nval = ucontrol->value.integer.value[0] ? 1 : 0;
1965*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1966*4882a593Smuzhiyun change = PRO_RATE_LOCKED != nval;
1967*4882a593Smuzhiyun PRO_RATE_LOCKED = nval;
1968*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1969*4882a593Smuzhiyun return change;
1970*4882a593Smuzhiyun }
1971*4882a593Smuzhiyun
1972*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_pro_rate_locking = {
1973*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1974*4882a593Smuzhiyun .name = "Multi Track Rate Locking",
1975*4882a593Smuzhiyun .info = snd_vt1724_pro_rate_locking_info,
1976*4882a593Smuzhiyun .get = snd_vt1724_pro_rate_locking_get,
1977*4882a593Smuzhiyun .put = snd_vt1724_pro_rate_locking_put
1978*4882a593Smuzhiyun };
1979*4882a593Smuzhiyun
1980*4882a593Smuzhiyun #define snd_vt1724_pro_rate_reset_info snd_ctl_boolean_mono_info
1981*4882a593Smuzhiyun
snd_vt1724_pro_rate_reset_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1982*4882a593Smuzhiyun static int snd_vt1724_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
1983*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1984*4882a593Smuzhiyun {
1985*4882a593Smuzhiyun ucontrol->value.integer.value[0] = PRO_RATE_RESET ? 1 : 0;
1986*4882a593Smuzhiyun return 0;
1987*4882a593Smuzhiyun }
1988*4882a593Smuzhiyun
snd_vt1724_pro_rate_reset_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1989*4882a593Smuzhiyun static int snd_vt1724_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
1990*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1991*4882a593Smuzhiyun {
1992*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1993*4882a593Smuzhiyun int change = 0, nval;
1994*4882a593Smuzhiyun
1995*4882a593Smuzhiyun nval = ucontrol->value.integer.value[0] ? 1 : 0;
1996*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1997*4882a593Smuzhiyun change = PRO_RATE_RESET != nval;
1998*4882a593Smuzhiyun PRO_RATE_RESET = nval;
1999*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
2000*4882a593Smuzhiyun return change;
2001*4882a593Smuzhiyun }
2002*4882a593Smuzhiyun
2003*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_pro_rate_reset = {
2004*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2005*4882a593Smuzhiyun .name = "Multi Track Rate Reset",
2006*4882a593Smuzhiyun .info = snd_vt1724_pro_rate_reset_info,
2007*4882a593Smuzhiyun .get = snd_vt1724_pro_rate_reset_get,
2008*4882a593Smuzhiyun .put = snd_vt1724_pro_rate_reset_put
2009*4882a593Smuzhiyun };
2010*4882a593Smuzhiyun
2011*4882a593Smuzhiyun
2012*4882a593Smuzhiyun /*
2013*4882a593Smuzhiyun * routing
2014*4882a593Smuzhiyun */
snd_vt1724_pro_route_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2015*4882a593Smuzhiyun static int snd_vt1724_pro_route_info(struct snd_kcontrol *kcontrol,
2016*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
2017*4882a593Smuzhiyun {
2018*4882a593Smuzhiyun static const char * const texts[] = {
2019*4882a593Smuzhiyun "PCM Out", /* 0 */
2020*4882a593Smuzhiyun "H/W In 0", "H/W In 1", /* 1-2 */
2021*4882a593Smuzhiyun "IEC958 In L", "IEC958 In R", /* 3-4 */
2022*4882a593Smuzhiyun };
2023*4882a593Smuzhiyun
2024*4882a593Smuzhiyun return snd_ctl_enum_info(uinfo, 1, 5, texts);
2025*4882a593Smuzhiyun }
2026*4882a593Smuzhiyun
analog_route_shift(int idx)2027*4882a593Smuzhiyun static inline int analog_route_shift(int idx)
2028*4882a593Smuzhiyun {
2029*4882a593Smuzhiyun return (idx % 2) * 12 + ((idx / 2) * 3) + 8;
2030*4882a593Smuzhiyun }
2031*4882a593Smuzhiyun
digital_route_shift(int idx)2032*4882a593Smuzhiyun static inline int digital_route_shift(int idx)
2033*4882a593Smuzhiyun {
2034*4882a593Smuzhiyun return idx * 3;
2035*4882a593Smuzhiyun }
2036*4882a593Smuzhiyun
snd_ice1724_get_route_val(struct snd_ice1712 * ice,int shift)2037*4882a593Smuzhiyun int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift)
2038*4882a593Smuzhiyun {
2039*4882a593Smuzhiyun unsigned long val;
2040*4882a593Smuzhiyun unsigned char eitem;
2041*4882a593Smuzhiyun static const unsigned char xlate[8] = {
2042*4882a593Smuzhiyun 0, 255, 1, 2, 255, 255, 3, 4,
2043*4882a593Smuzhiyun };
2044*4882a593Smuzhiyun
2045*4882a593Smuzhiyun val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2046*4882a593Smuzhiyun val >>= shift;
2047*4882a593Smuzhiyun val &= 7; /* we now have 3 bits per output */
2048*4882a593Smuzhiyun eitem = xlate[val];
2049*4882a593Smuzhiyun if (eitem == 255) {
2050*4882a593Smuzhiyun snd_BUG();
2051*4882a593Smuzhiyun return 0;
2052*4882a593Smuzhiyun }
2053*4882a593Smuzhiyun return eitem;
2054*4882a593Smuzhiyun }
2055*4882a593Smuzhiyun
snd_ice1724_put_route_val(struct snd_ice1712 * ice,unsigned int val,int shift)2056*4882a593Smuzhiyun int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
2057*4882a593Smuzhiyun int shift)
2058*4882a593Smuzhiyun {
2059*4882a593Smuzhiyun unsigned int old_val, nval;
2060*4882a593Smuzhiyun int change;
2061*4882a593Smuzhiyun static const unsigned char xroute[8] = {
2062*4882a593Smuzhiyun 0, /* PCM */
2063*4882a593Smuzhiyun 2, /* PSDIN0 Left */
2064*4882a593Smuzhiyun 3, /* PSDIN0 Right */
2065*4882a593Smuzhiyun 6, /* SPDIN Left */
2066*4882a593Smuzhiyun 7, /* SPDIN Right */
2067*4882a593Smuzhiyun };
2068*4882a593Smuzhiyun
2069*4882a593Smuzhiyun nval = xroute[val % 5];
2070*4882a593Smuzhiyun val = old_val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2071*4882a593Smuzhiyun val &= ~(0x07 << shift);
2072*4882a593Smuzhiyun val |= nval << shift;
2073*4882a593Smuzhiyun change = val != old_val;
2074*4882a593Smuzhiyun if (change)
2075*4882a593Smuzhiyun outl(val, ICEMT1724(ice, ROUTE_PLAYBACK));
2076*4882a593Smuzhiyun return change;
2077*4882a593Smuzhiyun }
2078*4882a593Smuzhiyun
snd_vt1724_pro_route_analog_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2079*4882a593Smuzhiyun static int snd_vt1724_pro_route_analog_get(struct snd_kcontrol *kcontrol,
2080*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2081*4882a593Smuzhiyun {
2082*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2083*4882a593Smuzhiyun int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2084*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] =
2085*4882a593Smuzhiyun snd_ice1724_get_route_val(ice, analog_route_shift(idx));
2086*4882a593Smuzhiyun return 0;
2087*4882a593Smuzhiyun }
2088*4882a593Smuzhiyun
snd_vt1724_pro_route_analog_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2089*4882a593Smuzhiyun static int snd_vt1724_pro_route_analog_put(struct snd_kcontrol *kcontrol,
2090*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2091*4882a593Smuzhiyun {
2092*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2093*4882a593Smuzhiyun int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2094*4882a593Smuzhiyun return snd_ice1724_put_route_val(ice,
2095*4882a593Smuzhiyun ucontrol->value.enumerated.item[0],
2096*4882a593Smuzhiyun analog_route_shift(idx));
2097*4882a593Smuzhiyun }
2098*4882a593Smuzhiyun
snd_vt1724_pro_route_spdif_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2099*4882a593Smuzhiyun static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
2100*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2101*4882a593Smuzhiyun {
2102*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2103*4882a593Smuzhiyun int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2104*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] =
2105*4882a593Smuzhiyun snd_ice1724_get_route_val(ice, digital_route_shift(idx));
2106*4882a593Smuzhiyun return 0;
2107*4882a593Smuzhiyun }
2108*4882a593Smuzhiyun
snd_vt1724_pro_route_spdif_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2109*4882a593Smuzhiyun static int snd_vt1724_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
2110*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2111*4882a593Smuzhiyun {
2112*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2113*4882a593Smuzhiyun int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2114*4882a593Smuzhiyun return snd_ice1724_put_route_val(ice,
2115*4882a593Smuzhiyun ucontrol->value.enumerated.item[0],
2116*4882a593Smuzhiyun digital_route_shift(idx));
2117*4882a593Smuzhiyun }
2118*4882a593Smuzhiyun
2119*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route =
2120*4882a593Smuzhiyun {
2121*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2122*4882a593Smuzhiyun .name = "H/W Playback Route",
2123*4882a593Smuzhiyun .info = snd_vt1724_pro_route_info,
2124*4882a593Smuzhiyun .get = snd_vt1724_pro_route_analog_get,
2125*4882a593Smuzhiyun .put = snd_vt1724_pro_route_analog_put,
2126*4882a593Smuzhiyun };
2127*4882a593Smuzhiyun
2128*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_mixer_pro_spdif_route = {
2129*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2130*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
2131*4882a593Smuzhiyun .info = snd_vt1724_pro_route_info,
2132*4882a593Smuzhiyun .get = snd_vt1724_pro_route_spdif_get,
2133*4882a593Smuzhiyun .put = snd_vt1724_pro_route_spdif_put,
2134*4882a593Smuzhiyun .count = 2,
2135*4882a593Smuzhiyun };
2136*4882a593Smuzhiyun
2137*4882a593Smuzhiyun
snd_vt1724_pro_peak_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2138*4882a593Smuzhiyun static int snd_vt1724_pro_peak_info(struct snd_kcontrol *kcontrol,
2139*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
2140*4882a593Smuzhiyun {
2141*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2142*4882a593Smuzhiyun uinfo->count = 22; /* FIXME: for compatibility with ice1712... */
2143*4882a593Smuzhiyun uinfo->value.integer.min = 0;
2144*4882a593Smuzhiyun uinfo->value.integer.max = 255;
2145*4882a593Smuzhiyun return 0;
2146*4882a593Smuzhiyun }
2147*4882a593Smuzhiyun
snd_vt1724_pro_peak_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2148*4882a593Smuzhiyun static int snd_vt1724_pro_peak_get(struct snd_kcontrol *kcontrol,
2149*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2150*4882a593Smuzhiyun {
2151*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2152*4882a593Smuzhiyun int idx;
2153*4882a593Smuzhiyun
2154*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
2155*4882a593Smuzhiyun for (idx = 0; idx < 22; idx++) {
2156*4882a593Smuzhiyun outb(idx, ICEMT1724(ice, MONITOR_PEAKINDEX));
2157*4882a593Smuzhiyun ucontrol->value.integer.value[idx] =
2158*4882a593Smuzhiyun inb(ICEMT1724(ice, MONITOR_PEAKDATA));
2159*4882a593Smuzhiyun }
2160*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
2161*4882a593Smuzhiyun return 0;
2162*4882a593Smuzhiyun }
2163*4882a593Smuzhiyun
2164*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_vt1724_mixer_pro_peak = {
2165*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2166*4882a593Smuzhiyun .name = "Multi Track Peak",
2167*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
2168*4882a593Smuzhiyun .info = snd_vt1724_pro_peak_info,
2169*4882a593Smuzhiyun .get = snd_vt1724_pro_peak_get
2170*4882a593Smuzhiyun };
2171*4882a593Smuzhiyun
2172*4882a593Smuzhiyun /*
2173*4882a593Smuzhiyun *
2174*4882a593Smuzhiyun */
2175*4882a593Smuzhiyun
2176*4882a593Smuzhiyun static const struct snd_ice1712_card_info no_matched;
2177*4882a593Smuzhiyun
2178*4882a593Smuzhiyun
2179*4882a593Smuzhiyun /*
2180*4882a593Smuzhiyun ooAoo cards with no controls
2181*4882a593Smuzhiyun */
2182*4882a593Smuzhiyun static const unsigned char ooaoo_sq210_eeprom[] = {
2183*4882a593Smuzhiyun [ICE_EEP2_SYSCONF] = 0x4c, /* 49MHz crystal, no mpu401, no ADC,
2184*4882a593Smuzhiyun 1xDACs */
2185*4882a593Smuzhiyun [ICE_EEP2_ACLINK] = 0x80, /* I2S */
2186*4882a593Smuzhiyun [ICE_EEP2_I2S] = 0x78, /* no volume, 96k, 24bit, 192k */
2187*4882a593Smuzhiyun [ICE_EEP2_SPDIF] = 0xc1, /* out-en, out-int, out-ext */
2188*4882a593Smuzhiyun [ICE_EEP2_GPIO_DIR] = 0x00, /* no GPIOs are used */
2189*4882a593Smuzhiyun [ICE_EEP2_GPIO_DIR1] = 0x00,
2190*4882a593Smuzhiyun [ICE_EEP2_GPIO_DIR2] = 0x00,
2191*4882a593Smuzhiyun [ICE_EEP2_GPIO_MASK] = 0xff,
2192*4882a593Smuzhiyun [ICE_EEP2_GPIO_MASK1] = 0xff,
2193*4882a593Smuzhiyun [ICE_EEP2_GPIO_MASK2] = 0xff,
2194*4882a593Smuzhiyun
2195*4882a593Smuzhiyun [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
2196*4882a593Smuzhiyun [ICE_EEP2_GPIO_STATE1] = 0x00, /* all 1, but GPIO_CPLD_RW
2197*4882a593Smuzhiyun and GPIO15 always zero */
2198*4882a593Smuzhiyun [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
2199*4882a593Smuzhiyun };
2200*4882a593Smuzhiyun
2201*4882a593Smuzhiyun
2202*4882a593Smuzhiyun static const struct snd_ice1712_card_info snd_vt1724_ooaoo_cards[] = {
2203*4882a593Smuzhiyun {
2204*4882a593Smuzhiyun .name = "ooAoo SQ210a",
2205*4882a593Smuzhiyun .model = "sq210a",
2206*4882a593Smuzhiyun .eeprom_size = sizeof(ooaoo_sq210_eeprom),
2207*4882a593Smuzhiyun .eeprom_data = ooaoo_sq210_eeprom,
2208*4882a593Smuzhiyun },
2209*4882a593Smuzhiyun { } /* terminator */
2210*4882a593Smuzhiyun };
2211*4882a593Smuzhiyun
2212*4882a593Smuzhiyun static const struct snd_ice1712_card_info *card_tables[] = {
2213*4882a593Smuzhiyun snd_vt1724_revo_cards,
2214*4882a593Smuzhiyun snd_vt1724_amp_cards,
2215*4882a593Smuzhiyun snd_vt1724_aureon_cards,
2216*4882a593Smuzhiyun snd_vt1720_mobo_cards,
2217*4882a593Smuzhiyun snd_vt1720_pontis_cards,
2218*4882a593Smuzhiyun snd_vt1724_prodigy_hifi_cards,
2219*4882a593Smuzhiyun snd_vt1724_prodigy192_cards,
2220*4882a593Smuzhiyun snd_vt1724_juli_cards,
2221*4882a593Smuzhiyun snd_vt1724_maya44_cards,
2222*4882a593Smuzhiyun snd_vt1724_phase_cards,
2223*4882a593Smuzhiyun snd_vt1724_wtm_cards,
2224*4882a593Smuzhiyun snd_vt1724_se_cards,
2225*4882a593Smuzhiyun snd_vt1724_qtet_cards,
2226*4882a593Smuzhiyun snd_vt1724_ooaoo_cards,
2227*4882a593Smuzhiyun snd_vt1724_psc724_cards,
2228*4882a593Smuzhiyun NULL,
2229*4882a593Smuzhiyun };
2230*4882a593Smuzhiyun
2231*4882a593Smuzhiyun
2232*4882a593Smuzhiyun /*
2233*4882a593Smuzhiyun */
2234*4882a593Smuzhiyun
wait_i2c_busy(struct snd_ice1712 * ice)2235*4882a593Smuzhiyun static void wait_i2c_busy(struct snd_ice1712 *ice)
2236*4882a593Smuzhiyun {
2237*4882a593Smuzhiyun int t = 0x10000;
2238*4882a593Smuzhiyun while ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_BUSY) && t--)
2239*4882a593Smuzhiyun ;
2240*4882a593Smuzhiyun if (t == -1)
2241*4882a593Smuzhiyun dev_err(ice->card->dev, "i2c busy timeout\n");
2242*4882a593Smuzhiyun }
2243*4882a593Smuzhiyun
snd_vt1724_read_i2c(struct snd_ice1712 * ice,unsigned char dev,unsigned char addr)2244*4882a593Smuzhiyun unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice,
2245*4882a593Smuzhiyun unsigned char dev, unsigned char addr)
2246*4882a593Smuzhiyun {
2247*4882a593Smuzhiyun unsigned char val;
2248*4882a593Smuzhiyun
2249*4882a593Smuzhiyun mutex_lock(&ice->i2c_mutex);
2250*4882a593Smuzhiyun wait_i2c_busy(ice);
2251*4882a593Smuzhiyun outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
2252*4882a593Smuzhiyun outb(dev & ~VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
2253*4882a593Smuzhiyun wait_i2c_busy(ice);
2254*4882a593Smuzhiyun val = inb(ICEREG1724(ice, I2C_DATA));
2255*4882a593Smuzhiyun mutex_unlock(&ice->i2c_mutex);
2256*4882a593Smuzhiyun /*
2257*4882a593Smuzhiyun dev_dbg(ice->card->dev, "i2c_read: [0x%x,0x%x] = 0x%x\n", dev, addr, val);
2258*4882a593Smuzhiyun */
2259*4882a593Smuzhiyun return val;
2260*4882a593Smuzhiyun }
2261*4882a593Smuzhiyun
snd_vt1724_write_i2c(struct snd_ice1712 * ice,unsigned char dev,unsigned char addr,unsigned char data)2262*4882a593Smuzhiyun void snd_vt1724_write_i2c(struct snd_ice1712 *ice,
2263*4882a593Smuzhiyun unsigned char dev, unsigned char addr, unsigned char data)
2264*4882a593Smuzhiyun {
2265*4882a593Smuzhiyun mutex_lock(&ice->i2c_mutex);
2266*4882a593Smuzhiyun wait_i2c_busy(ice);
2267*4882a593Smuzhiyun /*
2268*4882a593Smuzhiyun dev_dbg(ice->card->dev, "i2c_write: [0x%x,0x%x] = 0x%x\n", dev, addr, data);
2269*4882a593Smuzhiyun */
2270*4882a593Smuzhiyun outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
2271*4882a593Smuzhiyun outb(data, ICEREG1724(ice, I2C_DATA));
2272*4882a593Smuzhiyun outb(dev | VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
2273*4882a593Smuzhiyun wait_i2c_busy(ice);
2274*4882a593Smuzhiyun mutex_unlock(&ice->i2c_mutex);
2275*4882a593Smuzhiyun }
2276*4882a593Smuzhiyun
snd_vt1724_read_eeprom(struct snd_ice1712 * ice,const char * modelname)2277*4882a593Smuzhiyun static int snd_vt1724_read_eeprom(struct snd_ice1712 *ice,
2278*4882a593Smuzhiyun const char *modelname)
2279*4882a593Smuzhiyun {
2280*4882a593Smuzhiyun const int dev = 0xa0; /* EEPROM device address */
2281*4882a593Smuzhiyun unsigned int i, size;
2282*4882a593Smuzhiyun const struct snd_ice1712_card_info * const *tbl, *c;
2283*4882a593Smuzhiyun
2284*4882a593Smuzhiyun if (!modelname || !*modelname) {
2285*4882a593Smuzhiyun ice->eeprom.subvendor = 0;
2286*4882a593Smuzhiyun if ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_EEPROM) != 0)
2287*4882a593Smuzhiyun ice->eeprom.subvendor =
2288*4882a593Smuzhiyun (snd_vt1724_read_i2c(ice, dev, 0x00) << 0) |
2289*4882a593Smuzhiyun (snd_vt1724_read_i2c(ice, dev, 0x01) << 8) |
2290*4882a593Smuzhiyun (snd_vt1724_read_i2c(ice, dev, 0x02) << 16) |
2291*4882a593Smuzhiyun (snd_vt1724_read_i2c(ice, dev, 0x03) << 24);
2292*4882a593Smuzhiyun if (ice->eeprom.subvendor == 0 ||
2293*4882a593Smuzhiyun ice->eeprom.subvendor == (unsigned int)-1) {
2294*4882a593Smuzhiyun /* invalid subvendor from EEPROM, try the PCI
2295*4882a593Smuzhiyun * subststem ID instead
2296*4882a593Smuzhiyun */
2297*4882a593Smuzhiyun u16 vendor, device;
2298*4882a593Smuzhiyun pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID,
2299*4882a593Smuzhiyun &vendor);
2300*4882a593Smuzhiyun pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
2301*4882a593Smuzhiyun ice->eeprom.subvendor =
2302*4882a593Smuzhiyun ((unsigned int)swab16(vendor) << 16) | swab16(device);
2303*4882a593Smuzhiyun if (ice->eeprom.subvendor == 0 ||
2304*4882a593Smuzhiyun ice->eeprom.subvendor == (unsigned int)-1) {
2305*4882a593Smuzhiyun dev_err(ice->card->dev,
2306*4882a593Smuzhiyun "No valid ID is found\n");
2307*4882a593Smuzhiyun return -ENXIO;
2308*4882a593Smuzhiyun }
2309*4882a593Smuzhiyun }
2310*4882a593Smuzhiyun }
2311*4882a593Smuzhiyun for (tbl = card_tables; *tbl; tbl++) {
2312*4882a593Smuzhiyun for (c = *tbl; c->name; c++) {
2313*4882a593Smuzhiyun if (modelname && c->model &&
2314*4882a593Smuzhiyun !strcmp(modelname, c->model)) {
2315*4882a593Smuzhiyun dev_info(ice->card->dev,
2316*4882a593Smuzhiyun "Using board model %s\n",
2317*4882a593Smuzhiyun c->name);
2318*4882a593Smuzhiyun ice->eeprom.subvendor = c->subvendor;
2319*4882a593Smuzhiyun } else if (c->subvendor != ice->eeprom.subvendor)
2320*4882a593Smuzhiyun continue;
2321*4882a593Smuzhiyun ice->card_info = c;
2322*4882a593Smuzhiyun if (!c->eeprom_size || !c->eeprom_data)
2323*4882a593Smuzhiyun goto found;
2324*4882a593Smuzhiyun /* if the EEPROM is given by the driver, use it */
2325*4882a593Smuzhiyun dev_dbg(ice->card->dev, "using the defined eeprom..\n");
2326*4882a593Smuzhiyun ice->eeprom.version = 2;
2327*4882a593Smuzhiyun ice->eeprom.size = c->eeprom_size + 6;
2328*4882a593Smuzhiyun memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
2329*4882a593Smuzhiyun goto read_skipped;
2330*4882a593Smuzhiyun }
2331*4882a593Smuzhiyun }
2332*4882a593Smuzhiyun dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
2333*4882a593Smuzhiyun ice->eeprom.subvendor);
2334*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
2335*4882a593Smuzhiyun /* assume AC97-only card which can suspend without additional code */
2336*4882a593Smuzhiyun ice->pm_suspend_enabled = 1;
2337*4882a593Smuzhiyun #endif
2338*4882a593Smuzhiyun
2339*4882a593Smuzhiyun found:
2340*4882a593Smuzhiyun ice->eeprom.size = snd_vt1724_read_i2c(ice, dev, 0x04);
2341*4882a593Smuzhiyun if (ice->eeprom.size < 6)
2342*4882a593Smuzhiyun ice->eeprom.size = 32;
2343*4882a593Smuzhiyun else if (ice->eeprom.size > 32) {
2344*4882a593Smuzhiyun dev_err(ice->card->dev, "Invalid EEPROM (size = %i)\n",
2345*4882a593Smuzhiyun ice->eeprom.size);
2346*4882a593Smuzhiyun return -EIO;
2347*4882a593Smuzhiyun }
2348*4882a593Smuzhiyun ice->eeprom.version = snd_vt1724_read_i2c(ice, dev, 0x05);
2349*4882a593Smuzhiyun if (ice->eeprom.version != 1 && ice->eeprom.version != 2)
2350*4882a593Smuzhiyun dev_warn(ice->card->dev, "Invalid EEPROM version %i\n",
2351*4882a593Smuzhiyun ice->eeprom.version);
2352*4882a593Smuzhiyun size = ice->eeprom.size - 6;
2353*4882a593Smuzhiyun for (i = 0; i < size; i++)
2354*4882a593Smuzhiyun ice->eeprom.data[i] = snd_vt1724_read_i2c(ice, dev, i + 6);
2355*4882a593Smuzhiyun
2356*4882a593Smuzhiyun read_skipped:
2357*4882a593Smuzhiyun ice->eeprom.gpiomask = eeprom_triple(ice, ICE_EEP2_GPIO_MASK);
2358*4882a593Smuzhiyun ice->eeprom.gpiostate = eeprom_triple(ice, ICE_EEP2_GPIO_STATE);
2359*4882a593Smuzhiyun ice->eeprom.gpiodir = eeprom_triple(ice, ICE_EEP2_GPIO_DIR);
2360*4882a593Smuzhiyun
2361*4882a593Smuzhiyun return 0;
2362*4882a593Smuzhiyun }
2363*4882a593Smuzhiyun
2364*4882a593Smuzhiyun
2365*4882a593Smuzhiyun
snd_vt1724_chip_reset(struct snd_ice1712 * ice)2366*4882a593Smuzhiyun static void snd_vt1724_chip_reset(struct snd_ice1712 *ice)
2367*4882a593Smuzhiyun {
2368*4882a593Smuzhiyun outb(VT1724_RESET , ICEREG1724(ice, CONTROL));
2369*4882a593Smuzhiyun inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
2370*4882a593Smuzhiyun msleep(10);
2371*4882a593Smuzhiyun outb(0, ICEREG1724(ice, CONTROL));
2372*4882a593Smuzhiyun inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
2373*4882a593Smuzhiyun msleep(10);
2374*4882a593Smuzhiyun }
2375*4882a593Smuzhiyun
snd_vt1724_chip_init(struct snd_ice1712 * ice)2376*4882a593Smuzhiyun static int snd_vt1724_chip_init(struct snd_ice1712 *ice)
2377*4882a593Smuzhiyun {
2378*4882a593Smuzhiyun outb(ice->eeprom.data[ICE_EEP2_SYSCONF], ICEREG1724(ice, SYS_CFG));
2379*4882a593Smuzhiyun outb(ice->eeprom.data[ICE_EEP2_ACLINK], ICEREG1724(ice, AC97_CFG));
2380*4882a593Smuzhiyun outb(ice->eeprom.data[ICE_EEP2_I2S], ICEREG1724(ice, I2S_FEATURES));
2381*4882a593Smuzhiyun outb(ice->eeprom.data[ICE_EEP2_SPDIF], ICEREG1724(ice, SPDIF_CFG));
2382*4882a593Smuzhiyun
2383*4882a593Smuzhiyun ice->gpio.write_mask = ice->eeprom.gpiomask;
2384*4882a593Smuzhiyun ice->gpio.direction = ice->eeprom.gpiodir;
2385*4882a593Smuzhiyun snd_vt1724_set_gpio_mask(ice, ice->eeprom.gpiomask);
2386*4882a593Smuzhiyun snd_vt1724_set_gpio_dir(ice, ice->eeprom.gpiodir);
2387*4882a593Smuzhiyun snd_vt1724_set_gpio_data(ice, ice->eeprom.gpiostate);
2388*4882a593Smuzhiyun
2389*4882a593Smuzhiyun outb(0, ICEREG1724(ice, POWERDOWN));
2390*4882a593Smuzhiyun
2391*4882a593Smuzhiyun /* MPU_RX and TX irq masks are cleared later dynamically */
2392*4882a593Smuzhiyun outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
2393*4882a593Smuzhiyun
2394*4882a593Smuzhiyun /* don't handle FIFO overrun/underruns (just yet),
2395*4882a593Smuzhiyun * since they cause machine lockups
2396*4882a593Smuzhiyun */
2397*4882a593Smuzhiyun outb(VT1724_MULTI_FIFO_ERR, ICEMT1724(ice, DMA_INT_MASK));
2398*4882a593Smuzhiyun
2399*4882a593Smuzhiyun return 0;
2400*4882a593Smuzhiyun }
2401*4882a593Smuzhiyun
snd_vt1724_spdif_build_controls(struct snd_ice1712 * ice)2402*4882a593Smuzhiyun static int snd_vt1724_spdif_build_controls(struct snd_ice1712 *ice)
2403*4882a593Smuzhiyun {
2404*4882a593Smuzhiyun int err;
2405*4882a593Smuzhiyun struct snd_kcontrol *kctl;
2406*4882a593Smuzhiyun
2407*4882a593Smuzhiyun if (snd_BUG_ON(!ice->pcm))
2408*4882a593Smuzhiyun return -EIO;
2409*4882a593Smuzhiyun
2410*4882a593Smuzhiyun if (!ice->own_routing) {
2411*4882a593Smuzhiyun err = snd_ctl_add(ice->card,
2412*4882a593Smuzhiyun snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice));
2413*4882a593Smuzhiyun if (err < 0)
2414*4882a593Smuzhiyun return err;
2415*4882a593Smuzhiyun }
2416*4882a593Smuzhiyun
2417*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice));
2418*4882a593Smuzhiyun if (err < 0)
2419*4882a593Smuzhiyun return err;
2420*4882a593Smuzhiyun
2421*4882a593Smuzhiyun err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_default, ice));
2422*4882a593Smuzhiyun if (err < 0)
2423*4882a593Smuzhiyun return err;
2424*4882a593Smuzhiyun kctl->id.device = ice->pcm->device;
2425*4882a593Smuzhiyun err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskc, ice));
2426*4882a593Smuzhiyun if (err < 0)
2427*4882a593Smuzhiyun return err;
2428*4882a593Smuzhiyun kctl->id.device = ice->pcm->device;
2429*4882a593Smuzhiyun err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskp, ice));
2430*4882a593Smuzhiyun if (err < 0)
2431*4882a593Smuzhiyun return err;
2432*4882a593Smuzhiyun kctl->id.device = ice->pcm->device;
2433*4882a593Smuzhiyun #if 0 /* use default only */
2434*4882a593Smuzhiyun err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_stream, ice));
2435*4882a593Smuzhiyun if (err < 0)
2436*4882a593Smuzhiyun return err;
2437*4882a593Smuzhiyun kctl->id.device = ice->pcm->device;
2438*4882a593Smuzhiyun ice->spdif.stream_ctl = kctl;
2439*4882a593Smuzhiyun #endif
2440*4882a593Smuzhiyun return 0;
2441*4882a593Smuzhiyun }
2442*4882a593Smuzhiyun
2443*4882a593Smuzhiyun
snd_vt1724_build_controls(struct snd_ice1712 * ice)2444*4882a593Smuzhiyun static int snd_vt1724_build_controls(struct snd_ice1712 *ice)
2445*4882a593Smuzhiyun {
2446*4882a593Smuzhiyun int err;
2447*4882a593Smuzhiyun
2448*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_eeprom, ice));
2449*4882a593Smuzhiyun if (err < 0)
2450*4882a593Smuzhiyun return err;
2451*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_internal_clock, ice));
2452*4882a593Smuzhiyun if (err < 0)
2453*4882a593Smuzhiyun return err;
2454*4882a593Smuzhiyun
2455*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_locking, ice));
2456*4882a593Smuzhiyun if (err < 0)
2457*4882a593Smuzhiyun return err;
2458*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_reset, ice));
2459*4882a593Smuzhiyun if (err < 0)
2460*4882a593Smuzhiyun return err;
2461*4882a593Smuzhiyun
2462*4882a593Smuzhiyun if (!ice->own_routing && ice->num_total_dacs > 0) {
2463*4882a593Smuzhiyun struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route;
2464*4882a593Smuzhiyun tmp.count = ice->num_total_dacs;
2465*4882a593Smuzhiyun if (ice->vt1720 && tmp.count > 2)
2466*4882a593Smuzhiyun tmp.count = 2;
2467*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
2468*4882a593Smuzhiyun if (err < 0)
2469*4882a593Smuzhiyun return err;
2470*4882a593Smuzhiyun }
2471*4882a593Smuzhiyun
2472*4882a593Smuzhiyun return snd_ctl_add(ice->card,
2473*4882a593Smuzhiyun snd_ctl_new1(&snd_vt1724_mixer_pro_peak, ice));
2474*4882a593Smuzhiyun }
2475*4882a593Smuzhiyun
snd_vt1724_free(struct snd_ice1712 * ice)2476*4882a593Smuzhiyun static int snd_vt1724_free(struct snd_ice1712 *ice)
2477*4882a593Smuzhiyun {
2478*4882a593Smuzhiyun if (!ice->port)
2479*4882a593Smuzhiyun goto __hw_end;
2480*4882a593Smuzhiyun /* mask all interrupts */
2481*4882a593Smuzhiyun outb(0xff, ICEMT1724(ice, DMA_INT_MASK));
2482*4882a593Smuzhiyun outb(0xff, ICEREG1724(ice, IRQMASK));
2483*4882a593Smuzhiyun /* --- */
2484*4882a593Smuzhiyun __hw_end:
2485*4882a593Smuzhiyun if (ice->irq >= 0)
2486*4882a593Smuzhiyun free_irq(ice->irq, ice);
2487*4882a593Smuzhiyun pci_release_regions(ice->pci);
2488*4882a593Smuzhiyun snd_ice1712_akm4xxx_free(ice);
2489*4882a593Smuzhiyun pci_disable_device(ice->pci);
2490*4882a593Smuzhiyun kfree(ice->spec);
2491*4882a593Smuzhiyun kfree(ice);
2492*4882a593Smuzhiyun return 0;
2493*4882a593Smuzhiyun }
2494*4882a593Smuzhiyun
snd_vt1724_dev_free(struct snd_device * device)2495*4882a593Smuzhiyun static int snd_vt1724_dev_free(struct snd_device *device)
2496*4882a593Smuzhiyun {
2497*4882a593Smuzhiyun struct snd_ice1712 *ice = device->device_data;
2498*4882a593Smuzhiyun return snd_vt1724_free(ice);
2499*4882a593Smuzhiyun }
2500*4882a593Smuzhiyun
snd_vt1724_create(struct snd_card * card,struct pci_dev * pci,const char * modelname,struct snd_ice1712 ** r_ice1712)2501*4882a593Smuzhiyun static int snd_vt1724_create(struct snd_card *card,
2502*4882a593Smuzhiyun struct pci_dev *pci,
2503*4882a593Smuzhiyun const char *modelname,
2504*4882a593Smuzhiyun struct snd_ice1712 **r_ice1712)
2505*4882a593Smuzhiyun {
2506*4882a593Smuzhiyun struct snd_ice1712 *ice;
2507*4882a593Smuzhiyun int err;
2508*4882a593Smuzhiyun static const struct snd_device_ops ops = {
2509*4882a593Smuzhiyun .dev_free = snd_vt1724_dev_free,
2510*4882a593Smuzhiyun };
2511*4882a593Smuzhiyun
2512*4882a593Smuzhiyun *r_ice1712 = NULL;
2513*4882a593Smuzhiyun
2514*4882a593Smuzhiyun /* enable PCI device */
2515*4882a593Smuzhiyun err = pci_enable_device(pci);
2516*4882a593Smuzhiyun if (err < 0)
2517*4882a593Smuzhiyun return err;
2518*4882a593Smuzhiyun
2519*4882a593Smuzhiyun ice = kzalloc(sizeof(*ice), GFP_KERNEL);
2520*4882a593Smuzhiyun if (ice == NULL) {
2521*4882a593Smuzhiyun pci_disable_device(pci);
2522*4882a593Smuzhiyun return -ENOMEM;
2523*4882a593Smuzhiyun }
2524*4882a593Smuzhiyun ice->vt1724 = 1;
2525*4882a593Smuzhiyun spin_lock_init(&ice->reg_lock);
2526*4882a593Smuzhiyun mutex_init(&ice->gpio_mutex);
2527*4882a593Smuzhiyun mutex_init(&ice->open_mutex);
2528*4882a593Smuzhiyun mutex_init(&ice->i2c_mutex);
2529*4882a593Smuzhiyun ice->gpio.set_mask = snd_vt1724_set_gpio_mask;
2530*4882a593Smuzhiyun ice->gpio.get_mask = snd_vt1724_get_gpio_mask;
2531*4882a593Smuzhiyun ice->gpio.set_dir = snd_vt1724_set_gpio_dir;
2532*4882a593Smuzhiyun ice->gpio.get_dir = snd_vt1724_get_gpio_dir;
2533*4882a593Smuzhiyun ice->gpio.set_data = snd_vt1724_set_gpio_data;
2534*4882a593Smuzhiyun ice->gpio.get_data = snd_vt1724_get_gpio_data;
2535*4882a593Smuzhiyun ice->card = card;
2536*4882a593Smuzhiyun ice->pci = pci;
2537*4882a593Smuzhiyun ice->irq = -1;
2538*4882a593Smuzhiyun pci_set_master(pci);
2539*4882a593Smuzhiyun snd_vt1724_proc_init(ice);
2540*4882a593Smuzhiyun
2541*4882a593Smuzhiyun card->private_data = ice;
2542*4882a593Smuzhiyun
2543*4882a593Smuzhiyun err = pci_request_regions(pci, "ICE1724");
2544*4882a593Smuzhiyun if (err < 0) {
2545*4882a593Smuzhiyun kfree(ice);
2546*4882a593Smuzhiyun pci_disable_device(pci);
2547*4882a593Smuzhiyun return err;
2548*4882a593Smuzhiyun }
2549*4882a593Smuzhiyun ice->port = pci_resource_start(pci, 0);
2550*4882a593Smuzhiyun ice->profi_port = pci_resource_start(pci, 1);
2551*4882a593Smuzhiyun
2552*4882a593Smuzhiyun if (request_irq(pci->irq, snd_vt1724_interrupt,
2553*4882a593Smuzhiyun IRQF_SHARED, KBUILD_MODNAME, ice)) {
2554*4882a593Smuzhiyun dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2555*4882a593Smuzhiyun snd_vt1724_free(ice);
2556*4882a593Smuzhiyun return -EIO;
2557*4882a593Smuzhiyun }
2558*4882a593Smuzhiyun
2559*4882a593Smuzhiyun ice->irq = pci->irq;
2560*4882a593Smuzhiyun card->sync_irq = ice->irq;
2561*4882a593Smuzhiyun
2562*4882a593Smuzhiyun snd_vt1724_chip_reset(ice);
2563*4882a593Smuzhiyun if (snd_vt1724_read_eeprom(ice, modelname) < 0) {
2564*4882a593Smuzhiyun snd_vt1724_free(ice);
2565*4882a593Smuzhiyun return -EIO;
2566*4882a593Smuzhiyun }
2567*4882a593Smuzhiyun if (snd_vt1724_chip_init(ice) < 0) {
2568*4882a593Smuzhiyun snd_vt1724_free(ice);
2569*4882a593Smuzhiyun return -EIO;
2570*4882a593Smuzhiyun }
2571*4882a593Smuzhiyun
2572*4882a593Smuzhiyun err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
2573*4882a593Smuzhiyun if (err < 0) {
2574*4882a593Smuzhiyun snd_vt1724_free(ice);
2575*4882a593Smuzhiyun return err;
2576*4882a593Smuzhiyun }
2577*4882a593Smuzhiyun
2578*4882a593Smuzhiyun *r_ice1712 = ice;
2579*4882a593Smuzhiyun return 0;
2580*4882a593Smuzhiyun }
2581*4882a593Smuzhiyun
2582*4882a593Smuzhiyun
2583*4882a593Smuzhiyun /*
2584*4882a593Smuzhiyun *
2585*4882a593Smuzhiyun * Registration
2586*4882a593Smuzhiyun *
2587*4882a593Smuzhiyun */
2588*4882a593Smuzhiyun
snd_vt1724_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2589*4882a593Smuzhiyun static int snd_vt1724_probe(struct pci_dev *pci,
2590*4882a593Smuzhiyun const struct pci_device_id *pci_id)
2591*4882a593Smuzhiyun {
2592*4882a593Smuzhiyun static int dev;
2593*4882a593Smuzhiyun struct snd_card *card;
2594*4882a593Smuzhiyun struct snd_ice1712 *ice;
2595*4882a593Smuzhiyun int pcm_dev = 0, err;
2596*4882a593Smuzhiyun const struct snd_ice1712_card_info * const *tbl, *c;
2597*4882a593Smuzhiyun
2598*4882a593Smuzhiyun if (dev >= SNDRV_CARDS)
2599*4882a593Smuzhiyun return -ENODEV;
2600*4882a593Smuzhiyun if (!enable[dev]) {
2601*4882a593Smuzhiyun dev++;
2602*4882a593Smuzhiyun return -ENOENT;
2603*4882a593Smuzhiyun }
2604*4882a593Smuzhiyun
2605*4882a593Smuzhiyun err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2606*4882a593Smuzhiyun 0, &card);
2607*4882a593Smuzhiyun if (err < 0)
2608*4882a593Smuzhiyun return err;
2609*4882a593Smuzhiyun
2610*4882a593Smuzhiyun strcpy(card->driver, "ICE1724");
2611*4882a593Smuzhiyun strcpy(card->shortname, "ICEnsemble ICE1724");
2612*4882a593Smuzhiyun
2613*4882a593Smuzhiyun err = snd_vt1724_create(card, pci, model[dev], &ice);
2614*4882a593Smuzhiyun if (err < 0) {
2615*4882a593Smuzhiyun snd_card_free(card);
2616*4882a593Smuzhiyun return err;
2617*4882a593Smuzhiyun }
2618*4882a593Smuzhiyun
2619*4882a593Smuzhiyun /* field init before calling chip_init */
2620*4882a593Smuzhiyun ice->ext_clock_count = 0;
2621*4882a593Smuzhiyun
2622*4882a593Smuzhiyun for (tbl = card_tables; *tbl; tbl++) {
2623*4882a593Smuzhiyun for (c = *tbl; c->name; c++) {
2624*4882a593Smuzhiyun if ((model[dev] && c->model &&
2625*4882a593Smuzhiyun !strcmp(model[dev], c->model)) ||
2626*4882a593Smuzhiyun (c->subvendor == ice->eeprom.subvendor)) {
2627*4882a593Smuzhiyun strcpy(card->shortname, c->name);
2628*4882a593Smuzhiyun if (c->driver) /* specific driver? */
2629*4882a593Smuzhiyun strcpy(card->driver, c->driver);
2630*4882a593Smuzhiyun if (c->chip_init) {
2631*4882a593Smuzhiyun err = c->chip_init(ice);
2632*4882a593Smuzhiyun if (err < 0) {
2633*4882a593Smuzhiyun snd_card_free(card);
2634*4882a593Smuzhiyun return err;
2635*4882a593Smuzhiyun }
2636*4882a593Smuzhiyun }
2637*4882a593Smuzhiyun goto __found;
2638*4882a593Smuzhiyun }
2639*4882a593Smuzhiyun }
2640*4882a593Smuzhiyun }
2641*4882a593Smuzhiyun c = &no_matched;
2642*4882a593Smuzhiyun __found:
2643*4882a593Smuzhiyun /*
2644*4882a593Smuzhiyun * VT1724 has separate DMAs for the analog and the SPDIF streams while
2645*4882a593Smuzhiyun * ICE1712 has only one for both (mixed up).
2646*4882a593Smuzhiyun *
2647*4882a593Smuzhiyun * Confusingly the analog PCM is named "professional" here because it
2648*4882a593Smuzhiyun * was called so in ice1712 driver, and vt1724 driver is derived from
2649*4882a593Smuzhiyun * ice1712 driver.
2650*4882a593Smuzhiyun */
2651*4882a593Smuzhiyun ice->pro_rate_default = PRO_RATE_DEFAULT;
2652*4882a593Smuzhiyun if (!ice->is_spdif_master)
2653*4882a593Smuzhiyun ice->is_spdif_master = stdclock_is_spdif_master;
2654*4882a593Smuzhiyun if (!ice->get_rate)
2655*4882a593Smuzhiyun ice->get_rate = stdclock_get_rate;
2656*4882a593Smuzhiyun if (!ice->set_rate)
2657*4882a593Smuzhiyun ice->set_rate = stdclock_set_rate;
2658*4882a593Smuzhiyun if (!ice->set_mclk)
2659*4882a593Smuzhiyun ice->set_mclk = stdclock_set_mclk;
2660*4882a593Smuzhiyun if (!ice->set_spdif_clock)
2661*4882a593Smuzhiyun ice->set_spdif_clock = stdclock_set_spdif_clock;
2662*4882a593Smuzhiyun if (!ice->get_spdif_master_type)
2663*4882a593Smuzhiyun ice->get_spdif_master_type = stdclock_get_spdif_master_type;
2664*4882a593Smuzhiyun if (!ice->ext_clock_names)
2665*4882a593Smuzhiyun ice->ext_clock_names = ext_clock_names;
2666*4882a593Smuzhiyun if (!ice->ext_clock_count)
2667*4882a593Smuzhiyun ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
2668*4882a593Smuzhiyun
2669*4882a593Smuzhiyun if (!ice->hw_rates)
2670*4882a593Smuzhiyun set_std_hw_rates(ice);
2671*4882a593Smuzhiyun
2672*4882a593Smuzhiyun err = snd_vt1724_pcm_profi(ice, pcm_dev++);
2673*4882a593Smuzhiyun if (err < 0) {
2674*4882a593Smuzhiyun snd_card_free(card);
2675*4882a593Smuzhiyun return err;
2676*4882a593Smuzhiyun }
2677*4882a593Smuzhiyun
2678*4882a593Smuzhiyun err = snd_vt1724_pcm_spdif(ice, pcm_dev++);
2679*4882a593Smuzhiyun if (err < 0) {
2680*4882a593Smuzhiyun snd_card_free(card);
2681*4882a593Smuzhiyun return err;
2682*4882a593Smuzhiyun }
2683*4882a593Smuzhiyun
2684*4882a593Smuzhiyun err = snd_vt1724_pcm_indep(ice, pcm_dev++);
2685*4882a593Smuzhiyun if (err < 0) {
2686*4882a593Smuzhiyun snd_card_free(card);
2687*4882a593Smuzhiyun return err;
2688*4882a593Smuzhiyun }
2689*4882a593Smuzhiyun
2690*4882a593Smuzhiyun err = snd_vt1724_ac97_mixer(ice);
2691*4882a593Smuzhiyun if (err < 0) {
2692*4882a593Smuzhiyun snd_card_free(card);
2693*4882a593Smuzhiyun return err;
2694*4882a593Smuzhiyun }
2695*4882a593Smuzhiyun
2696*4882a593Smuzhiyun err = snd_vt1724_build_controls(ice);
2697*4882a593Smuzhiyun if (err < 0) {
2698*4882a593Smuzhiyun snd_card_free(card);
2699*4882a593Smuzhiyun return err;
2700*4882a593Smuzhiyun }
2701*4882a593Smuzhiyun
2702*4882a593Smuzhiyun if (ice->pcm && ice->has_spdif) { /* has SPDIF I/O */
2703*4882a593Smuzhiyun err = snd_vt1724_spdif_build_controls(ice);
2704*4882a593Smuzhiyun if (err < 0) {
2705*4882a593Smuzhiyun snd_card_free(card);
2706*4882a593Smuzhiyun return err;
2707*4882a593Smuzhiyun }
2708*4882a593Smuzhiyun }
2709*4882a593Smuzhiyun
2710*4882a593Smuzhiyun if (c->build_controls) {
2711*4882a593Smuzhiyun err = c->build_controls(ice);
2712*4882a593Smuzhiyun if (err < 0) {
2713*4882a593Smuzhiyun snd_card_free(card);
2714*4882a593Smuzhiyun return err;
2715*4882a593Smuzhiyun }
2716*4882a593Smuzhiyun }
2717*4882a593Smuzhiyun
2718*4882a593Smuzhiyun if (!c->no_mpu401) {
2719*4882a593Smuzhiyun if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
2720*4882a593Smuzhiyun struct snd_rawmidi *rmidi;
2721*4882a593Smuzhiyun
2722*4882a593Smuzhiyun err = snd_rawmidi_new(card, "MIDI", 0, 1, 1, &rmidi);
2723*4882a593Smuzhiyun if (err < 0) {
2724*4882a593Smuzhiyun snd_card_free(card);
2725*4882a593Smuzhiyun return err;
2726*4882a593Smuzhiyun }
2727*4882a593Smuzhiyun ice->rmidi[0] = rmidi;
2728*4882a593Smuzhiyun rmidi->private_data = ice;
2729*4882a593Smuzhiyun strcpy(rmidi->name, "ICE1724 MIDI");
2730*4882a593Smuzhiyun rmidi->info_flags = SNDRV_RAWMIDI_INFO_OUTPUT |
2731*4882a593Smuzhiyun SNDRV_RAWMIDI_INFO_INPUT |
2732*4882a593Smuzhiyun SNDRV_RAWMIDI_INFO_DUPLEX;
2733*4882a593Smuzhiyun snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
2734*4882a593Smuzhiyun &vt1724_midi_output_ops);
2735*4882a593Smuzhiyun snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
2736*4882a593Smuzhiyun &vt1724_midi_input_ops);
2737*4882a593Smuzhiyun
2738*4882a593Smuzhiyun /* set watermarks */
2739*4882a593Smuzhiyun outb(VT1724_MPU_RX_FIFO | 0x1,
2740*4882a593Smuzhiyun ICEREG1724(ice, MPU_FIFO_WM));
2741*4882a593Smuzhiyun outb(0x1, ICEREG1724(ice, MPU_FIFO_WM));
2742*4882a593Smuzhiyun /* set UART mode */
2743*4882a593Smuzhiyun outb(VT1724_MPU_UART, ICEREG1724(ice, MPU_CTRL));
2744*4882a593Smuzhiyun }
2745*4882a593Smuzhiyun }
2746*4882a593Smuzhiyun
2747*4882a593Smuzhiyun sprintf(card->longname, "%s at 0x%lx, irq %i",
2748*4882a593Smuzhiyun card->shortname, ice->port, ice->irq);
2749*4882a593Smuzhiyun
2750*4882a593Smuzhiyun err = snd_card_register(card);
2751*4882a593Smuzhiyun if (err < 0) {
2752*4882a593Smuzhiyun snd_card_free(card);
2753*4882a593Smuzhiyun return err;
2754*4882a593Smuzhiyun }
2755*4882a593Smuzhiyun pci_set_drvdata(pci, card);
2756*4882a593Smuzhiyun dev++;
2757*4882a593Smuzhiyun return 0;
2758*4882a593Smuzhiyun }
2759*4882a593Smuzhiyun
snd_vt1724_remove(struct pci_dev * pci)2760*4882a593Smuzhiyun static void snd_vt1724_remove(struct pci_dev *pci)
2761*4882a593Smuzhiyun {
2762*4882a593Smuzhiyun struct snd_card *card = pci_get_drvdata(pci);
2763*4882a593Smuzhiyun struct snd_ice1712 *ice = card->private_data;
2764*4882a593Smuzhiyun
2765*4882a593Smuzhiyun if (ice->card_info && ice->card_info->chip_exit)
2766*4882a593Smuzhiyun ice->card_info->chip_exit(ice);
2767*4882a593Smuzhiyun snd_card_free(card);
2768*4882a593Smuzhiyun }
2769*4882a593Smuzhiyun
2770*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
snd_vt1724_suspend(struct device * dev)2771*4882a593Smuzhiyun static int snd_vt1724_suspend(struct device *dev)
2772*4882a593Smuzhiyun {
2773*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
2774*4882a593Smuzhiyun struct snd_ice1712 *ice = card->private_data;
2775*4882a593Smuzhiyun
2776*4882a593Smuzhiyun if (!ice->pm_suspend_enabled)
2777*4882a593Smuzhiyun return 0;
2778*4882a593Smuzhiyun
2779*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2780*4882a593Smuzhiyun
2781*4882a593Smuzhiyun snd_ac97_suspend(ice->ac97);
2782*4882a593Smuzhiyun
2783*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
2784*4882a593Smuzhiyun ice->pm_saved_is_spdif_master = ice->is_spdif_master(ice);
2785*4882a593Smuzhiyun ice->pm_saved_spdif_ctrl = inw(ICEMT1724(ice, SPDIF_CTRL));
2786*4882a593Smuzhiyun ice->pm_saved_spdif_cfg = inb(ICEREG1724(ice, SPDIF_CFG));
2787*4882a593Smuzhiyun ice->pm_saved_route = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2788*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
2789*4882a593Smuzhiyun
2790*4882a593Smuzhiyun if (ice->pm_suspend)
2791*4882a593Smuzhiyun ice->pm_suspend(ice);
2792*4882a593Smuzhiyun return 0;
2793*4882a593Smuzhiyun }
2794*4882a593Smuzhiyun
snd_vt1724_resume(struct device * dev)2795*4882a593Smuzhiyun static int snd_vt1724_resume(struct device *dev)
2796*4882a593Smuzhiyun {
2797*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
2798*4882a593Smuzhiyun struct snd_ice1712 *ice = card->private_data;
2799*4882a593Smuzhiyun
2800*4882a593Smuzhiyun if (!ice->pm_suspend_enabled)
2801*4882a593Smuzhiyun return 0;
2802*4882a593Smuzhiyun
2803*4882a593Smuzhiyun snd_vt1724_chip_reset(ice);
2804*4882a593Smuzhiyun
2805*4882a593Smuzhiyun if (snd_vt1724_chip_init(ice) < 0) {
2806*4882a593Smuzhiyun snd_card_disconnect(card);
2807*4882a593Smuzhiyun return -EIO;
2808*4882a593Smuzhiyun }
2809*4882a593Smuzhiyun
2810*4882a593Smuzhiyun if (ice->pm_resume)
2811*4882a593Smuzhiyun ice->pm_resume(ice);
2812*4882a593Smuzhiyun
2813*4882a593Smuzhiyun if (ice->pm_saved_is_spdif_master) {
2814*4882a593Smuzhiyun /* switching to external clock via SPDIF */
2815*4882a593Smuzhiyun ice->set_spdif_clock(ice, 0);
2816*4882a593Smuzhiyun } else {
2817*4882a593Smuzhiyun /* internal on-card clock */
2818*4882a593Smuzhiyun int rate;
2819*4882a593Smuzhiyun if (ice->cur_rate)
2820*4882a593Smuzhiyun rate = ice->cur_rate;
2821*4882a593Smuzhiyun else
2822*4882a593Smuzhiyun rate = ice->pro_rate_default;
2823*4882a593Smuzhiyun snd_vt1724_set_pro_rate(ice, rate, 1);
2824*4882a593Smuzhiyun }
2825*4882a593Smuzhiyun
2826*4882a593Smuzhiyun update_spdif_bits(ice, ice->pm_saved_spdif_ctrl);
2827*4882a593Smuzhiyun
2828*4882a593Smuzhiyun outb(ice->pm_saved_spdif_cfg, ICEREG1724(ice, SPDIF_CFG));
2829*4882a593Smuzhiyun outl(ice->pm_saved_route, ICEMT1724(ice, ROUTE_PLAYBACK));
2830*4882a593Smuzhiyun
2831*4882a593Smuzhiyun snd_ac97_resume(ice->ac97);
2832*4882a593Smuzhiyun
2833*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2834*4882a593Smuzhiyun return 0;
2835*4882a593Smuzhiyun }
2836*4882a593Smuzhiyun
2837*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(snd_vt1724_pm, snd_vt1724_suspend, snd_vt1724_resume);
2838*4882a593Smuzhiyun #define SND_VT1724_PM_OPS &snd_vt1724_pm
2839*4882a593Smuzhiyun #else
2840*4882a593Smuzhiyun #define SND_VT1724_PM_OPS NULL
2841*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
2842*4882a593Smuzhiyun
2843*4882a593Smuzhiyun static struct pci_driver vt1724_driver = {
2844*4882a593Smuzhiyun .name = KBUILD_MODNAME,
2845*4882a593Smuzhiyun .id_table = snd_vt1724_ids,
2846*4882a593Smuzhiyun .probe = snd_vt1724_probe,
2847*4882a593Smuzhiyun .remove = snd_vt1724_remove,
2848*4882a593Smuzhiyun .driver = {
2849*4882a593Smuzhiyun .pm = SND_VT1724_PM_OPS,
2850*4882a593Smuzhiyun },
2851*4882a593Smuzhiyun };
2852*4882a593Smuzhiyun
2853*4882a593Smuzhiyun module_pci_driver(vt1724_driver);
2854