1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ALSA driver for ICEnsemble ICE1712 (Envy24)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun NOTES:
10*4882a593Smuzhiyun - spdif nonaudio consumer mode does not work (at least with my
11*4882a593Smuzhiyun Sony STR-DB830)
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /*
15*4882a593Smuzhiyun * Changes:
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * 2002.09.09 Takashi Iwai <tiwai@suse.de>
18*4882a593Smuzhiyun * split the code to several files. each low-level routine
19*4882a593Smuzhiyun * is stored in the local file and called from registration
20*4882a593Smuzhiyun * function from card_info struct.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * 2002.11.26 James Stafford <jstafford@ampltd.com>
23*4882a593Smuzhiyun * Added support for VT1724 (Envy24HT)
24*4882a593Smuzhiyun * I have left out support for 176.4 and 192 KHz for the moment.
25*4882a593Smuzhiyun * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
28*4882a593Smuzhiyun * Split vt1724 part to an independent driver.
29*4882a593Smuzhiyun * The GPIO is accessed through the callback functions now.
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun * 2004.03.31 Doug McLain <nostar@comcast.net>
32*4882a593Smuzhiyun * Added support for Event Electronics EZ8 card to hoontech.c.
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #include <linux/delay.h>
37*4882a593Smuzhiyun #include <linux/interrupt.h>
38*4882a593Smuzhiyun #include <linux/init.h>
39*4882a593Smuzhiyun #include <linux/pci.h>
40*4882a593Smuzhiyun #include <linux/dma-mapping.h>
41*4882a593Smuzhiyun #include <linux/slab.h>
42*4882a593Smuzhiyun #include <linux/module.h>
43*4882a593Smuzhiyun #include <linux/mutex.h>
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #include <sound/core.h>
46*4882a593Smuzhiyun #include <sound/cs8427.h>
47*4882a593Smuzhiyun #include <sound/info.h>
48*4882a593Smuzhiyun #include <sound/initval.h>
49*4882a593Smuzhiyun #include <sound/tlv.h>
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #include <sound/asoundef.h>
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #include "ice1712.h"
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* lowlevel routines */
56*4882a593Smuzhiyun #include "delta.h"
57*4882a593Smuzhiyun #include "ews.h"
58*4882a593Smuzhiyun #include "hoontech.h"
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
61*4882a593Smuzhiyun MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
62*4882a593Smuzhiyun MODULE_LICENSE("GPL");
63*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{"
64*4882a593Smuzhiyun HOONTECH_DEVICE_DESC
65*4882a593Smuzhiyun DELTA_DEVICE_DESC
66*4882a593Smuzhiyun EWS_DEVICE_DESC
67*4882a593Smuzhiyun "{ICEnsemble,Generic ICE1712},"
68*4882a593Smuzhiyun "{ICEnsemble,Generic Envy24}}");
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
71*4882a593Smuzhiyun static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
72*4882a593Smuzhiyun static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
73*4882a593Smuzhiyun static char *model[SNDRV_CARDS];
74*4882a593Smuzhiyun static bool omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
75*4882a593Smuzhiyun static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transceiver reset timeout value in msec */
76*4882a593Smuzhiyun static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun module_param_array(index, int, NULL, 0444);
79*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
80*4882a593Smuzhiyun module_param_array(id, charp, NULL, 0444);
81*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
82*4882a593Smuzhiyun module_param_array(enable, bool, NULL, 0444);
83*4882a593Smuzhiyun MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
84*4882a593Smuzhiyun module_param_array(omni, bool, NULL, 0444);
85*4882a593Smuzhiyun MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
86*4882a593Smuzhiyun module_param_array(cs8427_timeout, int, NULL, 0444);
87*4882a593Smuzhiyun MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
88*4882a593Smuzhiyun module_param_array(model, charp, NULL, 0444);
89*4882a593Smuzhiyun MODULE_PARM_DESC(model, "Use the given board model.");
90*4882a593Smuzhiyun module_param_array(dxr_enable, int, NULL, 0444);
91*4882a593Smuzhiyun MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static const struct pci_device_id snd_ice1712_ids[] = {
95*4882a593Smuzhiyun { PCI_VDEVICE(ICE, PCI_DEVICE_ID_ICE_1712), 0 }, /* ICE1712 */
96*4882a593Smuzhiyun { 0, }
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
102*4882a593Smuzhiyun static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static int PRO_RATE_LOCKED;
105*4882a593Smuzhiyun static int PRO_RATE_RESET = 1;
106*4882a593Smuzhiyun static unsigned int PRO_RATE_DEFAULT = 44100;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun * Basic I/O
110*4882a593Smuzhiyun */
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* check whether the clock mode is spdif-in */
is_spdif_master(struct snd_ice1712 * ice)113*4882a593Smuzhiyun static inline int is_spdif_master(struct snd_ice1712 *ice)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
is_pro_rate_locked(struct snd_ice1712 * ice)118*4882a593Smuzhiyun static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun return is_spdif_master(ice) || PRO_RATE_LOCKED;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
snd_ice1712_ds_write(struct snd_ice1712 * ice,u8 channel,u8 addr,u32 data)123*4882a593Smuzhiyun static inline void snd_ice1712_ds_write(struct snd_ice1712 *ice, u8 channel, u8 addr, u32 data)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun outb((channel << 4) | addr, ICEDS(ice, INDEX));
126*4882a593Smuzhiyun outl(data, ICEDS(ice, DATA));
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
snd_ice1712_ds_read(struct snd_ice1712 * ice,u8 channel,u8 addr)129*4882a593Smuzhiyun static inline u32 snd_ice1712_ds_read(struct snd_ice1712 *ice, u8 channel, u8 addr)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun outb((channel << 4) | addr, ICEDS(ice, INDEX));
132*4882a593Smuzhiyun return inl(ICEDS(ice, DATA));
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
snd_ice1712_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)135*4882a593Smuzhiyun static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
136*4882a593Smuzhiyun unsigned short reg,
137*4882a593Smuzhiyun unsigned short val)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun struct snd_ice1712 *ice = ac97->private_data;
140*4882a593Smuzhiyun int tm;
141*4882a593Smuzhiyun unsigned char old_cmd = 0;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun for (tm = 0; tm < 0x10000; tm++) {
144*4882a593Smuzhiyun old_cmd = inb(ICEREG(ice, AC97_CMD));
145*4882a593Smuzhiyun if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
146*4882a593Smuzhiyun continue;
147*4882a593Smuzhiyun if (!(old_cmd & ICE1712_AC97_READY))
148*4882a593Smuzhiyun continue;
149*4882a593Smuzhiyun break;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun outb(reg, ICEREG(ice, AC97_INDEX));
152*4882a593Smuzhiyun outw(val, ICEREG(ice, AC97_DATA));
153*4882a593Smuzhiyun old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
154*4882a593Smuzhiyun outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
155*4882a593Smuzhiyun for (tm = 0; tm < 0x10000; tm++)
156*4882a593Smuzhiyun if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
157*4882a593Smuzhiyun break;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
snd_ice1712_ac97_read(struct snd_ac97 * ac97,unsigned short reg)160*4882a593Smuzhiyun static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
161*4882a593Smuzhiyun unsigned short reg)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun struct snd_ice1712 *ice = ac97->private_data;
164*4882a593Smuzhiyun int tm;
165*4882a593Smuzhiyun unsigned char old_cmd = 0;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun for (tm = 0; tm < 0x10000; tm++) {
168*4882a593Smuzhiyun old_cmd = inb(ICEREG(ice, AC97_CMD));
169*4882a593Smuzhiyun if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
170*4882a593Smuzhiyun continue;
171*4882a593Smuzhiyun if (!(old_cmd & ICE1712_AC97_READY))
172*4882a593Smuzhiyun continue;
173*4882a593Smuzhiyun break;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun outb(reg, ICEREG(ice, AC97_INDEX));
176*4882a593Smuzhiyun outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
177*4882a593Smuzhiyun for (tm = 0; tm < 0x10000; tm++)
178*4882a593Smuzhiyun if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
179*4882a593Smuzhiyun break;
180*4882a593Smuzhiyun if (tm >= 0x10000) /* timeout */
181*4882a593Smuzhiyun return ~0;
182*4882a593Smuzhiyun return inw(ICEREG(ice, AC97_DATA));
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /*
186*4882a593Smuzhiyun * pro ac97 section
187*4882a593Smuzhiyun */
188*4882a593Smuzhiyun
snd_ice1712_pro_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)189*4882a593Smuzhiyun static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
190*4882a593Smuzhiyun unsigned short reg,
191*4882a593Smuzhiyun unsigned short val)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct snd_ice1712 *ice = ac97->private_data;
194*4882a593Smuzhiyun int tm;
195*4882a593Smuzhiyun unsigned char old_cmd = 0;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun for (tm = 0; tm < 0x10000; tm++) {
198*4882a593Smuzhiyun old_cmd = inb(ICEMT(ice, AC97_CMD));
199*4882a593Smuzhiyun if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
200*4882a593Smuzhiyun continue;
201*4882a593Smuzhiyun if (!(old_cmd & ICE1712_AC97_READY))
202*4882a593Smuzhiyun continue;
203*4882a593Smuzhiyun break;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun outb(reg, ICEMT(ice, AC97_INDEX));
206*4882a593Smuzhiyun outw(val, ICEMT(ice, AC97_DATA));
207*4882a593Smuzhiyun old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
208*4882a593Smuzhiyun outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
209*4882a593Smuzhiyun for (tm = 0; tm < 0x10000; tm++)
210*4882a593Smuzhiyun if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
211*4882a593Smuzhiyun break;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun
snd_ice1712_pro_ac97_read(struct snd_ac97 * ac97,unsigned short reg)215*4882a593Smuzhiyun static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
216*4882a593Smuzhiyun unsigned short reg)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun struct snd_ice1712 *ice = ac97->private_data;
219*4882a593Smuzhiyun int tm;
220*4882a593Smuzhiyun unsigned char old_cmd = 0;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun for (tm = 0; tm < 0x10000; tm++) {
223*4882a593Smuzhiyun old_cmd = inb(ICEMT(ice, AC97_CMD));
224*4882a593Smuzhiyun if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
225*4882a593Smuzhiyun continue;
226*4882a593Smuzhiyun if (!(old_cmd & ICE1712_AC97_READY))
227*4882a593Smuzhiyun continue;
228*4882a593Smuzhiyun break;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun outb(reg, ICEMT(ice, AC97_INDEX));
231*4882a593Smuzhiyun outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
232*4882a593Smuzhiyun for (tm = 0; tm < 0x10000; tm++)
233*4882a593Smuzhiyun if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
234*4882a593Smuzhiyun break;
235*4882a593Smuzhiyun if (tm >= 0x10000) /* timeout */
236*4882a593Smuzhiyun return ~0;
237*4882a593Smuzhiyun return inw(ICEMT(ice, AC97_DATA));
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun /*
241*4882a593Smuzhiyun * consumer ac97 digital mix
242*4882a593Smuzhiyun */
243*4882a593Smuzhiyun #define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
244*4882a593Smuzhiyun
snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)245*4882a593Smuzhiyun static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
250*4882a593Smuzhiyun return 0;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)253*4882a593Smuzhiyun static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
256*4882a593Smuzhiyun unsigned char val, nval;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
259*4882a593Smuzhiyun val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
260*4882a593Smuzhiyun nval = val & ~ICE1712_ROUTE_AC97;
261*4882a593Smuzhiyun if (ucontrol->value.integer.value[0])
262*4882a593Smuzhiyun nval |= ICE1712_ROUTE_AC97;
263*4882a593Smuzhiyun outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
264*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
265*4882a593Smuzhiyun return val != nval;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 = {
269*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
270*4882a593Smuzhiyun .name = "Digital Mixer To AC97",
271*4882a593Smuzhiyun .info = snd_ice1712_digmix_route_ac97_info,
272*4882a593Smuzhiyun .get = snd_ice1712_digmix_route_ac97_get,
273*4882a593Smuzhiyun .put = snd_ice1712_digmix_route_ac97_put,
274*4882a593Smuzhiyun };
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun /*
278*4882a593Smuzhiyun * gpio operations
279*4882a593Smuzhiyun */
snd_ice1712_set_gpio_dir(struct snd_ice1712 * ice,unsigned int data)280*4882a593Smuzhiyun static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
283*4882a593Smuzhiyun inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
snd_ice1712_get_gpio_dir(struct snd_ice1712 * ice)286*4882a593Smuzhiyun static unsigned int snd_ice1712_get_gpio_dir(struct snd_ice1712 *ice)
287*4882a593Smuzhiyun {
288*4882a593Smuzhiyun return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION);
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
snd_ice1712_get_gpio_mask(struct snd_ice1712 * ice)291*4882a593Smuzhiyun static unsigned int snd_ice1712_get_gpio_mask(struct snd_ice1712 *ice)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun return snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
snd_ice1712_set_gpio_mask(struct snd_ice1712 * ice,unsigned int data)296*4882a593Smuzhiyun static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
299*4882a593Smuzhiyun inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
snd_ice1712_get_gpio_data(struct snd_ice1712 * ice)302*4882a593Smuzhiyun static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
snd_ice1712_set_gpio_data(struct snd_ice1712 * ice,unsigned int val)307*4882a593Smuzhiyun static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
310*4882a593Smuzhiyun inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun /*
314*4882a593Smuzhiyun *
315*4882a593Smuzhiyun * CS8427 interface
316*4882a593Smuzhiyun *
317*4882a593Smuzhiyun */
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun /*
320*4882a593Smuzhiyun * change the input clock selection
321*4882a593Smuzhiyun * spdif_clock = 1 - IEC958 input, 0 - Envy24
322*4882a593Smuzhiyun */
snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 * ice,int spdif_clock)323*4882a593Smuzhiyun static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
326*4882a593Smuzhiyun unsigned char val, nval;
327*4882a593Smuzhiyun int res = 0;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun snd_i2c_lock(ice->i2c);
330*4882a593Smuzhiyun if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
331*4882a593Smuzhiyun snd_i2c_unlock(ice->i2c);
332*4882a593Smuzhiyun return -EIO;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
335*4882a593Smuzhiyun snd_i2c_unlock(ice->i2c);
336*4882a593Smuzhiyun return -EIO;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun nval = val & 0xf0;
339*4882a593Smuzhiyun if (spdif_clock)
340*4882a593Smuzhiyun nval |= 0x01;
341*4882a593Smuzhiyun else
342*4882a593Smuzhiyun nval |= 0x04;
343*4882a593Smuzhiyun if (val != nval) {
344*4882a593Smuzhiyun reg[1] = nval;
345*4882a593Smuzhiyun if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
346*4882a593Smuzhiyun res = -EIO;
347*4882a593Smuzhiyun } else {
348*4882a593Smuzhiyun res++;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun snd_i2c_unlock(ice->i2c);
352*4882a593Smuzhiyun return res;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun /*
356*4882a593Smuzhiyun * spdif callbacks
357*4882a593Smuzhiyun */
open_cs8427(struct snd_ice1712 * ice,struct snd_pcm_substream * substream)358*4882a593Smuzhiyun static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
359*4882a593Smuzhiyun {
360*4882a593Smuzhiyun snd_cs8427_iec958_active(ice->cs8427, 1);
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
close_cs8427(struct snd_ice1712 * ice,struct snd_pcm_substream * substream)363*4882a593Smuzhiyun static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun snd_cs8427_iec958_active(ice->cs8427, 0);
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun
setup_cs8427(struct snd_ice1712 * ice,int rate)368*4882a593Smuzhiyun static void setup_cs8427(struct snd_ice1712 *ice, int rate)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun snd_cs8427_iec958_pcm(ice->cs8427, rate);
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun /*
374*4882a593Smuzhiyun * create and initialize callbacks for cs8427 interface
375*4882a593Smuzhiyun */
snd_ice1712_init_cs8427(struct snd_ice1712 * ice,int addr)376*4882a593Smuzhiyun int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun int err;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun err = snd_cs8427_create(ice->i2c, addr,
381*4882a593Smuzhiyun (ice->cs8427_timeout * HZ) / 1000, &ice->cs8427);
382*4882a593Smuzhiyun if (err < 0) {
383*4882a593Smuzhiyun dev_err(ice->card->dev, "CS8427 initialization failed\n");
384*4882a593Smuzhiyun return err;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun ice->spdif.ops.open = open_cs8427;
387*4882a593Smuzhiyun ice->spdif.ops.close = close_cs8427;
388*4882a593Smuzhiyun ice->spdif.ops.setup_rate = setup_cs8427;
389*4882a593Smuzhiyun return 0;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
snd_ice1712_set_input_clock_source(struct snd_ice1712 * ice,int spdif_is_master)392*4882a593Smuzhiyun static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun /* change CS8427 clock source too */
395*4882a593Smuzhiyun if (ice->cs8427)
396*4882a593Smuzhiyun snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
397*4882a593Smuzhiyun /* notify ak4524 chip as well */
398*4882a593Smuzhiyun if (spdif_is_master) {
399*4882a593Smuzhiyun unsigned int i;
400*4882a593Smuzhiyun for (i = 0; i < ice->akm_codecs; i++) {
401*4882a593Smuzhiyun if (ice->akm[i].ops.set_rate_val)
402*4882a593Smuzhiyun ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /*
408*4882a593Smuzhiyun * Interrupt handler
409*4882a593Smuzhiyun */
410*4882a593Smuzhiyun
snd_ice1712_interrupt(int irq,void * dev_id)411*4882a593Smuzhiyun static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun struct snd_ice1712 *ice = dev_id;
414*4882a593Smuzhiyun unsigned char status;
415*4882a593Smuzhiyun int handled = 0;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun while (1) {
418*4882a593Smuzhiyun status = inb(ICEREG(ice, IRQSTAT));
419*4882a593Smuzhiyun if (status == 0)
420*4882a593Smuzhiyun break;
421*4882a593Smuzhiyun handled = 1;
422*4882a593Smuzhiyun if (status & ICE1712_IRQ_MPU1) {
423*4882a593Smuzhiyun if (ice->rmidi[0])
424*4882a593Smuzhiyun snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
425*4882a593Smuzhiyun outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
426*4882a593Smuzhiyun status &= ~ICE1712_IRQ_MPU1;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun if (status & ICE1712_IRQ_TIMER)
429*4882a593Smuzhiyun outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
430*4882a593Smuzhiyun if (status & ICE1712_IRQ_MPU2) {
431*4882a593Smuzhiyun if (ice->rmidi[1])
432*4882a593Smuzhiyun snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
433*4882a593Smuzhiyun outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
434*4882a593Smuzhiyun status &= ~ICE1712_IRQ_MPU2;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun if (status & ICE1712_IRQ_PROPCM) {
437*4882a593Smuzhiyun unsigned char mtstat = inb(ICEMT(ice, IRQ));
438*4882a593Smuzhiyun if (mtstat & ICE1712_MULTI_PBKSTATUS) {
439*4882a593Smuzhiyun if (ice->playback_pro_substream)
440*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->playback_pro_substream);
441*4882a593Smuzhiyun outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun if (mtstat & ICE1712_MULTI_CAPSTATUS) {
444*4882a593Smuzhiyun if (ice->capture_pro_substream)
445*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->capture_pro_substream);
446*4882a593Smuzhiyun outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun if (status & ICE1712_IRQ_FM)
450*4882a593Smuzhiyun outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
451*4882a593Smuzhiyun if (status & ICE1712_IRQ_PBKDS) {
452*4882a593Smuzhiyun u32 idx;
453*4882a593Smuzhiyun u16 pbkstatus;
454*4882a593Smuzhiyun struct snd_pcm_substream *substream;
455*4882a593Smuzhiyun pbkstatus = inw(ICEDS(ice, INTSTAT));
456*4882a593Smuzhiyun /* dev_dbg(ice->card->dev, "pbkstatus = 0x%x\n", pbkstatus); */
457*4882a593Smuzhiyun for (idx = 0; idx < 6; idx++) {
458*4882a593Smuzhiyun if ((pbkstatus & (3 << (idx * 2))) == 0)
459*4882a593Smuzhiyun continue;
460*4882a593Smuzhiyun substream = ice->playback_con_substream_ds[idx];
461*4882a593Smuzhiyun if (substream != NULL)
462*4882a593Smuzhiyun snd_pcm_period_elapsed(substream);
463*4882a593Smuzhiyun outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun if (status & ICE1712_IRQ_CONCAP) {
468*4882a593Smuzhiyun if (ice->capture_con_substream)
469*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->capture_con_substream);
470*4882a593Smuzhiyun outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun if (status & ICE1712_IRQ_CONPBK) {
473*4882a593Smuzhiyun if (ice->playback_con_substream)
474*4882a593Smuzhiyun snd_pcm_period_elapsed(ice->playback_con_substream);
475*4882a593Smuzhiyun outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
476*4882a593Smuzhiyun }
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun return IRQ_RETVAL(handled);
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun /*
483*4882a593Smuzhiyun * PCM part - consumer I/O
484*4882a593Smuzhiyun */
485*4882a593Smuzhiyun
snd_ice1712_playback_trigger(struct snd_pcm_substream * substream,int cmd)486*4882a593Smuzhiyun static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
487*4882a593Smuzhiyun int cmd)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
490*4882a593Smuzhiyun int result = 0;
491*4882a593Smuzhiyun u32 tmp;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun spin_lock(&ice->reg_lock);
494*4882a593Smuzhiyun tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
495*4882a593Smuzhiyun if (cmd == SNDRV_PCM_TRIGGER_START) {
496*4882a593Smuzhiyun tmp |= 1;
497*4882a593Smuzhiyun } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
498*4882a593Smuzhiyun tmp &= ~1;
499*4882a593Smuzhiyun } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
500*4882a593Smuzhiyun tmp |= 2;
501*4882a593Smuzhiyun } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
502*4882a593Smuzhiyun tmp &= ~2;
503*4882a593Smuzhiyun } else {
504*4882a593Smuzhiyun result = -EINVAL;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
507*4882a593Smuzhiyun spin_unlock(&ice->reg_lock);
508*4882a593Smuzhiyun return result;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
snd_ice1712_playback_ds_trigger(struct snd_pcm_substream * substream,int cmd)511*4882a593Smuzhiyun static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
512*4882a593Smuzhiyun int cmd)
513*4882a593Smuzhiyun {
514*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
515*4882a593Smuzhiyun int result = 0;
516*4882a593Smuzhiyun u32 tmp;
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun spin_lock(&ice->reg_lock);
519*4882a593Smuzhiyun tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
520*4882a593Smuzhiyun if (cmd == SNDRV_PCM_TRIGGER_START) {
521*4882a593Smuzhiyun tmp |= 1;
522*4882a593Smuzhiyun } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
523*4882a593Smuzhiyun tmp &= ~1;
524*4882a593Smuzhiyun } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
525*4882a593Smuzhiyun tmp |= 2;
526*4882a593Smuzhiyun } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
527*4882a593Smuzhiyun tmp &= ~2;
528*4882a593Smuzhiyun } else {
529*4882a593Smuzhiyun result = -EINVAL;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
532*4882a593Smuzhiyun spin_unlock(&ice->reg_lock);
533*4882a593Smuzhiyun return result;
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun
snd_ice1712_capture_trigger(struct snd_pcm_substream * substream,int cmd)536*4882a593Smuzhiyun static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
537*4882a593Smuzhiyun int cmd)
538*4882a593Smuzhiyun {
539*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
540*4882a593Smuzhiyun int result = 0;
541*4882a593Smuzhiyun u8 tmp;
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun spin_lock(&ice->reg_lock);
544*4882a593Smuzhiyun tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
545*4882a593Smuzhiyun if (cmd == SNDRV_PCM_TRIGGER_START) {
546*4882a593Smuzhiyun tmp |= 1;
547*4882a593Smuzhiyun } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
548*4882a593Smuzhiyun tmp &= ~1;
549*4882a593Smuzhiyun } else {
550*4882a593Smuzhiyun result = -EINVAL;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
553*4882a593Smuzhiyun spin_unlock(&ice->reg_lock);
554*4882a593Smuzhiyun return result;
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun
snd_ice1712_playback_prepare(struct snd_pcm_substream * substream)557*4882a593Smuzhiyun static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
558*4882a593Smuzhiyun {
559*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
560*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
561*4882a593Smuzhiyun u32 period_size, buf_size, rate, tmp;
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
564*4882a593Smuzhiyun buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
565*4882a593Smuzhiyun tmp = 0x0000;
566*4882a593Smuzhiyun if (snd_pcm_format_width(runtime->format) == 16)
567*4882a593Smuzhiyun tmp |= 0x10;
568*4882a593Smuzhiyun if (runtime->channels == 2)
569*4882a593Smuzhiyun tmp |= 0x08;
570*4882a593Smuzhiyun rate = (runtime->rate * 8192) / 375;
571*4882a593Smuzhiyun if (rate > 0x000fffff)
572*4882a593Smuzhiyun rate = 0x000fffff;
573*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
574*4882a593Smuzhiyun outb(0, ice->ddma_port + 15);
575*4882a593Smuzhiyun outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
576*4882a593Smuzhiyun outl(runtime->dma_addr, ice->ddma_port + 0);
577*4882a593Smuzhiyun outw(buf_size, ice->ddma_port + 4);
578*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
579*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
580*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
581*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
582*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
583*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
584*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
585*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
586*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
587*4882a593Smuzhiyun return 0;
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun
snd_ice1712_playback_ds_prepare(struct snd_pcm_substream * substream)590*4882a593Smuzhiyun static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
591*4882a593Smuzhiyun {
592*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
593*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
594*4882a593Smuzhiyun u32 period_size, rate, tmp, chn;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun period_size = snd_pcm_lib_period_bytes(substream) - 1;
597*4882a593Smuzhiyun tmp = 0x0064;
598*4882a593Smuzhiyun if (snd_pcm_format_width(runtime->format) == 16)
599*4882a593Smuzhiyun tmp &= ~0x04;
600*4882a593Smuzhiyun if (runtime->channels == 2)
601*4882a593Smuzhiyun tmp |= 0x08;
602*4882a593Smuzhiyun rate = (runtime->rate * 8192) / 375;
603*4882a593Smuzhiyun if (rate > 0x000fffff)
604*4882a593Smuzhiyun rate = 0x000fffff;
605*4882a593Smuzhiyun ice->playback_con_active_buf[substream->number] = 0;
606*4882a593Smuzhiyun ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
607*4882a593Smuzhiyun chn = substream->number * 2;
608*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
609*4882a593Smuzhiyun snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
610*4882a593Smuzhiyun snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
611*4882a593Smuzhiyun snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
612*4882a593Smuzhiyun snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
613*4882a593Smuzhiyun snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
614*4882a593Smuzhiyun snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
615*4882a593Smuzhiyun snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
616*4882a593Smuzhiyun if (runtime->channels == 2) {
617*4882a593Smuzhiyun snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
618*4882a593Smuzhiyun snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
621*4882a593Smuzhiyun return 0;
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun
snd_ice1712_capture_prepare(struct snd_pcm_substream * substream)624*4882a593Smuzhiyun static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
625*4882a593Smuzhiyun {
626*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
627*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
628*4882a593Smuzhiyun u32 period_size, buf_size;
629*4882a593Smuzhiyun u8 tmp;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
632*4882a593Smuzhiyun buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
633*4882a593Smuzhiyun tmp = 0x06;
634*4882a593Smuzhiyun if (snd_pcm_format_width(runtime->format) == 16)
635*4882a593Smuzhiyun tmp &= ~0x04;
636*4882a593Smuzhiyun if (runtime->channels == 2)
637*4882a593Smuzhiyun tmp &= ~0x02;
638*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
639*4882a593Smuzhiyun outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
640*4882a593Smuzhiyun outw(buf_size, ICEREG(ice, CONCAP_COUNT));
641*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
642*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
643*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
644*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
645*4882a593Smuzhiyun snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
646*4882a593Smuzhiyun return 0;
647*4882a593Smuzhiyun }
648*4882a593Smuzhiyun
snd_ice1712_playback_pointer(struct snd_pcm_substream * substream)649*4882a593Smuzhiyun static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
652*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
653*4882a593Smuzhiyun size_t ptr;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
656*4882a593Smuzhiyun return 0;
657*4882a593Smuzhiyun ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
658*4882a593Smuzhiyun ptr = bytes_to_frames(substream->runtime, ptr);
659*4882a593Smuzhiyun if (ptr == runtime->buffer_size)
660*4882a593Smuzhiyun ptr = 0;
661*4882a593Smuzhiyun return ptr;
662*4882a593Smuzhiyun }
663*4882a593Smuzhiyun
snd_ice1712_playback_ds_pointer(struct snd_pcm_substream * substream)664*4882a593Smuzhiyun static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
665*4882a593Smuzhiyun {
666*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
667*4882a593Smuzhiyun u8 addr;
668*4882a593Smuzhiyun size_t ptr;
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
671*4882a593Smuzhiyun return 0;
672*4882a593Smuzhiyun if (ice->playback_con_active_buf[substream->number])
673*4882a593Smuzhiyun addr = ICE1712_DSC_ADDR1;
674*4882a593Smuzhiyun else
675*4882a593Smuzhiyun addr = ICE1712_DSC_ADDR0;
676*4882a593Smuzhiyun ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
677*4882a593Smuzhiyun ice->playback_con_virt_addr[substream->number];
678*4882a593Smuzhiyun ptr = bytes_to_frames(substream->runtime, ptr);
679*4882a593Smuzhiyun if (ptr == substream->runtime->buffer_size)
680*4882a593Smuzhiyun ptr = 0;
681*4882a593Smuzhiyun return ptr;
682*4882a593Smuzhiyun }
683*4882a593Smuzhiyun
snd_ice1712_capture_pointer(struct snd_pcm_substream * substream)684*4882a593Smuzhiyun static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
685*4882a593Smuzhiyun {
686*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
687*4882a593Smuzhiyun size_t ptr;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
690*4882a593Smuzhiyun return 0;
691*4882a593Smuzhiyun ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
692*4882a593Smuzhiyun ptr = bytes_to_frames(substream->runtime, ptr);
693*4882a593Smuzhiyun if (ptr == substream->runtime->buffer_size)
694*4882a593Smuzhiyun ptr = 0;
695*4882a593Smuzhiyun return ptr;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_ice1712_playback = {
699*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
700*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
701*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
702*4882a593Smuzhiyun SNDRV_PCM_INFO_PAUSE),
703*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
704*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
705*4882a593Smuzhiyun .rate_min = 4000,
706*4882a593Smuzhiyun .rate_max = 48000,
707*4882a593Smuzhiyun .channels_min = 1,
708*4882a593Smuzhiyun .channels_max = 2,
709*4882a593Smuzhiyun .buffer_bytes_max = (64*1024),
710*4882a593Smuzhiyun .period_bytes_min = 64,
711*4882a593Smuzhiyun .period_bytes_max = (64*1024),
712*4882a593Smuzhiyun .periods_min = 1,
713*4882a593Smuzhiyun .periods_max = 1024,
714*4882a593Smuzhiyun .fifo_size = 0,
715*4882a593Smuzhiyun };
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_ice1712_playback_ds = {
718*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
719*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
720*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
721*4882a593Smuzhiyun SNDRV_PCM_INFO_PAUSE),
722*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
723*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
724*4882a593Smuzhiyun .rate_min = 4000,
725*4882a593Smuzhiyun .rate_max = 48000,
726*4882a593Smuzhiyun .channels_min = 1,
727*4882a593Smuzhiyun .channels_max = 2,
728*4882a593Smuzhiyun .buffer_bytes_max = (128*1024),
729*4882a593Smuzhiyun .period_bytes_min = 64,
730*4882a593Smuzhiyun .period_bytes_max = (128*1024),
731*4882a593Smuzhiyun .periods_min = 2,
732*4882a593Smuzhiyun .periods_max = 2,
733*4882a593Smuzhiyun .fifo_size = 0,
734*4882a593Smuzhiyun };
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_ice1712_capture = {
737*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
738*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
739*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID),
740*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
741*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
742*4882a593Smuzhiyun .rate_min = 4000,
743*4882a593Smuzhiyun .rate_max = 48000,
744*4882a593Smuzhiyun .channels_min = 1,
745*4882a593Smuzhiyun .channels_max = 2,
746*4882a593Smuzhiyun .buffer_bytes_max = (64*1024),
747*4882a593Smuzhiyun .period_bytes_min = 64,
748*4882a593Smuzhiyun .period_bytes_max = (64*1024),
749*4882a593Smuzhiyun .periods_min = 1,
750*4882a593Smuzhiyun .periods_max = 1024,
751*4882a593Smuzhiyun .fifo_size = 0,
752*4882a593Smuzhiyun };
753*4882a593Smuzhiyun
snd_ice1712_playback_open(struct snd_pcm_substream * substream)754*4882a593Smuzhiyun static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
755*4882a593Smuzhiyun {
756*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
757*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun ice->playback_con_substream = substream;
760*4882a593Smuzhiyun runtime->hw = snd_ice1712_playback;
761*4882a593Smuzhiyun return 0;
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun
snd_ice1712_playback_ds_open(struct snd_pcm_substream * substream)764*4882a593Smuzhiyun static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
767*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
768*4882a593Smuzhiyun u32 tmp;
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun ice->playback_con_substream_ds[substream->number] = substream;
771*4882a593Smuzhiyun runtime->hw = snd_ice1712_playback_ds;
772*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
773*4882a593Smuzhiyun tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
774*4882a593Smuzhiyun outw(tmp, ICEDS(ice, INTMASK));
775*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
776*4882a593Smuzhiyun return 0;
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun
snd_ice1712_capture_open(struct snd_pcm_substream * substream)779*4882a593Smuzhiyun static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
780*4882a593Smuzhiyun {
781*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
782*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun ice->capture_con_substream = substream;
785*4882a593Smuzhiyun runtime->hw = snd_ice1712_capture;
786*4882a593Smuzhiyun runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
787*4882a593Smuzhiyun if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
788*4882a593Smuzhiyun runtime->hw.rate_min = 48000;
789*4882a593Smuzhiyun return 0;
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun
snd_ice1712_playback_close(struct snd_pcm_substream * substream)792*4882a593Smuzhiyun static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
793*4882a593Smuzhiyun {
794*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun ice->playback_con_substream = NULL;
797*4882a593Smuzhiyun return 0;
798*4882a593Smuzhiyun }
799*4882a593Smuzhiyun
snd_ice1712_playback_ds_close(struct snd_pcm_substream * substream)800*4882a593Smuzhiyun static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
801*4882a593Smuzhiyun {
802*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
803*4882a593Smuzhiyun u32 tmp;
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
806*4882a593Smuzhiyun tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
807*4882a593Smuzhiyun outw(tmp, ICEDS(ice, INTMASK));
808*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
809*4882a593Smuzhiyun ice->playback_con_substream_ds[substream->number] = NULL;
810*4882a593Smuzhiyun return 0;
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun
snd_ice1712_capture_close(struct snd_pcm_substream * substream)813*4882a593Smuzhiyun static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
814*4882a593Smuzhiyun {
815*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun ice->capture_con_substream = NULL;
818*4882a593Smuzhiyun return 0;
819*4882a593Smuzhiyun }
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ice1712_playback_ops = {
822*4882a593Smuzhiyun .open = snd_ice1712_playback_open,
823*4882a593Smuzhiyun .close = snd_ice1712_playback_close,
824*4882a593Smuzhiyun .prepare = snd_ice1712_playback_prepare,
825*4882a593Smuzhiyun .trigger = snd_ice1712_playback_trigger,
826*4882a593Smuzhiyun .pointer = snd_ice1712_playback_pointer,
827*4882a593Smuzhiyun };
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
830*4882a593Smuzhiyun .open = snd_ice1712_playback_ds_open,
831*4882a593Smuzhiyun .close = snd_ice1712_playback_ds_close,
832*4882a593Smuzhiyun .prepare = snd_ice1712_playback_ds_prepare,
833*4882a593Smuzhiyun .trigger = snd_ice1712_playback_ds_trigger,
834*4882a593Smuzhiyun .pointer = snd_ice1712_playback_ds_pointer,
835*4882a593Smuzhiyun };
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ice1712_capture_ops = {
838*4882a593Smuzhiyun .open = snd_ice1712_capture_open,
839*4882a593Smuzhiyun .close = snd_ice1712_capture_close,
840*4882a593Smuzhiyun .prepare = snd_ice1712_capture_prepare,
841*4882a593Smuzhiyun .trigger = snd_ice1712_capture_trigger,
842*4882a593Smuzhiyun .pointer = snd_ice1712_capture_pointer,
843*4882a593Smuzhiyun };
844*4882a593Smuzhiyun
snd_ice1712_pcm(struct snd_ice1712 * ice,int device)845*4882a593Smuzhiyun static int snd_ice1712_pcm(struct snd_ice1712 *ice, int device)
846*4882a593Smuzhiyun {
847*4882a593Smuzhiyun struct snd_pcm *pcm;
848*4882a593Smuzhiyun int err;
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
851*4882a593Smuzhiyun if (err < 0)
852*4882a593Smuzhiyun return err;
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
855*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun pcm->private_data = ice;
858*4882a593Smuzhiyun pcm->info_flags = 0;
859*4882a593Smuzhiyun strcpy(pcm->name, "ICE1712 consumer");
860*4882a593Smuzhiyun ice->pcm = pcm;
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
863*4882a593Smuzhiyun &ice->pci->dev, 64*1024, 64*1024);
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun dev_warn(ice->card->dev,
866*4882a593Smuzhiyun "Consumer PCM code does not work well at the moment --jk\n");
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun return 0;
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun
snd_ice1712_pcm_ds(struct snd_ice1712 * ice,int device)871*4882a593Smuzhiyun static int snd_ice1712_pcm_ds(struct snd_ice1712 *ice, int device)
872*4882a593Smuzhiyun {
873*4882a593Smuzhiyun struct snd_pcm *pcm;
874*4882a593Smuzhiyun int err;
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
877*4882a593Smuzhiyun if (err < 0)
878*4882a593Smuzhiyun return err;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun pcm->private_data = ice;
883*4882a593Smuzhiyun pcm->info_flags = 0;
884*4882a593Smuzhiyun strcpy(pcm->name, "ICE1712 consumer (DS)");
885*4882a593Smuzhiyun ice->pcm_ds = pcm;
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
888*4882a593Smuzhiyun &ice->pci->dev, 64*1024, 128*1024);
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun return 0;
891*4882a593Smuzhiyun }
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun /*
894*4882a593Smuzhiyun * PCM code - professional part (multitrack)
895*4882a593Smuzhiyun */
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun static const unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
898*4882a593Smuzhiyun 32000, 44100, 48000, 64000, 88200, 96000 };
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
901*4882a593Smuzhiyun .count = ARRAY_SIZE(rates),
902*4882a593Smuzhiyun .list = rates,
903*4882a593Smuzhiyun .mask = 0,
904*4882a593Smuzhiyun };
905*4882a593Smuzhiyun
snd_ice1712_pro_trigger(struct snd_pcm_substream * substream,int cmd)906*4882a593Smuzhiyun static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
907*4882a593Smuzhiyun int cmd)
908*4882a593Smuzhiyun {
909*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
910*4882a593Smuzhiyun switch (cmd) {
911*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
912*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
913*4882a593Smuzhiyun {
914*4882a593Smuzhiyun unsigned int what;
915*4882a593Smuzhiyun unsigned int old;
916*4882a593Smuzhiyun if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
917*4882a593Smuzhiyun return -EINVAL;
918*4882a593Smuzhiyun what = ICE1712_PLAYBACK_PAUSE;
919*4882a593Smuzhiyun snd_pcm_trigger_done(substream, substream);
920*4882a593Smuzhiyun spin_lock(&ice->reg_lock);
921*4882a593Smuzhiyun old = inl(ICEMT(ice, PLAYBACK_CONTROL));
922*4882a593Smuzhiyun if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
923*4882a593Smuzhiyun old |= what;
924*4882a593Smuzhiyun else
925*4882a593Smuzhiyun old &= ~what;
926*4882a593Smuzhiyun outl(old, ICEMT(ice, PLAYBACK_CONTROL));
927*4882a593Smuzhiyun spin_unlock(&ice->reg_lock);
928*4882a593Smuzhiyun break;
929*4882a593Smuzhiyun }
930*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
931*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
932*4882a593Smuzhiyun {
933*4882a593Smuzhiyun unsigned int what = 0;
934*4882a593Smuzhiyun unsigned int old;
935*4882a593Smuzhiyun struct snd_pcm_substream *s;
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun snd_pcm_group_for_each_entry(s, substream) {
938*4882a593Smuzhiyun if (s == ice->playback_pro_substream) {
939*4882a593Smuzhiyun what |= ICE1712_PLAYBACK_START;
940*4882a593Smuzhiyun snd_pcm_trigger_done(s, substream);
941*4882a593Smuzhiyun } else if (s == ice->capture_pro_substream) {
942*4882a593Smuzhiyun what |= ICE1712_CAPTURE_START_SHADOW;
943*4882a593Smuzhiyun snd_pcm_trigger_done(s, substream);
944*4882a593Smuzhiyun }
945*4882a593Smuzhiyun }
946*4882a593Smuzhiyun spin_lock(&ice->reg_lock);
947*4882a593Smuzhiyun old = inl(ICEMT(ice, PLAYBACK_CONTROL));
948*4882a593Smuzhiyun if (cmd == SNDRV_PCM_TRIGGER_START)
949*4882a593Smuzhiyun old |= what;
950*4882a593Smuzhiyun else
951*4882a593Smuzhiyun old &= ~what;
952*4882a593Smuzhiyun outl(old, ICEMT(ice, PLAYBACK_CONTROL));
953*4882a593Smuzhiyun spin_unlock(&ice->reg_lock);
954*4882a593Smuzhiyun break;
955*4882a593Smuzhiyun }
956*4882a593Smuzhiyun default:
957*4882a593Smuzhiyun return -EINVAL;
958*4882a593Smuzhiyun }
959*4882a593Smuzhiyun return 0;
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun /*
963*4882a593Smuzhiyun */
snd_ice1712_set_pro_rate(struct snd_ice1712 * ice,unsigned int rate,int force)964*4882a593Smuzhiyun static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
965*4882a593Smuzhiyun {
966*4882a593Smuzhiyun unsigned long flags;
967*4882a593Smuzhiyun unsigned char val, old;
968*4882a593Smuzhiyun unsigned int i;
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun switch (rate) {
971*4882a593Smuzhiyun case 8000: val = 6; break;
972*4882a593Smuzhiyun case 9600: val = 3; break;
973*4882a593Smuzhiyun case 11025: val = 10; break;
974*4882a593Smuzhiyun case 12000: val = 2; break;
975*4882a593Smuzhiyun case 16000: val = 5; break;
976*4882a593Smuzhiyun case 22050: val = 9; break;
977*4882a593Smuzhiyun case 24000: val = 1; break;
978*4882a593Smuzhiyun case 32000: val = 4; break;
979*4882a593Smuzhiyun case 44100: val = 8; break;
980*4882a593Smuzhiyun case 48000: val = 0; break;
981*4882a593Smuzhiyun case 64000: val = 15; break;
982*4882a593Smuzhiyun case 88200: val = 11; break;
983*4882a593Smuzhiyun case 96000: val = 7; break;
984*4882a593Smuzhiyun default:
985*4882a593Smuzhiyun snd_BUG();
986*4882a593Smuzhiyun val = 0;
987*4882a593Smuzhiyun rate = 48000;
988*4882a593Smuzhiyun break;
989*4882a593Smuzhiyun }
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun spin_lock_irqsave(&ice->reg_lock, flags);
992*4882a593Smuzhiyun if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
993*4882a593Smuzhiyun ICE1712_PLAYBACK_PAUSE|
994*4882a593Smuzhiyun ICE1712_PLAYBACK_START)) {
995*4882a593Smuzhiyun __out:
996*4882a593Smuzhiyun spin_unlock_irqrestore(&ice->reg_lock, flags);
997*4882a593Smuzhiyun return;
998*4882a593Smuzhiyun }
999*4882a593Smuzhiyun if (!force && is_pro_rate_locked(ice))
1000*4882a593Smuzhiyun goto __out;
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun old = inb(ICEMT(ice, RATE));
1003*4882a593Smuzhiyun if (!force && old == val)
1004*4882a593Smuzhiyun goto __out;
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun ice->cur_rate = rate;
1007*4882a593Smuzhiyun outb(val, ICEMT(ice, RATE));
1008*4882a593Smuzhiyun spin_unlock_irqrestore(&ice->reg_lock, flags);
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun if (ice->gpio.set_pro_rate)
1011*4882a593Smuzhiyun ice->gpio.set_pro_rate(ice, rate);
1012*4882a593Smuzhiyun for (i = 0; i < ice->akm_codecs; i++) {
1013*4882a593Smuzhiyun if (ice->akm[i].ops.set_rate_val)
1014*4882a593Smuzhiyun ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun if (ice->spdif.ops.setup_rate)
1017*4882a593Smuzhiyun ice->spdif.ops.setup_rate(ice, rate);
1018*4882a593Smuzhiyun }
1019*4882a593Smuzhiyun
snd_ice1712_playback_pro_prepare(struct snd_pcm_substream * substream)1020*4882a593Smuzhiyun static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
1021*4882a593Smuzhiyun {
1022*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
1025*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1026*4882a593Smuzhiyun outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
1027*4882a593Smuzhiyun outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
1028*4882a593Smuzhiyun outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
1029*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun return 0;
1032*4882a593Smuzhiyun }
1033*4882a593Smuzhiyun
snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)1034*4882a593Smuzhiyun static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
1035*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params)
1036*4882a593Smuzhiyun {
1037*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
1040*4882a593Smuzhiyun return 0;
1041*4882a593Smuzhiyun }
1042*4882a593Smuzhiyun
snd_ice1712_capture_pro_prepare(struct snd_pcm_substream * substream)1043*4882a593Smuzhiyun static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
1044*4882a593Smuzhiyun {
1045*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
1048*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1049*4882a593Smuzhiyun outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
1050*4882a593Smuzhiyun outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
1051*4882a593Smuzhiyun outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
1052*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1053*4882a593Smuzhiyun return 0;
1054*4882a593Smuzhiyun }
1055*4882a593Smuzhiyun
snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)1056*4882a593Smuzhiyun static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
1057*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params)
1058*4882a593Smuzhiyun {
1059*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
1062*4882a593Smuzhiyun return 0;
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun
snd_ice1712_playback_pro_pointer(struct snd_pcm_substream * substream)1065*4882a593Smuzhiyun static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
1066*4882a593Smuzhiyun {
1067*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1068*4882a593Smuzhiyun size_t ptr;
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
1071*4882a593Smuzhiyun return 0;
1072*4882a593Smuzhiyun ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
1073*4882a593Smuzhiyun ptr = bytes_to_frames(substream->runtime, ptr);
1074*4882a593Smuzhiyun if (ptr == substream->runtime->buffer_size)
1075*4882a593Smuzhiyun ptr = 0;
1076*4882a593Smuzhiyun return ptr;
1077*4882a593Smuzhiyun }
1078*4882a593Smuzhiyun
snd_ice1712_capture_pro_pointer(struct snd_pcm_substream * substream)1079*4882a593Smuzhiyun static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
1080*4882a593Smuzhiyun {
1081*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1082*4882a593Smuzhiyun size_t ptr;
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
1085*4882a593Smuzhiyun return 0;
1086*4882a593Smuzhiyun ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
1087*4882a593Smuzhiyun ptr = bytes_to_frames(substream->runtime, ptr);
1088*4882a593Smuzhiyun if (ptr == substream->runtime->buffer_size)
1089*4882a593Smuzhiyun ptr = 0;
1090*4882a593Smuzhiyun return ptr;
1091*4882a593Smuzhiyun }
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_ice1712_playback_pro = {
1094*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1095*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
1096*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
1097*4882a593Smuzhiyun SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1098*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S32_LE,
1099*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
1100*4882a593Smuzhiyun .rate_min = 4000,
1101*4882a593Smuzhiyun .rate_max = 96000,
1102*4882a593Smuzhiyun .channels_min = 10,
1103*4882a593Smuzhiyun .channels_max = 10,
1104*4882a593Smuzhiyun .buffer_bytes_max = (256*1024),
1105*4882a593Smuzhiyun .period_bytes_min = 10 * 4 * 2,
1106*4882a593Smuzhiyun .period_bytes_max = 131040,
1107*4882a593Smuzhiyun .periods_min = 1,
1108*4882a593Smuzhiyun .periods_max = 1024,
1109*4882a593Smuzhiyun .fifo_size = 0,
1110*4882a593Smuzhiyun };
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_ice1712_capture_pro = {
1113*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1114*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
1115*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID |
1116*4882a593Smuzhiyun SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1117*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S32_LE,
1118*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
1119*4882a593Smuzhiyun .rate_min = 4000,
1120*4882a593Smuzhiyun .rate_max = 96000,
1121*4882a593Smuzhiyun .channels_min = 12,
1122*4882a593Smuzhiyun .channels_max = 12,
1123*4882a593Smuzhiyun .buffer_bytes_max = (256*1024),
1124*4882a593Smuzhiyun .period_bytes_min = 12 * 4 * 2,
1125*4882a593Smuzhiyun .period_bytes_max = 131040,
1126*4882a593Smuzhiyun .periods_min = 1,
1127*4882a593Smuzhiyun .periods_max = 1024,
1128*4882a593Smuzhiyun .fifo_size = 0,
1129*4882a593Smuzhiyun };
1130*4882a593Smuzhiyun
snd_ice1712_playback_pro_open(struct snd_pcm_substream * substream)1131*4882a593Smuzhiyun static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
1132*4882a593Smuzhiyun {
1133*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
1134*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun ice->playback_pro_substream = substream;
1137*4882a593Smuzhiyun runtime->hw = snd_ice1712_playback_pro;
1138*4882a593Smuzhiyun snd_pcm_set_sync(substream);
1139*4882a593Smuzhiyun snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1140*4882a593Smuzhiyun snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1141*4882a593Smuzhiyun if (is_pro_rate_locked(ice)) {
1142*4882a593Smuzhiyun runtime->hw.rate_min = PRO_RATE_DEFAULT;
1143*4882a593Smuzhiyun runtime->hw.rate_max = PRO_RATE_DEFAULT;
1144*4882a593Smuzhiyun }
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun if (ice->spdif.ops.open)
1147*4882a593Smuzhiyun ice->spdif.ops.open(ice, substream);
1148*4882a593Smuzhiyun
1149*4882a593Smuzhiyun return 0;
1150*4882a593Smuzhiyun }
1151*4882a593Smuzhiyun
snd_ice1712_capture_pro_open(struct snd_pcm_substream * substream)1152*4882a593Smuzhiyun static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
1153*4882a593Smuzhiyun {
1154*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1155*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun ice->capture_pro_substream = substream;
1158*4882a593Smuzhiyun runtime->hw = snd_ice1712_capture_pro;
1159*4882a593Smuzhiyun snd_pcm_set_sync(substream);
1160*4882a593Smuzhiyun snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1161*4882a593Smuzhiyun snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1162*4882a593Smuzhiyun if (is_pro_rate_locked(ice)) {
1163*4882a593Smuzhiyun runtime->hw.rate_min = PRO_RATE_DEFAULT;
1164*4882a593Smuzhiyun runtime->hw.rate_max = PRO_RATE_DEFAULT;
1165*4882a593Smuzhiyun }
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun return 0;
1168*4882a593Smuzhiyun }
1169*4882a593Smuzhiyun
snd_ice1712_playback_pro_close(struct snd_pcm_substream * substream)1170*4882a593Smuzhiyun static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
1171*4882a593Smuzhiyun {
1172*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun if (PRO_RATE_RESET)
1175*4882a593Smuzhiyun snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
1176*4882a593Smuzhiyun ice->playback_pro_substream = NULL;
1177*4882a593Smuzhiyun if (ice->spdif.ops.close)
1178*4882a593Smuzhiyun ice->spdif.ops.close(ice, substream);
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun return 0;
1181*4882a593Smuzhiyun }
1182*4882a593Smuzhiyun
snd_ice1712_capture_pro_close(struct snd_pcm_substream * substream)1183*4882a593Smuzhiyun static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
1184*4882a593Smuzhiyun {
1185*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun if (PRO_RATE_RESET)
1188*4882a593Smuzhiyun snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
1189*4882a593Smuzhiyun ice->capture_pro_substream = NULL;
1190*4882a593Smuzhiyun return 0;
1191*4882a593Smuzhiyun }
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
1194*4882a593Smuzhiyun .open = snd_ice1712_playback_pro_open,
1195*4882a593Smuzhiyun .close = snd_ice1712_playback_pro_close,
1196*4882a593Smuzhiyun .hw_params = snd_ice1712_playback_pro_hw_params,
1197*4882a593Smuzhiyun .prepare = snd_ice1712_playback_pro_prepare,
1198*4882a593Smuzhiyun .trigger = snd_ice1712_pro_trigger,
1199*4882a593Smuzhiyun .pointer = snd_ice1712_playback_pro_pointer,
1200*4882a593Smuzhiyun };
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
1203*4882a593Smuzhiyun .open = snd_ice1712_capture_pro_open,
1204*4882a593Smuzhiyun .close = snd_ice1712_capture_pro_close,
1205*4882a593Smuzhiyun .hw_params = snd_ice1712_capture_pro_hw_params,
1206*4882a593Smuzhiyun .prepare = snd_ice1712_capture_pro_prepare,
1207*4882a593Smuzhiyun .trigger = snd_ice1712_pro_trigger,
1208*4882a593Smuzhiyun .pointer = snd_ice1712_capture_pro_pointer,
1209*4882a593Smuzhiyun };
1210*4882a593Smuzhiyun
snd_ice1712_pcm_profi(struct snd_ice1712 * ice,int device)1211*4882a593Smuzhiyun static int snd_ice1712_pcm_profi(struct snd_ice1712 *ice, int device)
1212*4882a593Smuzhiyun {
1213*4882a593Smuzhiyun struct snd_pcm *pcm;
1214*4882a593Smuzhiyun int err;
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
1217*4882a593Smuzhiyun if (err < 0)
1218*4882a593Smuzhiyun return err;
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
1221*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun pcm->private_data = ice;
1224*4882a593Smuzhiyun pcm->info_flags = 0;
1225*4882a593Smuzhiyun strcpy(pcm->name, "ICE1712 multi");
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1228*4882a593Smuzhiyun &ice->pci->dev, 256*1024, 256*1024);
1229*4882a593Smuzhiyun
1230*4882a593Smuzhiyun ice->pcm_pro = pcm;
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun if (ice->cs8427) {
1233*4882a593Smuzhiyun /* assign channels to iec958 */
1234*4882a593Smuzhiyun err = snd_cs8427_iec958_build(ice->cs8427,
1235*4882a593Smuzhiyun pcm->streams[0].substream,
1236*4882a593Smuzhiyun pcm->streams[1].substream);
1237*4882a593Smuzhiyun if (err < 0)
1238*4882a593Smuzhiyun return err;
1239*4882a593Smuzhiyun }
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun return snd_ice1712_build_pro_mixer(ice);
1242*4882a593Smuzhiyun }
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun /*
1245*4882a593Smuzhiyun * Mixer section
1246*4882a593Smuzhiyun */
1247*4882a593Smuzhiyun
snd_ice1712_update_volume(struct snd_ice1712 * ice,int index)1248*4882a593Smuzhiyun static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
1249*4882a593Smuzhiyun {
1250*4882a593Smuzhiyun unsigned int vol = ice->pro_volumes[index];
1251*4882a593Smuzhiyun unsigned short val = 0;
1252*4882a593Smuzhiyun
1253*4882a593Smuzhiyun val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
1254*4882a593Smuzhiyun val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
1255*4882a593Smuzhiyun outb(index, ICEMT(ice, MONITOR_INDEX));
1256*4882a593Smuzhiyun outw(val, ICEMT(ice, MONITOR_VOLUME));
1257*4882a593Smuzhiyun }
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun #define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
1260*4882a593Smuzhiyun
snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1261*4882a593Smuzhiyun static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1262*4882a593Smuzhiyun {
1263*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1264*4882a593Smuzhiyun int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1265*4882a593Smuzhiyun kcontrol->private_value;
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1268*4882a593Smuzhiyun ucontrol->value.integer.value[0] =
1269*4882a593Smuzhiyun !((ice->pro_volumes[priv_idx] >> 15) & 1);
1270*4882a593Smuzhiyun ucontrol->value.integer.value[1] =
1271*4882a593Smuzhiyun !((ice->pro_volumes[priv_idx] >> 31) & 1);
1272*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1273*4882a593Smuzhiyun return 0;
1274*4882a593Smuzhiyun }
1275*4882a593Smuzhiyun
snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1276*4882a593Smuzhiyun static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1277*4882a593Smuzhiyun {
1278*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1279*4882a593Smuzhiyun int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1280*4882a593Smuzhiyun kcontrol->private_value;
1281*4882a593Smuzhiyun unsigned int nval, change;
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
1284*4882a593Smuzhiyun (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
1285*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1286*4882a593Smuzhiyun nval |= ice->pro_volumes[priv_idx] & ~0x80008000;
1287*4882a593Smuzhiyun change = nval != ice->pro_volumes[priv_idx];
1288*4882a593Smuzhiyun ice->pro_volumes[priv_idx] = nval;
1289*4882a593Smuzhiyun snd_ice1712_update_volume(ice, priv_idx);
1290*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1291*4882a593Smuzhiyun return change;
1292*4882a593Smuzhiyun }
1293*4882a593Smuzhiyun
snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1294*4882a593Smuzhiyun static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1295*4882a593Smuzhiyun {
1296*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1297*4882a593Smuzhiyun uinfo->count = 2;
1298*4882a593Smuzhiyun uinfo->value.integer.min = 0;
1299*4882a593Smuzhiyun uinfo->value.integer.max = 96;
1300*4882a593Smuzhiyun return 0;
1301*4882a593Smuzhiyun }
1302*4882a593Smuzhiyun
snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1303*4882a593Smuzhiyun static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1304*4882a593Smuzhiyun {
1305*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1306*4882a593Smuzhiyun int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1307*4882a593Smuzhiyun kcontrol->private_value;
1308*4882a593Smuzhiyun
1309*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1310*4882a593Smuzhiyun ucontrol->value.integer.value[0] =
1311*4882a593Smuzhiyun (ice->pro_volumes[priv_idx] >> 0) & 127;
1312*4882a593Smuzhiyun ucontrol->value.integer.value[1] =
1313*4882a593Smuzhiyun (ice->pro_volumes[priv_idx] >> 16) & 127;
1314*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1315*4882a593Smuzhiyun return 0;
1316*4882a593Smuzhiyun }
1317*4882a593Smuzhiyun
snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1318*4882a593Smuzhiyun static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1319*4882a593Smuzhiyun {
1320*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1321*4882a593Smuzhiyun int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1322*4882a593Smuzhiyun kcontrol->private_value;
1323*4882a593Smuzhiyun unsigned int nval, change;
1324*4882a593Smuzhiyun
1325*4882a593Smuzhiyun nval = (ucontrol->value.integer.value[0] & 127) |
1326*4882a593Smuzhiyun ((ucontrol->value.integer.value[1] & 127) << 16);
1327*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1328*4882a593Smuzhiyun nval |= ice->pro_volumes[priv_idx] & ~0x007f007f;
1329*4882a593Smuzhiyun change = nval != ice->pro_volumes[priv_idx];
1330*4882a593Smuzhiyun ice->pro_volumes[priv_idx] = nval;
1331*4882a593Smuzhiyun snd_ice1712_update_volume(ice, priv_idx);
1332*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1333*4882a593Smuzhiyun return change;
1334*4882a593Smuzhiyun }
1335*4882a593Smuzhiyun
1336*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] = {
1339*4882a593Smuzhiyun {
1340*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1341*4882a593Smuzhiyun .name = "Multi Playback Switch",
1342*4882a593Smuzhiyun .info = snd_ice1712_pro_mixer_switch_info,
1343*4882a593Smuzhiyun .get = snd_ice1712_pro_mixer_switch_get,
1344*4882a593Smuzhiyun .put = snd_ice1712_pro_mixer_switch_put,
1345*4882a593Smuzhiyun .private_value = 0,
1346*4882a593Smuzhiyun .count = 10,
1347*4882a593Smuzhiyun },
1348*4882a593Smuzhiyun {
1349*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1350*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1351*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1352*4882a593Smuzhiyun .name = "Multi Playback Volume",
1353*4882a593Smuzhiyun .info = snd_ice1712_pro_mixer_volume_info,
1354*4882a593Smuzhiyun .get = snd_ice1712_pro_mixer_volume_get,
1355*4882a593Smuzhiyun .put = snd_ice1712_pro_mixer_volume_put,
1356*4882a593Smuzhiyun .private_value = 0,
1357*4882a593Smuzhiyun .count = 10,
1358*4882a593Smuzhiyun .tlv = { .p = db_scale_playback }
1359*4882a593Smuzhiyun },
1360*4882a593Smuzhiyun };
1361*4882a593Smuzhiyun
1362*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch = {
1363*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1364*4882a593Smuzhiyun .name = "H/W Multi Capture Switch",
1365*4882a593Smuzhiyun .info = snd_ice1712_pro_mixer_switch_info,
1366*4882a593Smuzhiyun .get = snd_ice1712_pro_mixer_switch_get,
1367*4882a593Smuzhiyun .put = snd_ice1712_pro_mixer_switch_put,
1368*4882a593Smuzhiyun .private_value = 10,
1369*4882a593Smuzhiyun };
1370*4882a593Smuzhiyun
1371*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch = {
1372*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1373*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, SWITCH),
1374*4882a593Smuzhiyun .info = snd_ice1712_pro_mixer_switch_info,
1375*4882a593Smuzhiyun .get = snd_ice1712_pro_mixer_switch_get,
1376*4882a593Smuzhiyun .put = snd_ice1712_pro_mixer_switch_put,
1377*4882a593Smuzhiyun .private_value = 18,
1378*4882a593Smuzhiyun .count = 2,
1379*4882a593Smuzhiyun };
1380*4882a593Smuzhiyun
1381*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume = {
1382*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1383*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1384*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1385*4882a593Smuzhiyun .name = "H/W Multi Capture Volume",
1386*4882a593Smuzhiyun .info = snd_ice1712_pro_mixer_volume_info,
1387*4882a593Smuzhiyun .get = snd_ice1712_pro_mixer_volume_get,
1388*4882a593Smuzhiyun .put = snd_ice1712_pro_mixer_volume_put,
1389*4882a593Smuzhiyun .private_value = 10,
1390*4882a593Smuzhiyun .tlv = { .p = db_scale_playback }
1391*4882a593Smuzhiyun };
1392*4882a593Smuzhiyun
1393*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume = {
1394*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1395*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, VOLUME),
1396*4882a593Smuzhiyun .info = snd_ice1712_pro_mixer_volume_info,
1397*4882a593Smuzhiyun .get = snd_ice1712_pro_mixer_volume_get,
1398*4882a593Smuzhiyun .put = snd_ice1712_pro_mixer_volume_put,
1399*4882a593Smuzhiyun .private_value = 18,
1400*4882a593Smuzhiyun .count = 2,
1401*4882a593Smuzhiyun };
1402*4882a593Smuzhiyun
snd_ice1712_build_pro_mixer(struct snd_ice1712 * ice)1403*4882a593Smuzhiyun static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
1404*4882a593Smuzhiyun {
1405*4882a593Smuzhiyun struct snd_card *card = ice->card;
1406*4882a593Smuzhiyun unsigned int idx;
1407*4882a593Smuzhiyun int err;
1408*4882a593Smuzhiyun
1409*4882a593Smuzhiyun /* multi-channel mixer */
1410*4882a593Smuzhiyun for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
1411*4882a593Smuzhiyun err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
1412*4882a593Smuzhiyun if (err < 0)
1413*4882a593Smuzhiyun return err;
1414*4882a593Smuzhiyun }
1415*4882a593Smuzhiyun
1416*4882a593Smuzhiyun if (ice->num_total_adcs > 0) {
1417*4882a593Smuzhiyun struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
1418*4882a593Smuzhiyun tmp.count = ice->num_total_adcs;
1419*4882a593Smuzhiyun err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
1420*4882a593Smuzhiyun if (err < 0)
1421*4882a593Smuzhiyun return err;
1422*4882a593Smuzhiyun }
1423*4882a593Smuzhiyun
1424*4882a593Smuzhiyun err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
1425*4882a593Smuzhiyun if (err < 0)
1426*4882a593Smuzhiyun return err;
1427*4882a593Smuzhiyun
1428*4882a593Smuzhiyun if (ice->num_total_adcs > 0) {
1429*4882a593Smuzhiyun struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
1430*4882a593Smuzhiyun tmp.count = ice->num_total_adcs;
1431*4882a593Smuzhiyun err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
1432*4882a593Smuzhiyun if (err < 0)
1433*4882a593Smuzhiyun return err;
1434*4882a593Smuzhiyun }
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
1437*4882a593Smuzhiyun if (err < 0)
1438*4882a593Smuzhiyun return err;
1439*4882a593Smuzhiyun
1440*4882a593Smuzhiyun /* initialize volumes */
1441*4882a593Smuzhiyun for (idx = 0; idx < 10; idx++) {
1442*4882a593Smuzhiyun ice->pro_volumes[idx] = 0x80008000; /* mute */
1443*4882a593Smuzhiyun snd_ice1712_update_volume(ice, idx);
1444*4882a593Smuzhiyun }
1445*4882a593Smuzhiyun for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
1446*4882a593Smuzhiyun ice->pro_volumes[idx] = 0x80008000; /* mute */
1447*4882a593Smuzhiyun snd_ice1712_update_volume(ice, idx);
1448*4882a593Smuzhiyun }
1449*4882a593Smuzhiyun for (idx = 18; idx < 20; idx++) {
1450*4882a593Smuzhiyun ice->pro_volumes[idx] = 0x80008000; /* mute */
1451*4882a593Smuzhiyun snd_ice1712_update_volume(ice, idx);
1452*4882a593Smuzhiyun }
1453*4882a593Smuzhiyun return 0;
1454*4882a593Smuzhiyun }
1455*4882a593Smuzhiyun
snd_ice1712_mixer_free_ac97(struct snd_ac97 * ac97)1456*4882a593Smuzhiyun static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
1457*4882a593Smuzhiyun {
1458*4882a593Smuzhiyun struct snd_ice1712 *ice = ac97->private_data;
1459*4882a593Smuzhiyun ice->ac97 = NULL;
1460*4882a593Smuzhiyun }
1461*4882a593Smuzhiyun
snd_ice1712_ac97_mixer(struct snd_ice1712 * ice)1462*4882a593Smuzhiyun static int snd_ice1712_ac97_mixer(struct snd_ice1712 *ice)
1463*4882a593Smuzhiyun {
1464*4882a593Smuzhiyun int err, bus_num = 0;
1465*4882a593Smuzhiyun struct snd_ac97_template ac97;
1466*4882a593Smuzhiyun struct snd_ac97_bus *pbus;
1467*4882a593Smuzhiyun static const struct snd_ac97_bus_ops con_ops = {
1468*4882a593Smuzhiyun .write = snd_ice1712_ac97_write,
1469*4882a593Smuzhiyun .read = snd_ice1712_ac97_read,
1470*4882a593Smuzhiyun };
1471*4882a593Smuzhiyun static const struct snd_ac97_bus_ops pro_ops = {
1472*4882a593Smuzhiyun .write = snd_ice1712_pro_ac97_write,
1473*4882a593Smuzhiyun .read = snd_ice1712_pro_ac97_read,
1474*4882a593Smuzhiyun };
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun if (ice_has_con_ac97(ice)) {
1477*4882a593Smuzhiyun err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus);
1478*4882a593Smuzhiyun if (err < 0)
1479*4882a593Smuzhiyun return err;
1480*4882a593Smuzhiyun memset(&ac97, 0, sizeof(ac97));
1481*4882a593Smuzhiyun ac97.private_data = ice;
1482*4882a593Smuzhiyun ac97.private_free = snd_ice1712_mixer_free_ac97;
1483*4882a593Smuzhiyun err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
1484*4882a593Smuzhiyun if (err < 0)
1485*4882a593Smuzhiyun dev_warn(ice->card->dev,
1486*4882a593Smuzhiyun "cannot initialize ac97 for consumer, skipped\n");
1487*4882a593Smuzhiyun else {
1488*4882a593Smuzhiyun return snd_ctl_add(ice->card,
1489*4882a593Smuzhiyun snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97,
1490*4882a593Smuzhiyun ice));
1491*4882a593Smuzhiyun }
1492*4882a593Smuzhiyun }
1493*4882a593Smuzhiyun
1494*4882a593Smuzhiyun if (!(ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
1495*4882a593Smuzhiyun err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus);
1496*4882a593Smuzhiyun if (err < 0)
1497*4882a593Smuzhiyun return err;
1498*4882a593Smuzhiyun memset(&ac97, 0, sizeof(ac97));
1499*4882a593Smuzhiyun ac97.private_data = ice;
1500*4882a593Smuzhiyun ac97.private_free = snd_ice1712_mixer_free_ac97;
1501*4882a593Smuzhiyun err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
1502*4882a593Smuzhiyun if (err < 0)
1503*4882a593Smuzhiyun dev_warn(ice->card->dev,
1504*4882a593Smuzhiyun "cannot initialize pro ac97, skipped\n");
1505*4882a593Smuzhiyun else
1506*4882a593Smuzhiyun return 0;
1507*4882a593Smuzhiyun }
1508*4882a593Smuzhiyun /* I2S mixer only */
1509*4882a593Smuzhiyun strcat(ice->card->mixername, "ICE1712 - multitrack");
1510*4882a593Smuzhiyun return 0;
1511*4882a593Smuzhiyun }
1512*4882a593Smuzhiyun
1513*4882a593Smuzhiyun /*
1514*4882a593Smuzhiyun *
1515*4882a593Smuzhiyun */
1516*4882a593Smuzhiyun
eeprom_double(struct snd_ice1712 * ice,int idx)1517*4882a593Smuzhiyun static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
1518*4882a593Smuzhiyun {
1519*4882a593Smuzhiyun return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
1520*4882a593Smuzhiyun }
1521*4882a593Smuzhiyun
snd_ice1712_proc_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1522*4882a593Smuzhiyun static void snd_ice1712_proc_read(struct snd_info_entry *entry,
1523*4882a593Smuzhiyun struct snd_info_buffer *buffer)
1524*4882a593Smuzhiyun {
1525*4882a593Smuzhiyun struct snd_ice1712 *ice = entry->private_data;
1526*4882a593Smuzhiyun unsigned int idx;
1527*4882a593Smuzhiyun
1528*4882a593Smuzhiyun snd_iprintf(buffer, "%s\n\n", ice->card->longname);
1529*4882a593Smuzhiyun snd_iprintf(buffer, "EEPROM:\n");
1530*4882a593Smuzhiyun
1531*4882a593Smuzhiyun snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
1532*4882a593Smuzhiyun snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
1533*4882a593Smuzhiyun snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
1534*4882a593Smuzhiyun snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
1535*4882a593Smuzhiyun snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
1536*4882a593Smuzhiyun snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
1537*4882a593Smuzhiyun snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
1538*4882a593Smuzhiyun snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
1539*4882a593Smuzhiyun snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
1540*4882a593Smuzhiyun snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
1541*4882a593Smuzhiyun snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
1542*4882a593Smuzhiyun snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
1543*4882a593Smuzhiyun snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
1544*4882a593Smuzhiyun snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
1545*4882a593Smuzhiyun for (idx = 0; idx < 4; idx++)
1546*4882a593Smuzhiyun snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
1547*4882a593Smuzhiyun for (idx = 0; idx < 4; idx++)
1548*4882a593Smuzhiyun snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
1549*4882a593Smuzhiyun for (idx = 0x1c; idx < ice->eeprom.size; idx++)
1550*4882a593Smuzhiyun snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
1551*4882a593Smuzhiyun
1552*4882a593Smuzhiyun snd_iprintf(buffer, "\nRegisters:\n");
1553*4882a593Smuzhiyun snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
1554*4882a593Smuzhiyun snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
1555*4882a593Smuzhiyun snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
1556*4882a593Smuzhiyun snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
1557*4882a593Smuzhiyun snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
1558*4882a593Smuzhiyun snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
1559*4882a593Smuzhiyun snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
1560*4882a593Smuzhiyun }
1561*4882a593Smuzhiyun
snd_ice1712_proc_init(struct snd_ice1712 * ice)1562*4882a593Smuzhiyun static void snd_ice1712_proc_init(struct snd_ice1712 *ice)
1563*4882a593Smuzhiyun {
1564*4882a593Smuzhiyun snd_card_ro_proc_new(ice->card, "ice1712", ice, snd_ice1712_proc_read);
1565*4882a593Smuzhiyun }
1566*4882a593Smuzhiyun
1567*4882a593Smuzhiyun /*
1568*4882a593Smuzhiyun *
1569*4882a593Smuzhiyun */
1570*4882a593Smuzhiyun
snd_ice1712_eeprom_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1571*4882a593Smuzhiyun static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
1572*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1573*4882a593Smuzhiyun {
1574*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1575*4882a593Smuzhiyun uinfo->count = sizeof(struct snd_ice1712_eeprom);
1576*4882a593Smuzhiyun return 0;
1577*4882a593Smuzhiyun }
1578*4882a593Smuzhiyun
snd_ice1712_eeprom_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1579*4882a593Smuzhiyun static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
1580*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1581*4882a593Smuzhiyun {
1582*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1583*4882a593Smuzhiyun
1584*4882a593Smuzhiyun memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
1585*4882a593Smuzhiyun return 0;
1586*4882a593Smuzhiyun }
1587*4882a593Smuzhiyun
1588*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_eeprom = {
1589*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_CARD,
1590*4882a593Smuzhiyun .name = "ICE1712 EEPROM",
1591*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ,
1592*4882a593Smuzhiyun .info = snd_ice1712_eeprom_info,
1593*4882a593Smuzhiyun .get = snd_ice1712_eeprom_get
1594*4882a593Smuzhiyun };
1595*4882a593Smuzhiyun
1596*4882a593Smuzhiyun /*
1597*4882a593Smuzhiyun */
snd_ice1712_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1598*4882a593Smuzhiyun static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
1599*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1600*4882a593Smuzhiyun {
1601*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1602*4882a593Smuzhiyun uinfo->count = 1;
1603*4882a593Smuzhiyun return 0;
1604*4882a593Smuzhiyun }
1605*4882a593Smuzhiyun
snd_ice1712_spdif_default_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1606*4882a593Smuzhiyun static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
1607*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1608*4882a593Smuzhiyun {
1609*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1610*4882a593Smuzhiyun if (ice->spdif.ops.default_get)
1611*4882a593Smuzhiyun ice->spdif.ops.default_get(ice, ucontrol);
1612*4882a593Smuzhiyun return 0;
1613*4882a593Smuzhiyun }
1614*4882a593Smuzhiyun
snd_ice1712_spdif_default_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1615*4882a593Smuzhiyun static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
1616*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1617*4882a593Smuzhiyun {
1618*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1619*4882a593Smuzhiyun if (ice->spdif.ops.default_put)
1620*4882a593Smuzhiyun return ice->spdif.ops.default_put(ice, ucontrol);
1621*4882a593Smuzhiyun return 0;
1622*4882a593Smuzhiyun }
1623*4882a593Smuzhiyun
1624*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_spdif_default =
1625*4882a593Smuzhiyun {
1626*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1627*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1628*4882a593Smuzhiyun .info = snd_ice1712_spdif_info,
1629*4882a593Smuzhiyun .get = snd_ice1712_spdif_default_get,
1630*4882a593Smuzhiyun .put = snd_ice1712_spdif_default_put
1631*4882a593Smuzhiyun };
1632*4882a593Smuzhiyun
snd_ice1712_spdif_maskc_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1633*4882a593Smuzhiyun static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
1634*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1635*4882a593Smuzhiyun {
1636*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1637*4882a593Smuzhiyun if (ice->spdif.ops.default_get) {
1638*4882a593Smuzhiyun ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1639*4882a593Smuzhiyun IEC958_AES0_PROFESSIONAL |
1640*4882a593Smuzhiyun IEC958_AES0_CON_NOT_COPYRIGHT |
1641*4882a593Smuzhiyun IEC958_AES0_CON_EMPHASIS;
1642*4882a593Smuzhiyun ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
1643*4882a593Smuzhiyun IEC958_AES1_CON_CATEGORY;
1644*4882a593Smuzhiyun ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
1645*4882a593Smuzhiyun } else {
1646*4882a593Smuzhiyun ucontrol->value.iec958.status[0] = 0xff;
1647*4882a593Smuzhiyun ucontrol->value.iec958.status[1] = 0xff;
1648*4882a593Smuzhiyun ucontrol->value.iec958.status[2] = 0xff;
1649*4882a593Smuzhiyun ucontrol->value.iec958.status[3] = 0xff;
1650*4882a593Smuzhiyun ucontrol->value.iec958.status[4] = 0xff;
1651*4882a593Smuzhiyun }
1652*4882a593Smuzhiyun return 0;
1653*4882a593Smuzhiyun }
1654*4882a593Smuzhiyun
snd_ice1712_spdif_maskp_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1655*4882a593Smuzhiyun static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
1656*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1657*4882a593Smuzhiyun {
1658*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1659*4882a593Smuzhiyun if (ice->spdif.ops.default_get) {
1660*4882a593Smuzhiyun ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1661*4882a593Smuzhiyun IEC958_AES0_PROFESSIONAL |
1662*4882a593Smuzhiyun IEC958_AES0_PRO_FS |
1663*4882a593Smuzhiyun IEC958_AES0_PRO_EMPHASIS;
1664*4882a593Smuzhiyun ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
1665*4882a593Smuzhiyun } else {
1666*4882a593Smuzhiyun ucontrol->value.iec958.status[0] = 0xff;
1667*4882a593Smuzhiyun ucontrol->value.iec958.status[1] = 0xff;
1668*4882a593Smuzhiyun ucontrol->value.iec958.status[2] = 0xff;
1669*4882a593Smuzhiyun ucontrol->value.iec958.status[3] = 0xff;
1670*4882a593Smuzhiyun ucontrol->value.iec958.status[4] = 0xff;
1671*4882a593Smuzhiyun }
1672*4882a593Smuzhiyun return 0;
1673*4882a593Smuzhiyun }
1674*4882a593Smuzhiyun
1675*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_spdif_maskc =
1676*4882a593Smuzhiyun {
1677*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ,
1678*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1679*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1680*4882a593Smuzhiyun .info = snd_ice1712_spdif_info,
1681*4882a593Smuzhiyun .get = snd_ice1712_spdif_maskc_get,
1682*4882a593Smuzhiyun };
1683*4882a593Smuzhiyun
1684*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_spdif_maskp =
1685*4882a593Smuzhiyun {
1686*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ,
1687*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1688*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1689*4882a593Smuzhiyun .info = snd_ice1712_spdif_info,
1690*4882a593Smuzhiyun .get = snd_ice1712_spdif_maskp_get,
1691*4882a593Smuzhiyun };
1692*4882a593Smuzhiyun
snd_ice1712_spdif_stream_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1693*4882a593Smuzhiyun static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
1694*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1695*4882a593Smuzhiyun {
1696*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1697*4882a593Smuzhiyun if (ice->spdif.ops.stream_get)
1698*4882a593Smuzhiyun ice->spdif.ops.stream_get(ice, ucontrol);
1699*4882a593Smuzhiyun return 0;
1700*4882a593Smuzhiyun }
1701*4882a593Smuzhiyun
snd_ice1712_spdif_stream_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1702*4882a593Smuzhiyun static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
1703*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1704*4882a593Smuzhiyun {
1705*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1706*4882a593Smuzhiyun if (ice->spdif.ops.stream_put)
1707*4882a593Smuzhiyun return ice->spdif.ops.stream_put(ice, ucontrol);
1708*4882a593Smuzhiyun return 0;
1709*4882a593Smuzhiyun }
1710*4882a593Smuzhiyun
1711*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_spdif_stream =
1712*4882a593Smuzhiyun {
1713*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1714*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_INACTIVE),
1715*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1716*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1717*4882a593Smuzhiyun .info = snd_ice1712_spdif_info,
1718*4882a593Smuzhiyun .get = snd_ice1712_spdif_stream_get,
1719*4882a593Smuzhiyun .put = snd_ice1712_spdif_stream_put
1720*4882a593Smuzhiyun };
1721*4882a593Smuzhiyun
snd_ice1712_gpio_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1722*4882a593Smuzhiyun int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
1723*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1724*4882a593Smuzhiyun {
1725*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1726*4882a593Smuzhiyun unsigned char mask = kcontrol->private_value & 0xff;
1727*4882a593Smuzhiyun int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
1728*4882a593Smuzhiyun
1729*4882a593Smuzhiyun snd_ice1712_save_gpio_status(ice);
1730*4882a593Smuzhiyun ucontrol->value.integer.value[0] =
1731*4882a593Smuzhiyun (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
1732*4882a593Smuzhiyun snd_ice1712_restore_gpio_status(ice);
1733*4882a593Smuzhiyun return 0;
1734*4882a593Smuzhiyun }
1735*4882a593Smuzhiyun
snd_ice1712_gpio_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1736*4882a593Smuzhiyun int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
1737*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1738*4882a593Smuzhiyun {
1739*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1740*4882a593Smuzhiyun unsigned char mask = kcontrol->private_value & 0xff;
1741*4882a593Smuzhiyun int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
1742*4882a593Smuzhiyun unsigned int val, nval;
1743*4882a593Smuzhiyun
1744*4882a593Smuzhiyun if (kcontrol->private_value & (1 << 31))
1745*4882a593Smuzhiyun return -EPERM;
1746*4882a593Smuzhiyun nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
1747*4882a593Smuzhiyun snd_ice1712_save_gpio_status(ice);
1748*4882a593Smuzhiyun val = snd_ice1712_gpio_read(ice);
1749*4882a593Smuzhiyun nval |= val & ~mask;
1750*4882a593Smuzhiyun if (val != nval)
1751*4882a593Smuzhiyun snd_ice1712_gpio_write(ice, nval);
1752*4882a593Smuzhiyun snd_ice1712_restore_gpio_status(ice);
1753*4882a593Smuzhiyun return val != nval;
1754*4882a593Smuzhiyun }
1755*4882a593Smuzhiyun
1756*4882a593Smuzhiyun /*
1757*4882a593Smuzhiyun * rate
1758*4882a593Smuzhiyun */
snd_ice1712_pro_internal_clock_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1759*4882a593Smuzhiyun static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
1760*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1761*4882a593Smuzhiyun {
1762*4882a593Smuzhiyun static const char * const texts[] = {
1763*4882a593Smuzhiyun "8000", /* 0: 6 */
1764*4882a593Smuzhiyun "9600", /* 1: 3 */
1765*4882a593Smuzhiyun "11025", /* 2: 10 */
1766*4882a593Smuzhiyun "12000", /* 3: 2 */
1767*4882a593Smuzhiyun "16000", /* 4: 5 */
1768*4882a593Smuzhiyun "22050", /* 5: 9 */
1769*4882a593Smuzhiyun "24000", /* 6: 1 */
1770*4882a593Smuzhiyun "32000", /* 7: 4 */
1771*4882a593Smuzhiyun "44100", /* 8: 8 */
1772*4882a593Smuzhiyun "48000", /* 9: 0 */
1773*4882a593Smuzhiyun "64000", /* 10: 15 */
1774*4882a593Smuzhiyun "88200", /* 11: 11 */
1775*4882a593Smuzhiyun "96000", /* 12: 7 */
1776*4882a593Smuzhiyun "IEC958 Input", /* 13: -- */
1777*4882a593Smuzhiyun };
1778*4882a593Smuzhiyun return snd_ctl_enum_info(uinfo, 1, 14, texts);
1779*4882a593Smuzhiyun }
1780*4882a593Smuzhiyun
snd_ice1712_pro_internal_clock_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1781*4882a593Smuzhiyun static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
1782*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1783*4882a593Smuzhiyun {
1784*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1785*4882a593Smuzhiyun static const unsigned char xlate[16] = {
1786*4882a593Smuzhiyun 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
1787*4882a593Smuzhiyun };
1788*4882a593Smuzhiyun unsigned char val;
1789*4882a593Smuzhiyun
1790*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1791*4882a593Smuzhiyun if (is_spdif_master(ice)) {
1792*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = 13;
1793*4882a593Smuzhiyun } else {
1794*4882a593Smuzhiyun val = xlate[inb(ICEMT(ice, RATE)) & 15];
1795*4882a593Smuzhiyun if (val == 255) {
1796*4882a593Smuzhiyun snd_BUG();
1797*4882a593Smuzhiyun val = 0;
1798*4882a593Smuzhiyun }
1799*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = val;
1800*4882a593Smuzhiyun }
1801*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1802*4882a593Smuzhiyun return 0;
1803*4882a593Smuzhiyun }
1804*4882a593Smuzhiyun
snd_ice1712_pro_internal_clock_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1805*4882a593Smuzhiyun static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
1806*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1807*4882a593Smuzhiyun {
1808*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1809*4882a593Smuzhiyun static const unsigned int xrate[13] = {
1810*4882a593Smuzhiyun 8000, 9600, 11025, 12000, 16000, 22050, 24000,
1811*4882a593Smuzhiyun 32000, 44100, 48000, 64000, 88200, 96000
1812*4882a593Smuzhiyun };
1813*4882a593Smuzhiyun unsigned char oval;
1814*4882a593Smuzhiyun int change = 0;
1815*4882a593Smuzhiyun
1816*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1817*4882a593Smuzhiyun oval = inb(ICEMT(ice, RATE));
1818*4882a593Smuzhiyun if (ucontrol->value.enumerated.item[0] == 13) {
1819*4882a593Smuzhiyun outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
1820*4882a593Smuzhiyun } else {
1821*4882a593Smuzhiyun PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
1822*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1823*4882a593Smuzhiyun snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
1824*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1825*4882a593Smuzhiyun }
1826*4882a593Smuzhiyun change = inb(ICEMT(ice, RATE)) != oval;
1827*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1828*4882a593Smuzhiyun
1829*4882a593Smuzhiyun if ((oval & ICE1712_SPDIF_MASTER) !=
1830*4882a593Smuzhiyun (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
1831*4882a593Smuzhiyun snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
1832*4882a593Smuzhiyun
1833*4882a593Smuzhiyun return change;
1834*4882a593Smuzhiyun }
1835*4882a593Smuzhiyun
1836*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_pro_internal_clock = {
1837*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1838*4882a593Smuzhiyun .name = "Multi Track Internal Clock",
1839*4882a593Smuzhiyun .info = snd_ice1712_pro_internal_clock_info,
1840*4882a593Smuzhiyun .get = snd_ice1712_pro_internal_clock_get,
1841*4882a593Smuzhiyun .put = snd_ice1712_pro_internal_clock_put
1842*4882a593Smuzhiyun };
1843*4882a593Smuzhiyun
snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1844*4882a593Smuzhiyun static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
1845*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1846*4882a593Smuzhiyun {
1847*4882a593Smuzhiyun static const char * const texts[] = {
1848*4882a593Smuzhiyun "8000", /* 0: 6 */
1849*4882a593Smuzhiyun "9600", /* 1: 3 */
1850*4882a593Smuzhiyun "11025", /* 2: 10 */
1851*4882a593Smuzhiyun "12000", /* 3: 2 */
1852*4882a593Smuzhiyun "16000", /* 4: 5 */
1853*4882a593Smuzhiyun "22050", /* 5: 9 */
1854*4882a593Smuzhiyun "24000", /* 6: 1 */
1855*4882a593Smuzhiyun "32000", /* 7: 4 */
1856*4882a593Smuzhiyun "44100", /* 8: 8 */
1857*4882a593Smuzhiyun "48000", /* 9: 0 */
1858*4882a593Smuzhiyun "64000", /* 10: 15 */
1859*4882a593Smuzhiyun "88200", /* 11: 11 */
1860*4882a593Smuzhiyun "96000", /* 12: 7 */
1861*4882a593Smuzhiyun /* "IEC958 Input", 13: -- */
1862*4882a593Smuzhiyun };
1863*4882a593Smuzhiyun return snd_ctl_enum_info(uinfo, 1, 13, texts);
1864*4882a593Smuzhiyun }
1865*4882a593Smuzhiyun
snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1866*4882a593Smuzhiyun static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
1867*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1868*4882a593Smuzhiyun {
1869*4882a593Smuzhiyun int val;
1870*4882a593Smuzhiyun static const unsigned int xrate[13] = {
1871*4882a593Smuzhiyun 8000, 9600, 11025, 12000, 16000, 22050, 24000,
1872*4882a593Smuzhiyun 32000, 44100, 48000, 64000, 88200, 96000
1873*4882a593Smuzhiyun };
1874*4882a593Smuzhiyun
1875*4882a593Smuzhiyun for (val = 0; val < 13; val++) {
1876*4882a593Smuzhiyun if (xrate[val] == PRO_RATE_DEFAULT)
1877*4882a593Smuzhiyun break;
1878*4882a593Smuzhiyun }
1879*4882a593Smuzhiyun
1880*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = val;
1881*4882a593Smuzhiyun return 0;
1882*4882a593Smuzhiyun }
1883*4882a593Smuzhiyun
snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1884*4882a593Smuzhiyun static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
1885*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1886*4882a593Smuzhiyun {
1887*4882a593Smuzhiyun static const unsigned int xrate[13] = {
1888*4882a593Smuzhiyun 8000, 9600, 11025, 12000, 16000, 22050, 24000,
1889*4882a593Smuzhiyun 32000, 44100, 48000, 64000, 88200, 96000
1890*4882a593Smuzhiyun };
1891*4882a593Smuzhiyun unsigned char oval;
1892*4882a593Smuzhiyun int change = 0;
1893*4882a593Smuzhiyun
1894*4882a593Smuzhiyun oval = PRO_RATE_DEFAULT;
1895*4882a593Smuzhiyun PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
1896*4882a593Smuzhiyun change = PRO_RATE_DEFAULT != oval;
1897*4882a593Smuzhiyun
1898*4882a593Smuzhiyun return change;
1899*4882a593Smuzhiyun }
1900*4882a593Smuzhiyun
1901*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default = {
1902*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1903*4882a593Smuzhiyun .name = "Multi Track Internal Clock Default",
1904*4882a593Smuzhiyun .info = snd_ice1712_pro_internal_clock_default_info,
1905*4882a593Smuzhiyun .get = snd_ice1712_pro_internal_clock_default_get,
1906*4882a593Smuzhiyun .put = snd_ice1712_pro_internal_clock_default_put
1907*4882a593Smuzhiyun };
1908*4882a593Smuzhiyun
1909*4882a593Smuzhiyun #define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
1910*4882a593Smuzhiyun
snd_ice1712_pro_rate_locking_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1911*4882a593Smuzhiyun static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
1912*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1913*4882a593Smuzhiyun {
1914*4882a593Smuzhiyun ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
1915*4882a593Smuzhiyun return 0;
1916*4882a593Smuzhiyun }
1917*4882a593Smuzhiyun
snd_ice1712_pro_rate_locking_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1918*4882a593Smuzhiyun static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
1919*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1920*4882a593Smuzhiyun {
1921*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1922*4882a593Smuzhiyun int change = 0, nval;
1923*4882a593Smuzhiyun
1924*4882a593Smuzhiyun nval = ucontrol->value.integer.value[0] ? 1 : 0;
1925*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1926*4882a593Smuzhiyun change = PRO_RATE_LOCKED != nval;
1927*4882a593Smuzhiyun PRO_RATE_LOCKED = nval;
1928*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1929*4882a593Smuzhiyun return change;
1930*4882a593Smuzhiyun }
1931*4882a593Smuzhiyun
1932*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_pro_rate_locking = {
1933*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1934*4882a593Smuzhiyun .name = "Multi Track Rate Locking",
1935*4882a593Smuzhiyun .info = snd_ice1712_pro_rate_locking_info,
1936*4882a593Smuzhiyun .get = snd_ice1712_pro_rate_locking_get,
1937*4882a593Smuzhiyun .put = snd_ice1712_pro_rate_locking_put
1938*4882a593Smuzhiyun };
1939*4882a593Smuzhiyun
1940*4882a593Smuzhiyun #define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
1941*4882a593Smuzhiyun
snd_ice1712_pro_rate_reset_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1942*4882a593Smuzhiyun static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
1943*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1944*4882a593Smuzhiyun {
1945*4882a593Smuzhiyun ucontrol->value.integer.value[0] = PRO_RATE_RESET;
1946*4882a593Smuzhiyun return 0;
1947*4882a593Smuzhiyun }
1948*4882a593Smuzhiyun
snd_ice1712_pro_rate_reset_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1949*4882a593Smuzhiyun static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
1950*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1951*4882a593Smuzhiyun {
1952*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1953*4882a593Smuzhiyun int change = 0, nval;
1954*4882a593Smuzhiyun
1955*4882a593Smuzhiyun nval = ucontrol->value.integer.value[0] ? 1 : 0;
1956*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1957*4882a593Smuzhiyun change = PRO_RATE_RESET != nval;
1958*4882a593Smuzhiyun PRO_RATE_RESET = nval;
1959*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1960*4882a593Smuzhiyun return change;
1961*4882a593Smuzhiyun }
1962*4882a593Smuzhiyun
1963*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_pro_rate_reset = {
1964*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1965*4882a593Smuzhiyun .name = "Multi Track Rate Reset",
1966*4882a593Smuzhiyun .info = snd_ice1712_pro_rate_reset_info,
1967*4882a593Smuzhiyun .get = snd_ice1712_pro_rate_reset_get,
1968*4882a593Smuzhiyun .put = snd_ice1712_pro_rate_reset_put
1969*4882a593Smuzhiyun };
1970*4882a593Smuzhiyun
1971*4882a593Smuzhiyun /*
1972*4882a593Smuzhiyun * routing
1973*4882a593Smuzhiyun */
snd_ice1712_pro_route_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1974*4882a593Smuzhiyun static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
1975*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1976*4882a593Smuzhiyun {
1977*4882a593Smuzhiyun static const char * const texts[] = {
1978*4882a593Smuzhiyun "PCM Out", /* 0 */
1979*4882a593Smuzhiyun "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
1980*4882a593Smuzhiyun "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
1981*4882a593Smuzhiyun "IEC958 In L", "IEC958 In R", /* 9-10 */
1982*4882a593Smuzhiyun "Digital Mixer", /* 11 - optional */
1983*4882a593Smuzhiyun };
1984*4882a593Smuzhiyun int num_items = snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
1985*4882a593Smuzhiyun return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1986*4882a593Smuzhiyun }
1987*4882a593Smuzhiyun
snd_ice1712_pro_route_analog_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1988*4882a593Smuzhiyun static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
1989*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1990*4882a593Smuzhiyun {
1991*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1992*4882a593Smuzhiyun int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1993*4882a593Smuzhiyun unsigned int val, cval;
1994*4882a593Smuzhiyun
1995*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
1996*4882a593Smuzhiyun val = inw(ICEMT(ice, ROUTE_PSDOUT03));
1997*4882a593Smuzhiyun cval = inl(ICEMT(ice, ROUTE_CAPTURE));
1998*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
1999*4882a593Smuzhiyun
2000*4882a593Smuzhiyun val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
2001*4882a593Smuzhiyun val &= 3;
2002*4882a593Smuzhiyun cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
2003*4882a593Smuzhiyun if (val == 1 && idx < 2)
2004*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = 11;
2005*4882a593Smuzhiyun else if (val == 2)
2006*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
2007*4882a593Smuzhiyun else if (val == 3)
2008*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
2009*4882a593Smuzhiyun else
2010*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = 0;
2011*4882a593Smuzhiyun return 0;
2012*4882a593Smuzhiyun }
2013*4882a593Smuzhiyun
snd_ice1712_pro_route_analog_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2014*4882a593Smuzhiyun static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
2015*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2016*4882a593Smuzhiyun {
2017*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2018*4882a593Smuzhiyun int change, shift;
2019*4882a593Smuzhiyun int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2020*4882a593Smuzhiyun unsigned int val, old_val, nval;
2021*4882a593Smuzhiyun
2022*4882a593Smuzhiyun /* update PSDOUT */
2023*4882a593Smuzhiyun if (ucontrol->value.enumerated.item[0] >= 11)
2024*4882a593Smuzhiyun nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
2025*4882a593Smuzhiyun else if (ucontrol->value.enumerated.item[0] >= 9)
2026*4882a593Smuzhiyun nval = 3; /* spdif in */
2027*4882a593Smuzhiyun else if (ucontrol->value.enumerated.item[0] >= 1)
2028*4882a593Smuzhiyun nval = 2; /* analog in */
2029*4882a593Smuzhiyun else
2030*4882a593Smuzhiyun nval = 0; /* pcm */
2031*4882a593Smuzhiyun shift = ((idx % 2) * 8) + ((idx / 2) * 2);
2032*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
2033*4882a593Smuzhiyun val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
2034*4882a593Smuzhiyun val &= ~(0x03 << shift);
2035*4882a593Smuzhiyun val |= nval << shift;
2036*4882a593Smuzhiyun change = val != old_val;
2037*4882a593Smuzhiyun if (change)
2038*4882a593Smuzhiyun outw(val, ICEMT(ice, ROUTE_PSDOUT03));
2039*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
2040*4882a593Smuzhiyun if (nval < 2) /* dig mixer of pcm */
2041*4882a593Smuzhiyun return change;
2042*4882a593Smuzhiyun
2043*4882a593Smuzhiyun /* update CAPTURE */
2044*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
2045*4882a593Smuzhiyun val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
2046*4882a593Smuzhiyun shift = ((idx / 2) * 8) + ((idx % 2) * 4);
2047*4882a593Smuzhiyun if (nval == 2) { /* analog in */
2048*4882a593Smuzhiyun nval = ucontrol->value.enumerated.item[0] - 1;
2049*4882a593Smuzhiyun val &= ~(0x07 << shift);
2050*4882a593Smuzhiyun val |= nval << shift;
2051*4882a593Smuzhiyun } else { /* spdif in */
2052*4882a593Smuzhiyun nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
2053*4882a593Smuzhiyun val &= ~(0x08 << shift);
2054*4882a593Smuzhiyun val |= nval << shift;
2055*4882a593Smuzhiyun }
2056*4882a593Smuzhiyun if (val != old_val) {
2057*4882a593Smuzhiyun change = 1;
2058*4882a593Smuzhiyun outl(val, ICEMT(ice, ROUTE_CAPTURE));
2059*4882a593Smuzhiyun }
2060*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
2061*4882a593Smuzhiyun return change;
2062*4882a593Smuzhiyun }
2063*4882a593Smuzhiyun
snd_ice1712_pro_route_spdif_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2064*4882a593Smuzhiyun static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
2065*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2066*4882a593Smuzhiyun {
2067*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2068*4882a593Smuzhiyun int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2069*4882a593Smuzhiyun unsigned int val, cval;
2070*4882a593Smuzhiyun val = inw(ICEMT(ice, ROUTE_SPDOUT));
2071*4882a593Smuzhiyun cval = (val >> (idx * 4 + 8)) & 0x0f;
2072*4882a593Smuzhiyun val = (val >> (idx * 2)) & 0x03;
2073*4882a593Smuzhiyun if (val == 1)
2074*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = 11;
2075*4882a593Smuzhiyun else if (val == 2)
2076*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
2077*4882a593Smuzhiyun else if (val == 3)
2078*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
2079*4882a593Smuzhiyun else
2080*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = 0;
2081*4882a593Smuzhiyun return 0;
2082*4882a593Smuzhiyun }
2083*4882a593Smuzhiyun
snd_ice1712_pro_route_spdif_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2084*4882a593Smuzhiyun static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
2085*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2086*4882a593Smuzhiyun {
2087*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2088*4882a593Smuzhiyun int change, shift;
2089*4882a593Smuzhiyun int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2090*4882a593Smuzhiyun unsigned int val, old_val, nval;
2091*4882a593Smuzhiyun
2092*4882a593Smuzhiyun /* update SPDOUT */
2093*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
2094*4882a593Smuzhiyun val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
2095*4882a593Smuzhiyun if (ucontrol->value.enumerated.item[0] >= 11)
2096*4882a593Smuzhiyun nval = 1;
2097*4882a593Smuzhiyun else if (ucontrol->value.enumerated.item[0] >= 9)
2098*4882a593Smuzhiyun nval = 3;
2099*4882a593Smuzhiyun else if (ucontrol->value.enumerated.item[0] >= 1)
2100*4882a593Smuzhiyun nval = 2;
2101*4882a593Smuzhiyun else
2102*4882a593Smuzhiyun nval = 0;
2103*4882a593Smuzhiyun shift = idx * 2;
2104*4882a593Smuzhiyun val &= ~(0x03 << shift);
2105*4882a593Smuzhiyun val |= nval << shift;
2106*4882a593Smuzhiyun shift = idx * 4 + 8;
2107*4882a593Smuzhiyun if (nval == 2) {
2108*4882a593Smuzhiyun nval = ucontrol->value.enumerated.item[0] - 1;
2109*4882a593Smuzhiyun val &= ~(0x07 << shift);
2110*4882a593Smuzhiyun val |= nval << shift;
2111*4882a593Smuzhiyun } else if (nval == 3) {
2112*4882a593Smuzhiyun nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
2113*4882a593Smuzhiyun val &= ~(0x08 << shift);
2114*4882a593Smuzhiyun val |= nval << shift;
2115*4882a593Smuzhiyun }
2116*4882a593Smuzhiyun change = val != old_val;
2117*4882a593Smuzhiyun if (change)
2118*4882a593Smuzhiyun outw(val, ICEMT(ice, ROUTE_SPDOUT));
2119*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
2120*4882a593Smuzhiyun return change;
2121*4882a593Smuzhiyun }
2122*4882a593Smuzhiyun
2123*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route = {
2124*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2125*4882a593Smuzhiyun .name = "H/W Playback Route",
2126*4882a593Smuzhiyun .info = snd_ice1712_pro_route_info,
2127*4882a593Smuzhiyun .get = snd_ice1712_pro_route_analog_get,
2128*4882a593Smuzhiyun .put = snd_ice1712_pro_route_analog_put,
2129*4882a593Smuzhiyun };
2130*4882a593Smuzhiyun
2131*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route = {
2132*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2133*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
2134*4882a593Smuzhiyun .info = snd_ice1712_pro_route_info,
2135*4882a593Smuzhiyun .get = snd_ice1712_pro_route_spdif_get,
2136*4882a593Smuzhiyun .put = snd_ice1712_pro_route_spdif_put,
2137*4882a593Smuzhiyun .count = 2,
2138*4882a593Smuzhiyun };
2139*4882a593Smuzhiyun
2140*4882a593Smuzhiyun
snd_ice1712_pro_volume_rate_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2141*4882a593Smuzhiyun static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
2142*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
2143*4882a593Smuzhiyun {
2144*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2145*4882a593Smuzhiyun uinfo->count = 1;
2146*4882a593Smuzhiyun uinfo->value.integer.min = 0;
2147*4882a593Smuzhiyun uinfo->value.integer.max = 255;
2148*4882a593Smuzhiyun return 0;
2149*4882a593Smuzhiyun }
2150*4882a593Smuzhiyun
snd_ice1712_pro_volume_rate_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2151*4882a593Smuzhiyun static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
2152*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2153*4882a593Smuzhiyun {
2154*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2155*4882a593Smuzhiyun
2156*4882a593Smuzhiyun ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
2157*4882a593Smuzhiyun return 0;
2158*4882a593Smuzhiyun }
2159*4882a593Smuzhiyun
snd_ice1712_pro_volume_rate_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2160*4882a593Smuzhiyun static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
2161*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2162*4882a593Smuzhiyun {
2163*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2164*4882a593Smuzhiyun int change;
2165*4882a593Smuzhiyun
2166*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
2167*4882a593Smuzhiyun change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
2168*4882a593Smuzhiyun outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
2169*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
2170*4882a593Smuzhiyun return change;
2171*4882a593Smuzhiyun }
2172*4882a593Smuzhiyun
2173*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate = {
2174*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2175*4882a593Smuzhiyun .name = "Multi Track Volume Rate",
2176*4882a593Smuzhiyun .info = snd_ice1712_pro_volume_rate_info,
2177*4882a593Smuzhiyun .get = snd_ice1712_pro_volume_rate_get,
2178*4882a593Smuzhiyun .put = snd_ice1712_pro_volume_rate_put
2179*4882a593Smuzhiyun };
2180*4882a593Smuzhiyun
snd_ice1712_pro_peak_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2181*4882a593Smuzhiyun static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
2182*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
2183*4882a593Smuzhiyun {
2184*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2185*4882a593Smuzhiyun uinfo->count = 22;
2186*4882a593Smuzhiyun uinfo->value.integer.min = 0;
2187*4882a593Smuzhiyun uinfo->value.integer.max = 255;
2188*4882a593Smuzhiyun return 0;
2189*4882a593Smuzhiyun }
2190*4882a593Smuzhiyun
snd_ice1712_pro_peak_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2191*4882a593Smuzhiyun static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
2192*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
2193*4882a593Smuzhiyun {
2194*4882a593Smuzhiyun struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2195*4882a593Smuzhiyun int idx;
2196*4882a593Smuzhiyun
2197*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
2198*4882a593Smuzhiyun for (idx = 0; idx < 22; idx++) {
2199*4882a593Smuzhiyun outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
2200*4882a593Smuzhiyun ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
2201*4882a593Smuzhiyun }
2202*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
2203*4882a593Smuzhiyun return 0;
2204*4882a593Smuzhiyun }
2205*4882a593Smuzhiyun
2206*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_mixer_pro_peak = {
2207*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2208*4882a593Smuzhiyun .name = "Multi Track Peak",
2209*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
2210*4882a593Smuzhiyun .info = snd_ice1712_pro_peak_info,
2211*4882a593Smuzhiyun .get = snd_ice1712_pro_peak_get
2212*4882a593Smuzhiyun };
2213*4882a593Smuzhiyun
2214*4882a593Smuzhiyun /*
2215*4882a593Smuzhiyun *
2216*4882a593Smuzhiyun */
2217*4882a593Smuzhiyun
2218*4882a593Smuzhiyun /*
2219*4882a593Smuzhiyun * list of available boards
2220*4882a593Smuzhiyun */
2221*4882a593Smuzhiyun static const struct snd_ice1712_card_info *card_tables[] = {
2222*4882a593Smuzhiyun snd_ice1712_hoontech_cards,
2223*4882a593Smuzhiyun snd_ice1712_delta_cards,
2224*4882a593Smuzhiyun snd_ice1712_ews_cards,
2225*4882a593Smuzhiyun NULL,
2226*4882a593Smuzhiyun };
2227*4882a593Smuzhiyun
snd_ice1712_read_i2c(struct snd_ice1712 * ice,unsigned char dev,unsigned char addr)2228*4882a593Smuzhiyun static unsigned char snd_ice1712_read_i2c(struct snd_ice1712 *ice,
2229*4882a593Smuzhiyun unsigned char dev,
2230*4882a593Smuzhiyun unsigned char addr)
2231*4882a593Smuzhiyun {
2232*4882a593Smuzhiyun long t = 0x10000;
2233*4882a593Smuzhiyun
2234*4882a593Smuzhiyun outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
2235*4882a593Smuzhiyun outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
2236*4882a593Smuzhiyun while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
2237*4882a593Smuzhiyun return inb(ICEREG(ice, I2C_DATA));
2238*4882a593Smuzhiyun }
2239*4882a593Smuzhiyun
snd_ice1712_read_eeprom(struct snd_ice1712 * ice,const char * modelname)2240*4882a593Smuzhiyun static int snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
2241*4882a593Smuzhiyun const char *modelname)
2242*4882a593Smuzhiyun {
2243*4882a593Smuzhiyun int dev = ICE_I2C_EEPROM_ADDR; /* I2C EEPROM device address */
2244*4882a593Smuzhiyun unsigned int i, size;
2245*4882a593Smuzhiyun const struct snd_ice1712_card_info * const *tbl, *c;
2246*4882a593Smuzhiyun
2247*4882a593Smuzhiyun if (!modelname || !*modelname) {
2248*4882a593Smuzhiyun ice->eeprom.subvendor = 0;
2249*4882a593Smuzhiyun if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
2250*4882a593Smuzhiyun ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
2251*4882a593Smuzhiyun (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
2252*4882a593Smuzhiyun (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
2253*4882a593Smuzhiyun (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
2254*4882a593Smuzhiyun if (ice->eeprom.subvendor == 0 ||
2255*4882a593Smuzhiyun ice->eeprom.subvendor == (unsigned int)-1) {
2256*4882a593Smuzhiyun /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
2257*4882a593Smuzhiyun u16 vendor, device;
2258*4882a593Smuzhiyun pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
2259*4882a593Smuzhiyun pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
2260*4882a593Smuzhiyun ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
2261*4882a593Smuzhiyun if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
2262*4882a593Smuzhiyun dev_err(ice->card->dev,
2263*4882a593Smuzhiyun "No valid ID is found\n");
2264*4882a593Smuzhiyun return -ENXIO;
2265*4882a593Smuzhiyun }
2266*4882a593Smuzhiyun }
2267*4882a593Smuzhiyun }
2268*4882a593Smuzhiyun for (tbl = card_tables; *tbl; tbl++) {
2269*4882a593Smuzhiyun for (c = *tbl; c->subvendor; c++) {
2270*4882a593Smuzhiyun if (modelname && c->model && !strcmp(modelname, c->model)) {
2271*4882a593Smuzhiyun dev_info(ice->card->dev,
2272*4882a593Smuzhiyun "Using board model %s\n", c->name);
2273*4882a593Smuzhiyun ice->eeprom.subvendor = c->subvendor;
2274*4882a593Smuzhiyun } else if (c->subvendor != ice->eeprom.subvendor)
2275*4882a593Smuzhiyun continue;
2276*4882a593Smuzhiyun if (!c->eeprom_size || !c->eeprom_data)
2277*4882a593Smuzhiyun goto found;
2278*4882a593Smuzhiyun /* if the EEPROM is given by the driver, use it */
2279*4882a593Smuzhiyun dev_dbg(ice->card->dev, "using the defined eeprom..\n");
2280*4882a593Smuzhiyun ice->eeprom.version = 1;
2281*4882a593Smuzhiyun ice->eeprom.size = c->eeprom_size + 6;
2282*4882a593Smuzhiyun memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
2283*4882a593Smuzhiyun goto read_skipped;
2284*4882a593Smuzhiyun }
2285*4882a593Smuzhiyun }
2286*4882a593Smuzhiyun dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
2287*4882a593Smuzhiyun ice->eeprom.subvendor);
2288*4882a593Smuzhiyun
2289*4882a593Smuzhiyun found:
2290*4882a593Smuzhiyun ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
2291*4882a593Smuzhiyun if (ice->eeprom.size < 6)
2292*4882a593Smuzhiyun ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
2293*4882a593Smuzhiyun else if (ice->eeprom.size > 32) {
2294*4882a593Smuzhiyun dev_err(ice->card->dev,
2295*4882a593Smuzhiyun "invalid EEPROM (size = %i)\n", ice->eeprom.size);
2296*4882a593Smuzhiyun return -EIO;
2297*4882a593Smuzhiyun }
2298*4882a593Smuzhiyun ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
2299*4882a593Smuzhiyun if (ice->eeprom.version != 1) {
2300*4882a593Smuzhiyun dev_err(ice->card->dev, "invalid EEPROM version %i\n",
2301*4882a593Smuzhiyun ice->eeprom.version);
2302*4882a593Smuzhiyun /* return -EIO; */
2303*4882a593Smuzhiyun }
2304*4882a593Smuzhiyun size = ice->eeprom.size - 6;
2305*4882a593Smuzhiyun for (i = 0; i < size; i++)
2306*4882a593Smuzhiyun ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
2307*4882a593Smuzhiyun
2308*4882a593Smuzhiyun read_skipped:
2309*4882a593Smuzhiyun ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
2310*4882a593Smuzhiyun ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
2311*4882a593Smuzhiyun ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
2312*4882a593Smuzhiyun
2313*4882a593Smuzhiyun return 0;
2314*4882a593Smuzhiyun }
2315*4882a593Smuzhiyun
2316*4882a593Smuzhiyun
2317*4882a593Smuzhiyun
snd_ice1712_chip_init(struct snd_ice1712 * ice)2318*4882a593Smuzhiyun static int snd_ice1712_chip_init(struct snd_ice1712 *ice)
2319*4882a593Smuzhiyun {
2320*4882a593Smuzhiyun outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
2321*4882a593Smuzhiyun udelay(200);
2322*4882a593Smuzhiyun outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
2323*4882a593Smuzhiyun udelay(200);
2324*4882a593Smuzhiyun if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
2325*4882a593Smuzhiyun !ice->dxr_enable)
2326*4882a593Smuzhiyun /* Set eeprom value to limit active ADCs and DACs to 6;
2327*4882a593Smuzhiyun * Also disable AC97 as no hardware in standard 6fire card/box
2328*4882a593Smuzhiyun * Note: DXR extensions are not currently supported
2329*4882a593Smuzhiyun */
2330*4882a593Smuzhiyun ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
2331*4882a593Smuzhiyun pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
2332*4882a593Smuzhiyun pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
2333*4882a593Smuzhiyun pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
2334*4882a593Smuzhiyun pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
2335*4882a593Smuzhiyun if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24 &&
2336*4882a593Smuzhiyun ice->eeprom.subvendor != ICE1712_SUBDEVICE_STAUDIO_ADCIII) {
2337*4882a593Smuzhiyun ice->gpio.write_mask = ice->eeprom.gpiomask;
2338*4882a593Smuzhiyun ice->gpio.direction = ice->eeprom.gpiodir;
2339*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
2340*4882a593Smuzhiyun ice->eeprom.gpiomask);
2341*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
2342*4882a593Smuzhiyun ice->eeprom.gpiodir);
2343*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
2344*4882a593Smuzhiyun ice->eeprom.gpiostate);
2345*4882a593Smuzhiyun } else {
2346*4882a593Smuzhiyun ice->gpio.write_mask = 0xc0;
2347*4882a593Smuzhiyun ice->gpio.direction = 0xff;
2348*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
2349*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
2350*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
2351*4882a593Smuzhiyun ICE1712_STDSP24_CLOCK_BIT);
2352*4882a593Smuzhiyun }
2353*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
2354*4882a593Smuzhiyun if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
2355*4882a593Smuzhiyun outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
2356*4882a593Smuzhiyun udelay(100);
2357*4882a593Smuzhiyun outb(0, ICEREG(ice, AC97_CMD));
2358*4882a593Smuzhiyun udelay(200);
2359*4882a593Smuzhiyun snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
2360*4882a593Smuzhiyun }
2361*4882a593Smuzhiyun snd_ice1712_set_pro_rate(ice, 48000, 1);
2362*4882a593Smuzhiyun /* unmask used interrupts */
2363*4882a593Smuzhiyun outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
2364*4882a593Smuzhiyun ICE1712_IRQ_MPU2 : 0) |
2365*4882a593Smuzhiyun ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
2366*4882a593Smuzhiyun ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
2367*4882a593Smuzhiyun ICEREG(ice, IRQMASK));
2368*4882a593Smuzhiyun outb(0x00, ICEMT(ice, IRQ));
2369*4882a593Smuzhiyun
2370*4882a593Smuzhiyun return 0;
2371*4882a593Smuzhiyun }
2372*4882a593Smuzhiyun
snd_ice1712_spdif_build_controls(struct snd_ice1712 * ice)2373*4882a593Smuzhiyun int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
2374*4882a593Smuzhiyun {
2375*4882a593Smuzhiyun int err;
2376*4882a593Smuzhiyun struct snd_kcontrol *kctl;
2377*4882a593Smuzhiyun
2378*4882a593Smuzhiyun if (snd_BUG_ON(!ice->pcm_pro))
2379*4882a593Smuzhiyun return -EIO;
2380*4882a593Smuzhiyun err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
2381*4882a593Smuzhiyun if (err < 0)
2382*4882a593Smuzhiyun return err;
2383*4882a593Smuzhiyun kctl->id.device = ice->pcm_pro->device;
2384*4882a593Smuzhiyun err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
2385*4882a593Smuzhiyun if (err < 0)
2386*4882a593Smuzhiyun return err;
2387*4882a593Smuzhiyun kctl->id.device = ice->pcm_pro->device;
2388*4882a593Smuzhiyun err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
2389*4882a593Smuzhiyun if (err < 0)
2390*4882a593Smuzhiyun return err;
2391*4882a593Smuzhiyun kctl->id.device = ice->pcm_pro->device;
2392*4882a593Smuzhiyun err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
2393*4882a593Smuzhiyun if (err < 0)
2394*4882a593Smuzhiyun return err;
2395*4882a593Smuzhiyun kctl->id.device = ice->pcm_pro->device;
2396*4882a593Smuzhiyun ice->spdif.stream_ctl = kctl;
2397*4882a593Smuzhiyun return 0;
2398*4882a593Smuzhiyun }
2399*4882a593Smuzhiyun
2400*4882a593Smuzhiyun
snd_ice1712_build_controls(struct snd_ice1712 * ice)2401*4882a593Smuzhiyun static int snd_ice1712_build_controls(struct snd_ice1712 *ice)
2402*4882a593Smuzhiyun {
2403*4882a593Smuzhiyun int err;
2404*4882a593Smuzhiyun
2405*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
2406*4882a593Smuzhiyun if (err < 0)
2407*4882a593Smuzhiyun return err;
2408*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
2409*4882a593Smuzhiyun if (err < 0)
2410*4882a593Smuzhiyun return err;
2411*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
2412*4882a593Smuzhiyun if (err < 0)
2413*4882a593Smuzhiyun return err;
2414*4882a593Smuzhiyun
2415*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
2416*4882a593Smuzhiyun if (err < 0)
2417*4882a593Smuzhiyun return err;
2418*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
2419*4882a593Smuzhiyun if (err < 0)
2420*4882a593Smuzhiyun return err;
2421*4882a593Smuzhiyun
2422*4882a593Smuzhiyun if (ice->num_total_dacs > 0) {
2423*4882a593Smuzhiyun struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
2424*4882a593Smuzhiyun tmp.count = ice->num_total_dacs;
2425*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
2426*4882a593Smuzhiyun if (err < 0)
2427*4882a593Smuzhiyun return err;
2428*4882a593Smuzhiyun }
2429*4882a593Smuzhiyun
2430*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
2431*4882a593Smuzhiyun if (err < 0)
2432*4882a593Smuzhiyun return err;
2433*4882a593Smuzhiyun
2434*4882a593Smuzhiyun err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
2435*4882a593Smuzhiyun if (err < 0)
2436*4882a593Smuzhiyun return err;
2437*4882a593Smuzhiyun return snd_ctl_add(ice->card,
2438*4882a593Smuzhiyun snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
2439*4882a593Smuzhiyun }
2440*4882a593Smuzhiyun
snd_ice1712_free(struct snd_ice1712 * ice)2441*4882a593Smuzhiyun static int snd_ice1712_free(struct snd_ice1712 *ice)
2442*4882a593Smuzhiyun {
2443*4882a593Smuzhiyun if (!ice->port)
2444*4882a593Smuzhiyun goto __hw_end;
2445*4882a593Smuzhiyun /* mask all interrupts */
2446*4882a593Smuzhiyun outb(ICE1712_MULTI_CAPTURE | ICE1712_MULTI_PLAYBACK, ICEMT(ice, IRQ));
2447*4882a593Smuzhiyun outb(0xff, ICEREG(ice, IRQMASK));
2448*4882a593Smuzhiyun /* --- */
2449*4882a593Smuzhiyun __hw_end:
2450*4882a593Smuzhiyun if (ice->irq >= 0)
2451*4882a593Smuzhiyun free_irq(ice->irq, ice);
2452*4882a593Smuzhiyun
2453*4882a593Smuzhiyun if (ice->port)
2454*4882a593Smuzhiyun pci_release_regions(ice->pci);
2455*4882a593Smuzhiyun snd_ice1712_akm4xxx_free(ice);
2456*4882a593Smuzhiyun pci_disable_device(ice->pci);
2457*4882a593Smuzhiyun kfree(ice->spec);
2458*4882a593Smuzhiyun kfree(ice);
2459*4882a593Smuzhiyun return 0;
2460*4882a593Smuzhiyun }
2461*4882a593Smuzhiyun
snd_ice1712_dev_free(struct snd_device * device)2462*4882a593Smuzhiyun static int snd_ice1712_dev_free(struct snd_device *device)
2463*4882a593Smuzhiyun {
2464*4882a593Smuzhiyun struct snd_ice1712 *ice = device->device_data;
2465*4882a593Smuzhiyun return snd_ice1712_free(ice);
2466*4882a593Smuzhiyun }
2467*4882a593Smuzhiyun
snd_ice1712_create(struct snd_card * card,struct pci_dev * pci,const char * modelname,int omni,int cs8427_timeout,int dxr_enable,struct snd_ice1712 ** r_ice1712)2468*4882a593Smuzhiyun static int snd_ice1712_create(struct snd_card *card,
2469*4882a593Smuzhiyun struct pci_dev *pci,
2470*4882a593Smuzhiyun const char *modelname,
2471*4882a593Smuzhiyun int omni,
2472*4882a593Smuzhiyun int cs8427_timeout,
2473*4882a593Smuzhiyun int dxr_enable,
2474*4882a593Smuzhiyun struct snd_ice1712 **r_ice1712)
2475*4882a593Smuzhiyun {
2476*4882a593Smuzhiyun struct snd_ice1712 *ice;
2477*4882a593Smuzhiyun int err;
2478*4882a593Smuzhiyun static const struct snd_device_ops ops = {
2479*4882a593Smuzhiyun .dev_free = snd_ice1712_dev_free,
2480*4882a593Smuzhiyun };
2481*4882a593Smuzhiyun
2482*4882a593Smuzhiyun *r_ice1712 = NULL;
2483*4882a593Smuzhiyun
2484*4882a593Smuzhiyun /* enable PCI device */
2485*4882a593Smuzhiyun err = pci_enable_device(pci);
2486*4882a593Smuzhiyun if (err < 0)
2487*4882a593Smuzhiyun return err;
2488*4882a593Smuzhiyun /* check, if we can restrict PCI DMA transfers to 28 bits */
2489*4882a593Smuzhiyun if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
2490*4882a593Smuzhiyun dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
2491*4882a593Smuzhiyun dev_err(card->dev,
2492*4882a593Smuzhiyun "architecture does not support 28bit PCI busmaster DMA\n");
2493*4882a593Smuzhiyun pci_disable_device(pci);
2494*4882a593Smuzhiyun return -ENXIO;
2495*4882a593Smuzhiyun }
2496*4882a593Smuzhiyun
2497*4882a593Smuzhiyun ice = kzalloc(sizeof(*ice), GFP_KERNEL);
2498*4882a593Smuzhiyun if (ice == NULL) {
2499*4882a593Smuzhiyun pci_disable_device(pci);
2500*4882a593Smuzhiyun return -ENOMEM;
2501*4882a593Smuzhiyun }
2502*4882a593Smuzhiyun ice->omni = omni ? 1 : 0;
2503*4882a593Smuzhiyun if (cs8427_timeout < 1)
2504*4882a593Smuzhiyun cs8427_timeout = 1;
2505*4882a593Smuzhiyun else if (cs8427_timeout > 1000)
2506*4882a593Smuzhiyun cs8427_timeout = 1000;
2507*4882a593Smuzhiyun ice->cs8427_timeout = cs8427_timeout;
2508*4882a593Smuzhiyun ice->dxr_enable = dxr_enable;
2509*4882a593Smuzhiyun spin_lock_init(&ice->reg_lock);
2510*4882a593Smuzhiyun mutex_init(&ice->gpio_mutex);
2511*4882a593Smuzhiyun mutex_init(&ice->i2c_mutex);
2512*4882a593Smuzhiyun mutex_init(&ice->open_mutex);
2513*4882a593Smuzhiyun ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
2514*4882a593Smuzhiyun ice->gpio.get_mask = snd_ice1712_get_gpio_mask;
2515*4882a593Smuzhiyun ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
2516*4882a593Smuzhiyun ice->gpio.get_dir = snd_ice1712_get_gpio_dir;
2517*4882a593Smuzhiyun ice->gpio.set_data = snd_ice1712_set_gpio_data;
2518*4882a593Smuzhiyun ice->gpio.get_data = snd_ice1712_get_gpio_data;
2519*4882a593Smuzhiyun
2520*4882a593Smuzhiyun ice->spdif.cs8403_bits =
2521*4882a593Smuzhiyun ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
2522*4882a593Smuzhiyun 0x10 | /* no emphasis */
2523*4882a593Smuzhiyun 0x20); /* PCM encoder/decoder */
2524*4882a593Smuzhiyun ice->card = card;
2525*4882a593Smuzhiyun ice->pci = pci;
2526*4882a593Smuzhiyun ice->irq = -1;
2527*4882a593Smuzhiyun pci_set_master(pci);
2528*4882a593Smuzhiyun /* disable legacy emulation */
2529*4882a593Smuzhiyun pci_write_config_word(ice->pci, 0x40, 0x807f);
2530*4882a593Smuzhiyun pci_write_config_word(ice->pci, 0x42, 0x0006);
2531*4882a593Smuzhiyun snd_ice1712_proc_init(ice);
2532*4882a593Smuzhiyun
2533*4882a593Smuzhiyun card->private_data = ice;
2534*4882a593Smuzhiyun
2535*4882a593Smuzhiyun err = pci_request_regions(pci, "ICE1712");
2536*4882a593Smuzhiyun if (err < 0) {
2537*4882a593Smuzhiyun kfree(ice);
2538*4882a593Smuzhiyun pci_disable_device(pci);
2539*4882a593Smuzhiyun return err;
2540*4882a593Smuzhiyun }
2541*4882a593Smuzhiyun ice->port = pci_resource_start(pci, 0);
2542*4882a593Smuzhiyun ice->ddma_port = pci_resource_start(pci, 1);
2543*4882a593Smuzhiyun ice->dmapath_port = pci_resource_start(pci, 2);
2544*4882a593Smuzhiyun ice->profi_port = pci_resource_start(pci, 3);
2545*4882a593Smuzhiyun
2546*4882a593Smuzhiyun if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
2547*4882a593Smuzhiyun KBUILD_MODNAME, ice)) {
2548*4882a593Smuzhiyun dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2549*4882a593Smuzhiyun snd_ice1712_free(ice);
2550*4882a593Smuzhiyun return -EIO;
2551*4882a593Smuzhiyun }
2552*4882a593Smuzhiyun
2553*4882a593Smuzhiyun ice->irq = pci->irq;
2554*4882a593Smuzhiyun card->sync_irq = ice->irq;
2555*4882a593Smuzhiyun
2556*4882a593Smuzhiyun if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
2557*4882a593Smuzhiyun snd_ice1712_free(ice);
2558*4882a593Smuzhiyun return -EIO;
2559*4882a593Smuzhiyun }
2560*4882a593Smuzhiyun if (snd_ice1712_chip_init(ice) < 0) {
2561*4882a593Smuzhiyun snd_ice1712_free(ice);
2562*4882a593Smuzhiyun return -EIO;
2563*4882a593Smuzhiyun }
2564*4882a593Smuzhiyun
2565*4882a593Smuzhiyun err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
2566*4882a593Smuzhiyun if (err < 0) {
2567*4882a593Smuzhiyun snd_ice1712_free(ice);
2568*4882a593Smuzhiyun return err;
2569*4882a593Smuzhiyun }
2570*4882a593Smuzhiyun
2571*4882a593Smuzhiyun *r_ice1712 = ice;
2572*4882a593Smuzhiyun return 0;
2573*4882a593Smuzhiyun }
2574*4882a593Smuzhiyun
2575*4882a593Smuzhiyun
2576*4882a593Smuzhiyun /*
2577*4882a593Smuzhiyun *
2578*4882a593Smuzhiyun * Registration
2579*4882a593Smuzhiyun *
2580*4882a593Smuzhiyun */
2581*4882a593Smuzhiyun
2582*4882a593Smuzhiyun static struct snd_ice1712_card_info no_matched;
2583*4882a593Smuzhiyun
snd_ice1712_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2584*4882a593Smuzhiyun static int snd_ice1712_probe(struct pci_dev *pci,
2585*4882a593Smuzhiyun const struct pci_device_id *pci_id)
2586*4882a593Smuzhiyun {
2587*4882a593Smuzhiyun static int dev;
2588*4882a593Smuzhiyun struct snd_card *card;
2589*4882a593Smuzhiyun struct snd_ice1712 *ice;
2590*4882a593Smuzhiyun int pcm_dev = 0, err;
2591*4882a593Smuzhiyun const struct snd_ice1712_card_info * const *tbl, *c;
2592*4882a593Smuzhiyun
2593*4882a593Smuzhiyun if (dev >= SNDRV_CARDS)
2594*4882a593Smuzhiyun return -ENODEV;
2595*4882a593Smuzhiyun if (!enable[dev]) {
2596*4882a593Smuzhiyun dev++;
2597*4882a593Smuzhiyun return -ENOENT;
2598*4882a593Smuzhiyun }
2599*4882a593Smuzhiyun
2600*4882a593Smuzhiyun err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2601*4882a593Smuzhiyun 0, &card);
2602*4882a593Smuzhiyun if (err < 0)
2603*4882a593Smuzhiyun return err;
2604*4882a593Smuzhiyun
2605*4882a593Smuzhiyun strcpy(card->driver, "ICE1712");
2606*4882a593Smuzhiyun strcpy(card->shortname, "ICEnsemble ICE1712");
2607*4882a593Smuzhiyun
2608*4882a593Smuzhiyun err = snd_ice1712_create(card, pci, model[dev], omni[dev],
2609*4882a593Smuzhiyun cs8427_timeout[dev], dxr_enable[dev], &ice);
2610*4882a593Smuzhiyun if (err < 0) {
2611*4882a593Smuzhiyun snd_card_free(card);
2612*4882a593Smuzhiyun return err;
2613*4882a593Smuzhiyun }
2614*4882a593Smuzhiyun
2615*4882a593Smuzhiyun for (tbl = card_tables; *tbl; tbl++) {
2616*4882a593Smuzhiyun for (c = *tbl; c->subvendor; c++) {
2617*4882a593Smuzhiyun if (c->subvendor == ice->eeprom.subvendor) {
2618*4882a593Smuzhiyun ice->card_info = c;
2619*4882a593Smuzhiyun strcpy(card->shortname, c->name);
2620*4882a593Smuzhiyun if (c->driver) /* specific driver? */
2621*4882a593Smuzhiyun strcpy(card->driver, c->driver);
2622*4882a593Smuzhiyun if (c->chip_init) {
2623*4882a593Smuzhiyun err = c->chip_init(ice);
2624*4882a593Smuzhiyun if (err < 0) {
2625*4882a593Smuzhiyun snd_card_free(card);
2626*4882a593Smuzhiyun return err;
2627*4882a593Smuzhiyun }
2628*4882a593Smuzhiyun }
2629*4882a593Smuzhiyun goto __found;
2630*4882a593Smuzhiyun }
2631*4882a593Smuzhiyun }
2632*4882a593Smuzhiyun }
2633*4882a593Smuzhiyun c = &no_matched;
2634*4882a593Smuzhiyun __found:
2635*4882a593Smuzhiyun
2636*4882a593Smuzhiyun err = snd_ice1712_pcm_profi(ice, pcm_dev++);
2637*4882a593Smuzhiyun if (err < 0) {
2638*4882a593Smuzhiyun snd_card_free(card);
2639*4882a593Smuzhiyun return err;
2640*4882a593Smuzhiyun }
2641*4882a593Smuzhiyun
2642*4882a593Smuzhiyun if (ice_has_con_ac97(ice)) {
2643*4882a593Smuzhiyun err = snd_ice1712_pcm(ice, pcm_dev++);
2644*4882a593Smuzhiyun if (err < 0) {
2645*4882a593Smuzhiyun snd_card_free(card);
2646*4882a593Smuzhiyun return err;
2647*4882a593Smuzhiyun }
2648*4882a593Smuzhiyun }
2649*4882a593Smuzhiyun
2650*4882a593Smuzhiyun err = snd_ice1712_ac97_mixer(ice);
2651*4882a593Smuzhiyun if (err < 0) {
2652*4882a593Smuzhiyun snd_card_free(card);
2653*4882a593Smuzhiyun return err;
2654*4882a593Smuzhiyun }
2655*4882a593Smuzhiyun
2656*4882a593Smuzhiyun err = snd_ice1712_build_controls(ice);
2657*4882a593Smuzhiyun if (err < 0) {
2658*4882a593Smuzhiyun snd_card_free(card);
2659*4882a593Smuzhiyun return err;
2660*4882a593Smuzhiyun }
2661*4882a593Smuzhiyun
2662*4882a593Smuzhiyun if (c->build_controls) {
2663*4882a593Smuzhiyun err = c->build_controls(ice);
2664*4882a593Smuzhiyun if (err < 0) {
2665*4882a593Smuzhiyun snd_card_free(card);
2666*4882a593Smuzhiyun return err;
2667*4882a593Smuzhiyun }
2668*4882a593Smuzhiyun }
2669*4882a593Smuzhiyun
2670*4882a593Smuzhiyun if (ice_has_con_ac97(ice)) {
2671*4882a593Smuzhiyun err = snd_ice1712_pcm_ds(ice, pcm_dev++);
2672*4882a593Smuzhiyun if (err < 0) {
2673*4882a593Smuzhiyun snd_card_free(card);
2674*4882a593Smuzhiyun return err;
2675*4882a593Smuzhiyun }
2676*4882a593Smuzhiyun }
2677*4882a593Smuzhiyun
2678*4882a593Smuzhiyun if (!c->no_mpu401) {
2679*4882a593Smuzhiyun err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
2680*4882a593Smuzhiyun ICEREG(ice, MPU1_CTRL),
2681*4882a593Smuzhiyun c->mpu401_1_info_flags |
2682*4882a593Smuzhiyun MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2683*4882a593Smuzhiyun -1, &ice->rmidi[0]);
2684*4882a593Smuzhiyun if (err < 0) {
2685*4882a593Smuzhiyun snd_card_free(card);
2686*4882a593Smuzhiyun return err;
2687*4882a593Smuzhiyun }
2688*4882a593Smuzhiyun if (c->mpu401_1_name)
2689*4882a593Smuzhiyun /* Preferred name available in card_info */
2690*4882a593Smuzhiyun snprintf(ice->rmidi[0]->name,
2691*4882a593Smuzhiyun sizeof(ice->rmidi[0]->name),
2692*4882a593Smuzhiyun "%s %d", c->mpu401_1_name, card->number);
2693*4882a593Smuzhiyun
2694*4882a593Smuzhiyun if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
2695*4882a593Smuzhiyun /* 2nd port used */
2696*4882a593Smuzhiyun err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
2697*4882a593Smuzhiyun ICEREG(ice, MPU2_CTRL),
2698*4882a593Smuzhiyun c->mpu401_2_info_flags |
2699*4882a593Smuzhiyun MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2700*4882a593Smuzhiyun -1, &ice->rmidi[1]);
2701*4882a593Smuzhiyun
2702*4882a593Smuzhiyun if (err < 0) {
2703*4882a593Smuzhiyun snd_card_free(card);
2704*4882a593Smuzhiyun return err;
2705*4882a593Smuzhiyun }
2706*4882a593Smuzhiyun if (c->mpu401_2_name)
2707*4882a593Smuzhiyun /* Preferred name available in card_info */
2708*4882a593Smuzhiyun snprintf(ice->rmidi[1]->name,
2709*4882a593Smuzhiyun sizeof(ice->rmidi[1]->name),
2710*4882a593Smuzhiyun "%s %d", c->mpu401_2_name,
2711*4882a593Smuzhiyun card->number);
2712*4882a593Smuzhiyun }
2713*4882a593Smuzhiyun }
2714*4882a593Smuzhiyun
2715*4882a593Smuzhiyun snd_ice1712_set_input_clock_source(ice, 0);
2716*4882a593Smuzhiyun
2717*4882a593Smuzhiyun sprintf(card->longname, "%s at 0x%lx, irq %i",
2718*4882a593Smuzhiyun card->shortname, ice->port, ice->irq);
2719*4882a593Smuzhiyun
2720*4882a593Smuzhiyun err = snd_card_register(card);
2721*4882a593Smuzhiyun if (err < 0) {
2722*4882a593Smuzhiyun snd_card_free(card);
2723*4882a593Smuzhiyun return err;
2724*4882a593Smuzhiyun }
2725*4882a593Smuzhiyun pci_set_drvdata(pci, card);
2726*4882a593Smuzhiyun dev++;
2727*4882a593Smuzhiyun return 0;
2728*4882a593Smuzhiyun }
2729*4882a593Smuzhiyun
snd_ice1712_remove(struct pci_dev * pci)2730*4882a593Smuzhiyun static void snd_ice1712_remove(struct pci_dev *pci)
2731*4882a593Smuzhiyun {
2732*4882a593Smuzhiyun struct snd_card *card = pci_get_drvdata(pci);
2733*4882a593Smuzhiyun struct snd_ice1712 *ice = card->private_data;
2734*4882a593Smuzhiyun
2735*4882a593Smuzhiyun if (ice->card_info && ice->card_info->chip_exit)
2736*4882a593Smuzhiyun ice->card_info->chip_exit(ice);
2737*4882a593Smuzhiyun snd_card_free(card);
2738*4882a593Smuzhiyun }
2739*4882a593Smuzhiyun
2740*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
snd_ice1712_suspend(struct device * dev)2741*4882a593Smuzhiyun static int snd_ice1712_suspend(struct device *dev)
2742*4882a593Smuzhiyun {
2743*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
2744*4882a593Smuzhiyun struct snd_ice1712 *ice = card->private_data;
2745*4882a593Smuzhiyun
2746*4882a593Smuzhiyun if (!ice->pm_suspend_enabled)
2747*4882a593Smuzhiyun return 0;
2748*4882a593Smuzhiyun
2749*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2750*4882a593Smuzhiyun
2751*4882a593Smuzhiyun snd_ac97_suspend(ice->ac97);
2752*4882a593Smuzhiyun
2753*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
2754*4882a593Smuzhiyun ice->pm_saved_is_spdif_master = is_spdif_master(ice);
2755*4882a593Smuzhiyun ice->pm_saved_spdif_ctrl = inw(ICEMT(ice, ROUTE_SPDOUT));
2756*4882a593Smuzhiyun ice->pm_saved_route = inw(ICEMT(ice, ROUTE_PSDOUT03));
2757*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
2758*4882a593Smuzhiyun
2759*4882a593Smuzhiyun if (ice->pm_suspend)
2760*4882a593Smuzhiyun ice->pm_suspend(ice);
2761*4882a593Smuzhiyun return 0;
2762*4882a593Smuzhiyun }
2763*4882a593Smuzhiyun
snd_ice1712_resume(struct device * dev)2764*4882a593Smuzhiyun static int snd_ice1712_resume(struct device *dev)
2765*4882a593Smuzhiyun {
2766*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
2767*4882a593Smuzhiyun struct snd_ice1712 *ice = card->private_data;
2768*4882a593Smuzhiyun int rate;
2769*4882a593Smuzhiyun
2770*4882a593Smuzhiyun if (!ice->pm_suspend_enabled)
2771*4882a593Smuzhiyun return 0;
2772*4882a593Smuzhiyun
2773*4882a593Smuzhiyun if (ice->cur_rate)
2774*4882a593Smuzhiyun rate = ice->cur_rate;
2775*4882a593Smuzhiyun else
2776*4882a593Smuzhiyun rate = PRO_RATE_DEFAULT;
2777*4882a593Smuzhiyun
2778*4882a593Smuzhiyun if (snd_ice1712_chip_init(ice) < 0) {
2779*4882a593Smuzhiyun snd_card_disconnect(card);
2780*4882a593Smuzhiyun return -EIO;
2781*4882a593Smuzhiyun }
2782*4882a593Smuzhiyun
2783*4882a593Smuzhiyun ice->cur_rate = rate;
2784*4882a593Smuzhiyun
2785*4882a593Smuzhiyun if (ice->pm_resume)
2786*4882a593Smuzhiyun ice->pm_resume(ice);
2787*4882a593Smuzhiyun
2788*4882a593Smuzhiyun if (ice->pm_saved_is_spdif_master) {
2789*4882a593Smuzhiyun /* switching to external clock via SPDIF */
2790*4882a593Smuzhiyun spin_lock_irq(&ice->reg_lock);
2791*4882a593Smuzhiyun outb(inb(ICEMT(ice, RATE)) | ICE1712_SPDIF_MASTER,
2792*4882a593Smuzhiyun ICEMT(ice, RATE));
2793*4882a593Smuzhiyun spin_unlock_irq(&ice->reg_lock);
2794*4882a593Smuzhiyun snd_ice1712_set_input_clock_source(ice, 1);
2795*4882a593Smuzhiyun } else {
2796*4882a593Smuzhiyun /* internal on-card clock */
2797*4882a593Smuzhiyun snd_ice1712_set_pro_rate(ice, rate, 1);
2798*4882a593Smuzhiyun snd_ice1712_set_input_clock_source(ice, 0);
2799*4882a593Smuzhiyun }
2800*4882a593Smuzhiyun
2801*4882a593Smuzhiyun outw(ice->pm_saved_spdif_ctrl, ICEMT(ice, ROUTE_SPDOUT));
2802*4882a593Smuzhiyun outw(ice->pm_saved_route, ICEMT(ice, ROUTE_PSDOUT03));
2803*4882a593Smuzhiyun
2804*4882a593Smuzhiyun snd_ac97_resume(ice->ac97);
2805*4882a593Smuzhiyun
2806*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2807*4882a593Smuzhiyun return 0;
2808*4882a593Smuzhiyun }
2809*4882a593Smuzhiyun
2810*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(snd_ice1712_pm, snd_ice1712_suspend, snd_ice1712_resume);
2811*4882a593Smuzhiyun #define SND_VT1712_PM_OPS &snd_ice1712_pm
2812*4882a593Smuzhiyun #else
2813*4882a593Smuzhiyun #define SND_VT1712_PM_OPS NULL
2814*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
2815*4882a593Smuzhiyun
2816*4882a593Smuzhiyun static struct pci_driver ice1712_driver = {
2817*4882a593Smuzhiyun .name = KBUILD_MODNAME,
2818*4882a593Smuzhiyun .id_table = snd_ice1712_ids,
2819*4882a593Smuzhiyun .probe = snd_ice1712_probe,
2820*4882a593Smuzhiyun .remove = snd_ice1712_remove,
2821*4882a593Smuzhiyun .driver = {
2822*4882a593Smuzhiyun .pm = SND_VT1712_PM_OPS,
2823*4882a593Smuzhiyun },
2824*4882a593Smuzhiyun };
2825*4882a593Smuzhiyun
2826*4882a593Smuzhiyun module_pci_driver(ice1712_driver);
2827