1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun #ifndef __SOUND_DELTA_H 3*4882a593Smuzhiyun #define __SOUND_DELTA_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * ALSA driver for ICEnsemble ICE1712 (Envy24) 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Lowlevel functions for M-Audio Delta 1010, 44, 66, Dio2496, Audiophile 9*4882a593Smuzhiyun * Digigram VX442 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define DELTA_DEVICE_DESC \ 15*4882a593Smuzhiyun "{MidiMan M Audio,Delta 1010},"\ 16*4882a593Smuzhiyun "{MidiMan M Audio,Delta 1010LT},"\ 17*4882a593Smuzhiyun "{MidiMan M Audio,Delta DiO 2496},"\ 18*4882a593Smuzhiyun "{MidiMan M Audio,Delta 66},"\ 19*4882a593Smuzhiyun "{MidiMan M Audio,Delta 44},"\ 20*4882a593Smuzhiyun "{MidiMan M Audio,Delta 410},"\ 21*4882a593Smuzhiyun "{MidiMan M Audio,Audiophile 24/96},"\ 22*4882a593Smuzhiyun "{Digigram,VX442},"\ 23*4882a593Smuzhiyun "{Lionstracs,Mediastation},"\ 24*4882a593Smuzhiyun "{Edirol,DA2496}," 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_DELTA1010 0x121430d6 27*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_DELTA1010E 0xff1430d6 28*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_DELTADIO2496 0x121431d6 29*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_DELTA66 0x121432d6 30*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_DELTA66E 0xff1432d6 31*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_DELTA44 0x121433d6 32*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_AUDIOPHILE 0x121434d6 33*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_DELTA410 0x121438d6 34*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_DELTA1010LT 0x12143bd6 35*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_VX442 0x12143cd6 36*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_MEDIASTATION 0x694c0100 37*4882a593Smuzhiyun #define ICE1712_SUBDEVICE_EDIROLDA2496 0xce164010 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* entry point */ 40*4882a593Smuzhiyun extern struct snd_ice1712_card_info snd_ice1712_delta_cards[]; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * MidiMan M-Audio Delta GPIO definitions 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* MidiMan M-Audio Delta shared pins */ 48*4882a593Smuzhiyun #define ICE1712_DELTA_DFS 0x01 /* fast/slow sample rate mode */ 49*4882a593Smuzhiyun /* (>48kHz must be 1) */ 50*4882a593Smuzhiyun #define ICE1712_DELTA_SPDIF_IN_STAT 0x02 51*4882a593Smuzhiyun /* S/PDIF input status */ 52*4882a593Smuzhiyun /* 0 = valid signal is present */ 53*4882a593Smuzhiyun /* all except Delta44 */ 54*4882a593Smuzhiyun /* look to CS8414 datasheet */ 55*4882a593Smuzhiyun #define ICE1712_DELTA_SPDIF_OUT_STAT_CLOCK 0x04 56*4882a593Smuzhiyun /* S/PDIF output status clock */ 57*4882a593Smuzhiyun /* (writing on rising edge - 0->1) */ 58*4882a593Smuzhiyun /* all except Delta44 */ 59*4882a593Smuzhiyun /* look to CS8404A datasheet */ 60*4882a593Smuzhiyun #define ICE1712_DELTA_SPDIF_OUT_STAT_DATA 0x08 61*4882a593Smuzhiyun /* S/PDIF output status data */ 62*4882a593Smuzhiyun /* all except Delta44 */ 63*4882a593Smuzhiyun /* look to CS8404A datasheet */ 64*4882a593Smuzhiyun /* MidiMan M-Audio DeltaDiO */ 65*4882a593Smuzhiyun /* 0x01 = DFS */ 66*4882a593Smuzhiyun /* 0x02 = SPDIF_IN_STAT */ 67*4882a593Smuzhiyun /* 0x04 = SPDIF_OUT_STAT_CLOCK */ 68*4882a593Smuzhiyun /* 0x08 = SPDIF_OUT_STAT_DATA */ 69*4882a593Smuzhiyun #define ICE1712_DELTA_SPDIF_INPUT_SELECT 0x10 70*4882a593Smuzhiyun /* coaxial (0), optical (1) */ 71*4882a593Smuzhiyun /* S/PDIF input select*/ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* MidiMan M-Audio Delta1010 */ 74*4882a593Smuzhiyun /* 0x01 = DFS */ 75*4882a593Smuzhiyun /* 0x02 = SPDIF_IN_STAT */ 76*4882a593Smuzhiyun /* 0x04 = SPDIF_OUT_STAT_CLOCK */ 77*4882a593Smuzhiyun /* 0x08 = SPDIF_OUT_STAT_DATA */ 78*4882a593Smuzhiyun #define ICE1712_DELTA_WORD_CLOCK_SELECT 0x10 79*4882a593Smuzhiyun /* 1 - clock are taken from S/PDIF input */ 80*4882a593Smuzhiyun /* 0 - clock are taken from Word Clock input */ 81*4882a593Smuzhiyun /* affected SPMCLKIN pin of Envy24 */ 82*4882a593Smuzhiyun #define ICE1712_DELTA_WORD_CLOCK_STATUS 0x20 83*4882a593Smuzhiyun /* 0 = valid word clock signal is present */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* MidiMan M-Audio Delta66 */ 86*4882a593Smuzhiyun /* 0x01 = DFS */ 87*4882a593Smuzhiyun /* 0x02 = SPDIF_IN_STAT */ 88*4882a593Smuzhiyun /* 0x04 = SPDIF_OUT_STAT_CLOCK */ 89*4882a593Smuzhiyun /* 0x08 = SPDIF_OUT_STAT_DATA */ 90*4882a593Smuzhiyun #define ICE1712_DELTA_CODEC_SERIAL_DATA 0x10 91*4882a593Smuzhiyun /* AKM4524 serial data */ 92*4882a593Smuzhiyun #define ICE1712_DELTA_CODEC_SERIAL_CLOCK 0x20 93*4882a593Smuzhiyun /* AKM4524 serial clock */ 94*4882a593Smuzhiyun /* (writing on rising edge - 0->1 */ 95*4882a593Smuzhiyun #define ICE1712_DELTA_CODEC_CHIP_A 0x40 96*4882a593Smuzhiyun #define ICE1712_DELTA_CODEC_CHIP_B 0x80 97*4882a593Smuzhiyun /* 1 - select chip A or B */ 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* MidiMan M-Audio Delta44 */ 100*4882a593Smuzhiyun /* 0x01 = DFS */ 101*4882a593Smuzhiyun /* 0x10 = CODEC_SERIAL_DATA */ 102*4882a593Smuzhiyun /* 0x20 = CODEC_SERIAL_CLOCK */ 103*4882a593Smuzhiyun /* 0x40 = CODEC_CHIP_A */ 104*4882a593Smuzhiyun /* 0x80 = CODEC_CHIP_B */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* MidiMan M-Audio Audiophile/Delta410 definitions */ 107*4882a593Smuzhiyun /* thanks to Kristof Pelckmans <Kristof.Pelckmans@antwerpen.be> for Delta410 info */ 108*4882a593Smuzhiyun /* 0x01 = DFS */ 109*4882a593Smuzhiyun #define ICE1712_DELTA_AP_CCLK 0x02 /* SPI clock */ 110*4882a593Smuzhiyun /* (clocking on rising edge - 0->1) */ 111*4882a593Smuzhiyun #define ICE1712_DELTA_AP_DIN 0x04 /* data input */ 112*4882a593Smuzhiyun #define ICE1712_DELTA_AP_DOUT 0x08 /* data output */ 113*4882a593Smuzhiyun #define ICE1712_DELTA_AP_CS_DIGITAL 0x10 /* CS8427 chip select */ 114*4882a593Smuzhiyun /* low signal = select */ 115*4882a593Smuzhiyun #define ICE1712_DELTA_AP_CS_CODEC 0x20 /* AK4528 (audiophile), AK4529 (Delta410) chip select */ 116*4882a593Smuzhiyun /* low signal = select */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* MidiMan M-Audio Delta1010LT definitions */ 119*4882a593Smuzhiyun /* thanks to Anders Johansson <ajh@watri.uwa.edu.au> */ 120*4882a593Smuzhiyun /* 0x01 = DFS */ 121*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_CCLK 0x02 /* SPI clock (AK4524 + CS8427) */ 122*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_DIN 0x04 /* data input (CS8427) */ 123*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_DOUT 0x08 /* data output (AK4524 + CS8427) */ 124*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_CS 0x70 /* mask for CS address */ 125*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_CS_CHIP_A 0x00 /* AK4524 #0 */ 126*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_CS_CHIP_B 0x10 /* AK4524 #1 */ 127*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_CS_CHIP_C 0x20 /* AK4524 #2 */ 128*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_CS_CHIP_D 0x30 /* AK4524 #3 */ 129*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_CS_CS8427 0x40 /* CS8427 */ 130*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_CS_NONE 0x50 /* nothing */ 131*4882a593Smuzhiyun #define ICE1712_DELTA_1010LT_WORDCLOCK 0x80 /* sample clock source: 0 = Word Clock Input, 1 = S/PDIF Input ??? */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* M-Audio Delta 66 rev. E definitions. 134*4882a593Smuzhiyun * Newer revisions of Delta 66 have CS8427 over SPI for 135*4882a593Smuzhiyun * S/PDIF transceiver instead of CS8404/CS8414. */ 136*4882a593Smuzhiyun /* 0x01 = DFS */ 137*4882a593Smuzhiyun #define ICE1712_DELTA_66E_CCLK 0x02 /* SPI clock */ 138*4882a593Smuzhiyun #define ICE1712_DELTA_66E_DIN 0x04 /* data input */ 139*4882a593Smuzhiyun #define ICE1712_DELTA_66E_DOUT 0x08 /* data output */ 140*4882a593Smuzhiyun #define ICE1712_DELTA_66E_CS_CS8427 0x10 /* chip select, low = CS8427 */ 141*4882a593Smuzhiyun #define ICE1712_DELTA_66E_CS_CHIP_A 0x20 /* AK4524 #0 */ 142*4882a593Smuzhiyun #define ICE1712_DELTA_66E_CS_CHIP_B 0x40 /* AK4524 #1 */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* Digigram VX442 definitions */ 145*4882a593Smuzhiyun #define ICE1712_VX442_CCLK 0x02 /* SPI clock */ 146*4882a593Smuzhiyun #define ICE1712_VX442_DIN 0x04 /* data input */ 147*4882a593Smuzhiyun #define ICE1712_VX442_DOUT 0x08 /* data output */ 148*4882a593Smuzhiyun #define ICE1712_VX442_CS_DIGITAL 0x10 /* chip select, low = CS8427 */ 149*4882a593Smuzhiyun #define ICE1712_VX442_CODEC_CHIP_A 0x20 /* select chip A */ 150*4882a593Smuzhiyun #define ICE1712_VX442_CODEC_CHIP_B 0x40 /* select chip B */ 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #endif /* __SOUND_DELTA_H */ 153