xref: /OK3568_Linux_fs/kernel/sound/pci/ice1712/delta.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *   ALSA driver for ICEnsemble ICE1712 (Envy24)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *   Lowlevel functions for M-Audio Delta 1010, 1010E, 44, 66, 66E, Dio2496,
6*4882a593Smuzhiyun  *			    Audiophile, Digigram VX442
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  *	Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/mutex.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <sound/core.h>
18*4882a593Smuzhiyun #include <sound/cs8427.h>
19*4882a593Smuzhiyun #include <sound/asoundef.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include "ice1712.h"
22*4882a593Smuzhiyun #include "delta.h"
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define SND_CS8403
25*4882a593Smuzhiyun #include <sound/cs8403.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun  * CS8427 via SPI mode (for Audiophile), emulated I2C
30*4882a593Smuzhiyun  */
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* send 8 bits */
ap_cs8427_write_byte(struct snd_ice1712 * ice,unsigned char data,unsigned char tmp)33*4882a593Smuzhiyun static void ap_cs8427_write_byte(struct snd_ice1712 *ice, unsigned char data, unsigned char tmp)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun 	int idx;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	for (idx = 7; idx >= 0; idx--) {
38*4882a593Smuzhiyun 		tmp &= ~(ICE1712_DELTA_AP_DOUT|ICE1712_DELTA_AP_CCLK);
39*4882a593Smuzhiyun 		if (data & (1 << idx))
40*4882a593Smuzhiyun 			tmp |= ICE1712_DELTA_AP_DOUT;
41*4882a593Smuzhiyun 		snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
42*4882a593Smuzhiyun 		udelay(5);
43*4882a593Smuzhiyun 		tmp |= ICE1712_DELTA_AP_CCLK;
44*4882a593Smuzhiyun 		snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
45*4882a593Smuzhiyun 		udelay(5);
46*4882a593Smuzhiyun 	}
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun /* read 8 bits */
ap_cs8427_read_byte(struct snd_ice1712 * ice,unsigned char tmp)50*4882a593Smuzhiyun static unsigned char ap_cs8427_read_byte(struct snd_ice1712 *ice, unsigned char tmp)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	unsigned char data = 0;
53*4882a593Smuzhiyun 	int idx;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	for (idx = 7; idx >= 0; idx--) {
56*4882a593Smuzhiyun 		tmp &= ~ICE1712_DELTA_AP_CCLK;
57*4882a593Smuzhiyun 		snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
58*4882a593Smuzhiyun 		udelay(5);
59*4882a593Smuzhiyun 		if (snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & ICE1712_DELTA_AP_DIN)
60*4882a593Smuzhiyun 			data |= 1 << idx;
61*4882a593Smuzhiyun 		tmp |= ICE1712_DELTA_AP_CCLK;
62*4882a593Smuzhiyun 		snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
63*4882a593Smuzhiyun 		udelay(5);
64*4882a593Smuzhiyun 	}
65*4882a593Smuzhiyun 	return data;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* assert chip select */
ap_cs8427_codec_select(struct snd_ice1712 * ice)69*4882a593Smuzhiyun static unsigned char ap_cs8427_codec_select(struct snd_ice1712 *ice)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	unsigned char tmp;
72*4882a593Smuzhiyun 	tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
73*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
74*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010E:
75*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010LT:
76*4882a593Smuzhiyun 		tmp &= ~ICE1712_DELTA_1010LT_CS;
77*4882a593Smuzhiyun 		tmp |= ICE1712_DELTA_1010LT_CCLK | ICE1712_DELTA_1010LT_CS_CS8427;
78*4882a593Smuzhiyun 		break;
79*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_AUDIOPHILE:
80*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA410:
81*4882a593Smuzhiyun 		tmp |= ICE1712_DELTA_AP_CCLK | ICE1712_DELTA_AP_CS_CODEC;
82*4882a593Smuzhiyun 		tmp &= ~ICE1712_DELTA_AP_CS_DIGITAL;
83*4882a593Smuzhiyun 		break;
84*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66E:
85*4882a593Smuzhiyun 		tmp |= ICE1712_DELTA_66E_CCLK | ICE1712_DELTA_66E_CS_CHIP_A |
86*4882a593Smuzhiyun 		       ICE1712_DELTA_66E_CS_CHIP_B;
87*4882a593Smuzhiyun 		tmp &= ~ICE1712_DELTA_66E_CS_CS8427;
88*4882a593Smuzhiyun 		break;
89*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_VX442:
90*4882a593Smuzhiyun 		tmp |= ICE1712_VX442_CCLK | ICE1712_VX442_CODEC_CHIP_A | ICE1712_VX442_CODEC_CHIP_B;
91*4882a593Smuzhiyun 		tmp &= ~ICE1712_VX442_CS_DIGITAL;
92*4882a593Smuzhiyun 		break;
93*4882a593Smuzhiyun 	}
94*4882a593Smuzhiyun 	snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
95*4882a593Smuzhiyun 	udelay(5);
96*4882a593Smuzhiyun 	return tmp;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /* deassert chip select */
ap_cs8427_codec_deassert(struct snd_ice1712 * ice,unsigned char tmp)100*4882a593Smuzhiyun static void ap_cs8427_codec_deassert(struct snd_ice1712 *ice, unsigned char tmp)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
103*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010E:
104*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010LT:
105*4882a593Smuzhiyun 		tmp &= ~ICE1712_DELTA_1010LT_CS;
106*4882a593Smuzhiyun 		tmp |= ICE1712_DELTA_1010LT_CS_NONE;
107*4882a593Smuzhiyun 		break;
108*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_AUDIOPHILE:
109*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA410:
110*4882a593Smuzhiyun 		tmp |= ICE1712_DELTA_AP_CS_DIGITAL;
111*4882a593Smuzhiyun 		break;
112*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66E:
113*4882a593Smuzhiyun 		tmp |= ICE1712_DELTA_66E_CS_CS8427;
114*4882a593Smuzhiyun 		break;
115*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_VX442:
116*4882a593Smuzhiyun 		tmp |= ICE1712_VX442_CS_DIGITAL;
117*4882a593Smuzhiyun 		break;
118*4882a593Smuzhiyun 	}
119*4882a593Smuzhiyun 	snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /* sequential write */
ap_cs8427_sendbytes(struct snd_i2c_device * device,unsigned char * bytes,int count)123*4882a593Smuzhiyun static int ap_cs8427_sendbytes(struct snd_i2c_device *device, unsigned char *bytes, int count)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	struct snd_ice1712 *ice = device->bus->private_data;
126*4882a593Smuzhiyun 	int res = count;
127*4882a593Smuzhiyun 	unsigned char tmp;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
130*4882a593Smuzhiyun 	tmp = ap_cs8427_codec_select(ice);
131*4882a593Smuzhiyun 	ap_cs8427_write_byte(ice, (device->addr << 1) | 0, tmp); /* address + write mode */
132*4882a593Smuzhiyun 	while (count-- > 0)
133*4882a593Smuzhiyun 		ap_cs8427_write_byte(ice, *bytes++, tmp);
134*4882a593Smuzhiyun 	ap_cs8427_codec_deassert(ice, tmp);
135*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
136*4882a593Smuzhiyun 	return res;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun /* sequential read */
ap_cs8427_readbytes(struct snd_i2c_device * device,unsigned char * bytes,int count)140*4882a593Smuzhiyun static int ap_cs8427_readbytes(struct snd_i2c_device *device, unsigned char *bytes, int count)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	struct snd_ice1712 *ice = device->bus->private_data;
143*4882a593Smuzhiyun 	int res = count;
144*4882a593Smuzhiyun 	unsigned char tmp;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
147*4882a593Smuzhiyun 	tmp = ap_cs8427_codec_select(ice);
148*4882a593Smuzhiyun 	ap_cs8427_write_byte(ice, (device->addr << 1) | 1, tmp); /* address + read mode */
149*4882a593Smuzhiyun 	while (count-- > 0)
150*4882a593Smuzhiyun 		*bytes++ = ap_cs8427_read_byte(ice, tmp);
151*4882a593Smuzhiyun 	ap_cs8427_codec_deassert(ice, tmp);
152*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
153*4882a593Smuzhiyun 	return res;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
ap_cs8427_probeaddr(struct snd_i2c_bus * bus,unsigned short addr)156*4882a593Smuzhiyun static int ap_cs8427_probeaddr(struct snd_i2c_bus *bus, unsigned short addr)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	if (addr == 0x10)
159*4882a593Smuzhiyun 		return 1;
160*4882a593Smuzhiyun 	return -ENOENT;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun static const struct snd_i2c_ops ap_cs8427_i2c_ops = {
164*4882a593Smuzhiyun 	.sendbytes = ap_cs8427_sendbytes,
165*4882a593Smuzhiyun 	.readbytes = ap_cs8427_readbytes,
166*4882a593Smuzhiyun 	.probeaddr = ap_cs8427_probeaddr,
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun /*
170*4882a593Smuzhiyun  */
171*4882a593Smuzhiyun 
snd_ice1712_delta_cs8403_spdif_write(struct snd_ice1712 * ice,unsigned char bits)172*4882a593Smuzhiyun static void snd_ice1712_delta_cs8403_spdif_write(struct snd_ice1712 *ice, unsigned char bits)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun 	unsigned char tmp, mask1, mask2;
175*4882a593Smuzhiyun 	int idx;
176*4882a593Smuzhiyun 	/* send byte to transmitter */
177*4882a593Smuzhiyun 	mask1 = ICE1712_DELTA_SPDIF_OUT_STAT_CLOCK;
178*4882a593Smuzhiyun 	mask2 = ICE1712_DELTA_SPDIF_OUT_STAT_DATA;
179*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
180*4882a593Smuzhiyun 	tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
181*4882a593Smuzhiyun 	for (idx = 7; idx >= 0; idx--) {
182*4882a593Smuzhiyun 		tmp &= ~(mask1 | mask2);
183*4882a593Smuzhiyun 		if (bits & (1 << idx))
184*4882a593Smuzhiyun 			tmp |= mask2;
185*4882a593Smuzhiyun 		snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
186*4882a593Smuzhiyun 		udelay(100);
187*4882a593Smuzhiyun 		tmp |= mask1;
188*4882a593Smuzhiyun 		snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
189*4882a593Smuzhiyun 		udelay(100);
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun 	tmp &= ~mask1;
192*4882a593Smuzhiyun 	snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
193*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 
delta_spdif_default_get(struct snd_ice1712 * ice,struct snd_ctl_elem_value * ucontrol)197*4882a593Smuzhiyun static void delta_spdif_default_get(struct snd_ice1712 *ice, struct snd_ctl_elem_value *ucontrol)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun 	snd_cs8403_decode_spdif_bits(&ucontrol->value.iec958, ice->spdif.cs8403_bits);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
delta_spdif_default_put(struct snd_ice1712 * ice,struct snd_ctl_elem_value * ucontrol)202*4882a593Smuzhiyun static int delta_spdif_default_put(struct snd_ice1712 *ice, struct snd_ctl_elem_value *ucontrol)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	unsigned int val;
205*4882a593Smuzhiyun 	int change;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	val = snd_cs8403_encode_spdif_bits(&ucontrol->value.iec958);
208*4882a593Smuzhiyun 	spin_lock_irq(&ice->reg_lock);
209*4882a593Smuzhiyun 	change = ice->spdif.cs8403_bits != val;
210*4882a593Smuzhiyun 	ice->spdif.cs8403_bits = val;
211*4882a593Smuzhiyun 	if (change && ice->playback_pro_substream == NULL) {
212*4882a593Smuzhiyun 		spin_unlock_irq(&ice->reg_lock);
213*4882a593Smuzhiyun 		snd_ice1712_delta_cs8403_spdif_write(ice, val);
214*4882a593Smuzhiyun 	} else {
215*4882a593Smuzhiyun 		spin_unlock_irq(&ice->reg_lock);
216*4882a593Smuzhiyun 	}
217*4882a593Smuzhiyun 	return change;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun 
delta_spdif_stream_get(struct snd_ice1712 * ice,struct snd_ctl_elem_value * ucontrol)220*4882a593Smuzhiyun static void delta_spdif_stream_get(struct snd_ice1712 *ice, struct snd_ctl_elem_value *ucontrol)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	snd_cs8403_decode_spdif_bits(&ucontrol->value.iec958, ice->spdif.cs8403_stream_bits);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun 
delta_spdif_stream_put(struct snd_ice1712 * ice,struct snd_ctl_elem_value * ucontrol)225*4882a593Smuzhiyun static int delta_spdif_stream_put(struct snd_ice1712 *ice, struct snd_ctl_elem_value *ucontrol)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun 	unsigned int val;
228*4882a593Smuzhiyun 	int change;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	val = snd_cs8403_encode_spdif_bits(&ucontrol->value.iec958);
231*4882a593Smuzhiyun 	spin_lock_irq(&ice->reg_lock);
232*4882a593Smuzhiyun 	change = ice->spdif.cs8403_stream_bits != val;
233*4882a593Smuzhiyun 	ice->spdif.cs8403_stream_bits = val;
234*4882a593Smuzhiyun 	if (change && ice->playback_pro_substream != NULL) {
235*4882a593Smuzhiyun 		spin_unlock_irq(&ice->reg_lock);
236*4882a593Smuzhiyun 		snd_ice1712_delta_cs8403_spdif_write(ice, val);
237*4882a593Smuzhiyun 	} else {
238*4882a593Smuzhiyun 		spin_unlock_irq(&ice->reg_lock);
239*4882a593Smuzhiyun 	}
240*4882a593Smuzhiyun 	return change;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun /*
245*4882a593Smuzhiyun  * AK4524 on Delta 44 and 66 to choose the chip mask
246*4882a593Smuzhiyun  */
delta_ak4524_lock(struct snd_akm4xxx * ak,int chip)247*4882a593Smuzhiyun static void delta_ak4524_lock(struct snd_akm4xxx *ak, int chip)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun         struct snd_ak4xxx_private *priv = (void *)ak->private_value[0];
250*4882a593Smuzhiyun         struct snd_ice1712 *ice = ak->private_data[0];
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
253*4882a593Smuzhiyun 	priv->cs_mask =
254*4882a593Smuzhiyun 	priv->cs_addr = chip == 0 ? ICE1712_DELTA_CODEC_CHIP_A :
255*4882a593Smuzhiyun 				    ICE1712_DELTA_CODEC_CHIP_B;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun /*
259*4882a593Smuzhiyun  * AK4524 on Delta1010LT to choose the chip address
260*4882a593Smuzhiyun  */
delta1010lt_ak4524_lock(struct snd_akm4xxx * ak,int chip)261*4882a593Smuzhiyun static void delta1010lt_ak4524_lock(struct snd_akm4xxx *ak, int chip)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun         struct snd_ak4xxx_private *priv = (void *)ak->private_value[0];
264*4882a593Smuzhiyun         struct snd_ice1712 *ice = ak->private_data[0];
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
267*4882a593Smuzhiyun 	priv->cs_mask = ICE1712_DELTA_1010LT_CS;
268*4882a593Smuzhiyun 	priv->cs_addr = chip << 4;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun /*
272*4882a593Smuzhiyun  * AK4524 on Delta66 rev E to choose the chip address
273*4882a593Smuzhiyun  */
delta66e_ak4524_lock(struct snd_akm4xxx * ak,int chip)274*4882a593Smuzhiyun static void delta66e_ak4524_lock(struct snd_akm4xxx *ak, int chip)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun 	struct snd_ak4xxx_private *priv = (void *)ak->private_value[0];
277*4882a593Smuzhiyun 	struct snd_ice1712 *ice = ak->private_data[0];
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
280*4882a593Smuzhiyun 	priv->cs_mask =
281*4882a593Smuzhiyun 	priv->cs_addr = chip == 0 ? ICE1712_DELTA_66E_CS_CHIP_A :
282*4882a593Smuzhiyun 				    ICE1712_DELTA_66E_CS_CHIP_B;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun /*
286*4882a593Smuzhiyun  * AK4528 on VX442 to choose the chip mask
287*4882a593Smuzhiyun  */
vx442_ak4524_lock(struct snd_akm4xxx * ak,int chip)288*4882a593Smuzhiyun static void vx442_ak4524_lock(struct snd_akm4xxx *ak, int chip)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun         struct snd_ak4xxx_private *priv = (void *)ak->private_value[0];
291*4882a593Smuzhiyun         struct snd_ice1712 *ice = ak->private_data[0];
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
294*4882a593Smuzhiyun 	priv->cs_mask =
295*4882a593Smuzhiyun 	priv->cs_addr = chip == 0 ? ICE1712_VX442_CODEC_CHIP_A :
296*4882a593Smuzhiyun 				    ICE1712_VX442_CODEC_CHIP_B;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun /*
300*4882a593Smuzhiyun  * change the DFS bit according rate for Delta1010
301*4882a593Smuzhiyun  */
delta_1010_set_rate_val(struct snd_ice1712 * ice,unsigned int rate)302*4882a593Smuzhiyun static void delta_1010_set_rate_val(struct snd_ice1712 *ice, unsigned int rate)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun 	unsigned char tmp, tmp2;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	if (rate == 0)	/* no hint - S/PDIF input is master, simply return */
307*4882a593Smuzhiyun 		return;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
310*4882a593Smuzhiyun 	tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
311*4882a593Smuzhiyun 	tmp2 = tmp & ~ICE1712_DELTA_DFS;
312*4882a593Smuzhiyun 	if (rate > 48000)
313*4882a593Smuzhiyun 		tmp2 |= ICE1712_DELTA_DFS;
314*4882a593Smuzhiyun 	if (tmp != tmp2)
315*4882a593Smuzhiyun 		snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp2);
316*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun /*
320*4882a593Smuzhiyun  * change the rate of AK4524 on Delta 44/66, AP, 1010LT
321*4882a593Smuzhiyun  */
delta_ak4524_set_rate_val(struct snd_akm4xxx * ak,unsigned int rate)322*4882a593Smuzhiyun static void delta_ak4524_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun 	unsigned char tmp, tmp2;
325*4882a593Smuzhiyun 	struct snd_ice1712 *ice = ak->private_data[0];
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	if (rate == 0)	/* no hint - S/PDIF input is master, simply return */
328*4882a593Smuzhiyun 		return;
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	/* check before reset ak4524 to avoid unnecessary clicks */
331*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
332*4882a593Smuzhiyun 	tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
333*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
334*4882a593Smuzhiyun 	tmp2 = tmp & ~ICE1712_DELTA_DFS;
335*4882a593Smuzhiyun 	if (rate > 48000)
336*4882a593Smuzhiyun 		tmp2 |= ICE1712_DELTA_DFS;
337*4882a593Smuzhiyun 	if (tmp == tmp2)
338*4882a593Smuzhiyun 		return;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	/* do it again */
341*4882a593Smuzhiyun 	snd_akm4xxx_reset(ak, 1);
342*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
343*4882a593Smuzhiyun 	tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & ~ICE1712_DELTA_DFS;
344*4882a593Smuzhiyun 	if (rate > 48000)
345*4882a593Smuzhiyun 		tmp |= ICE1712_DELTA_DFS;
346*4882a593Smuzhiyun 	snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
347*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
348*4882a593Smuzhiyun 	snd_akm4xxx_reset(ak, 0);
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun /*
352*4882a593Smuzhiyun  * change the rate of AK4524 on VX442
353*4882a593Smuzhiyun  */
vx442_ak4524_set_rate_val(struct snd_akm4xxx * ak,unsigned int rate)354*4882a593Smuzhiyun static void vx442_ak4524_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun 	unsigned char val;
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	val = (rate > 48000) ? 0x65 : 0x60;
359*4882a593Smuzhiyun 	if (snd_akm4xxx_get(ak, 0, 0x02) != val ||
360*4882a593Smuzhiyun 	    snd_akm4xxx_get(ak, 1, 0x02) != val) {
361*4882a593Smuzhiyun 		snd_akm4xxx_reset(ak, 1);
362*4882a593Smuzhiyun 		snd_akm4xxx_write(ak, 0, 0x02, val);
363*4882a593Smuzhiyun 		snd_akm4xxx_write(ak, 1, 0x02, val);
364*4882a593Smuzhiyun 		snd_akm4xxx_reset(ak, 0);
365*4882a593Smuzhiyun 	}
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun /*
370*4882a593Smuzhiyun  * SPDIF ops for Delta 1010, Dio, 66
371*4882a593Smuzhiyun  */
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun /* open callback */
delta_open_spdif(struct snd_ice1712 * ice,struct snd_pcm_substream * substream)374*4882a593Smuzhiyun static void delta_open_spdif(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun 	ice->spdif.cs8403_stream_bits = ice->spdif.cs8403_bits;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun /* set up */
delta_setup_spdif(struct snd_ice1712 * ice,int rate)380*4882a593Smuzhiyun static void delta_setup_spdif(struct snd_ice1712 *ice, int rate)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	unsigned long flags;
383*4882a593Smuzhiyun 	unsigned int tmp;
384*4882a593Smuzhiyun 	int change;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	spin_lock_irqsave(&ice->reg_lock, flags);
387*4882a593Smuzhiyun 	tmp = ice->spdif.cs8403_stream_bits;
388*4882a593Smuzhiyun 	if (tmp & 0x01)		/* consumer */
389*4882a593Smuzhiyun 		tmp &= (tmp & 0x01) ? ~0x06 : ~0x18;
390*4882a593Smuzhiyun 	switch (rate) {
391*4882a593Smuzhiyun 	case 32000: tmp |= (tmp & 0x01) ? 0x04 : 0x00; break;
392*4882a593Smuzhiyun 	case 44100: tmp |= (tmp & 0x01) ? 0x00 : 0x10; break;
393*4882a593Smuzhiyun 	case 48000: tmp |= (tmp & 0x01) ? 0x02 : 0x08; break;
394*4882a593Smuzhiyun 	default: tmp |= (tmp & 0x01) ? 0x00 : 0x18; break;
395*4882a593Smuzhiyun 	}
396*4882a593Smuzhiyun 	change = ice->spdif.cs8403_stream_bits != tmp;
397*4882a593Smuzhiyun 	ice->spdif.cs8403_stream_bits = tmp;
398*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ice->reg_lock, flags);
399*4882a593Smuzhiyun 	if (change)
400*4882a593Smuzhiyun 		snd_ctl_notify(ice->card, SNDRV_CTL_EVENT_MASK_VALUE, &ice->spdif.stream_ctl->id);
401*4882a593Smuzhiyun 	snd_ice1712_delta_cs8403_spdif_write(ice, tmp);
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun #define snd_ice1712_delta1010lt_wordclock_status_info \
405*4882a593Smuzhiyun 	snd_ctl_boolean_mono_info
406*4882a593Smuzhiyun 
snd_ice1712_delta1010lt_wordclock_status_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)407*4882a593Smuzhiyun static int snd_ice1712_delta1010lt_wordclock_status_get(struct snd_kcontrol *kcontrol,
408*4882a593Smuzhiyun 			 struct snd_ctl_elem_value *ucontrol)
409*4882a593Smuzhiyun {
410*4882a593Smuzhiyun 	char reg = 0x10; /* CS8427 receiver error register */
411*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	if (snd_i2c_sendbytes(ice->cs8427, &reg, 1) != 1)
414*4882a593Smuzhiyun 		dev_err(ice->card->dev,
415*4882a593Smuzhiyun 			"unable to send register 0x%x byte to CS8427\n", reg);
416*4882a593Smuzhiyun 	snd_i2c_readbytes(ice->cs8427, &reg, 1);
417*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (reg & CS8427_UNLOCK) ? 1 : 0;
418*4882a593Smuzhiyun 	return 0;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_delta1010lt_wordclock_status =
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun 	.access =	(SNDRV_CTL_ELEM_ACCESS_READ),
424*4882a593Smuzhiyun 	.iface =	SNDRV_CTL_ELEM_IFACE_MIXER,
425*4882a593Smuzhiyun 	.name =         "Word Clock Status",
426*4882a593Smuzhiyun 	.info =		snd_ice1712_delta1010lt_wordclock_status_info,
427*4882a593Smuzhiyun 	.get =		snd_ice1712_delta1010lt_wordclock_status_get,
428*4882a593Smuzhiyun };
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun /*
431*4882a593Smuzhiyun  * initialize the chips on M-Audio cards
432*4882a593Smuzhiyun  */
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun static const struct snd_akm4xxx akm_audiophile = {
435*4882a593Smuzhiyun 	.type = SND_AK4528,
436*4882a593Smuzhiyun 	.num_adcs = 2,
437*4882a593Smuzhiyun 	.num_dacs = 2,
438*4882a593Smuzhiyun 	.ops = {
439*4882a593Smuzhiyun 		.set_rate_val = delta_ak4524_set_rate_val
440*4882a593Smuzhiyun 	}
441*4882a593Smuzhiyun };
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun static const struct snd_ak4xxx_private akm_audiophile_priv = {
444*4882a593Smuzhiyun 	.caddr = 2,
445*4882a593Smuzhiyun 	.cif = 0,
446*4882a593Smuzhiyun 	.data_mask = ICE1712_DELTA_AP_DOUT,
447*4882a593Smuzhiyun 	.clk_mask = ICE1712_DELTA_AP_CCLK,
448*4882a593Smuzhiyun 	.cs_mask = ICE1712_DELTA_AP_CS_CODEC,
449*4882a593Smuzhiyun 	.cs_addr = ICE1712_DELTA_AP_CS_CODEC,
450*4882a593Smuzhiyun 	.cs_none = 0,
451*4882a593Smuzhiyun 	.add_flags = ICE1712_DELTA_AP_CS_DIGITAL,
452*4882a593Smuzhiyun 	.mask_flags = 0,
453*4882a593Smuzhiyun };
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun static const struct snd_akm4xxx akm_delta410 = {
456*4882a593Smuzhiyun 	.type = SND_AK4529,
457*4882a593Smuzhiyun 	.num_adcs = 2,
458*4882a593Smuzhiyun 	.num_dacs = 8,
459*4882a593Smuzhiyun 	.ops = {
460*4882a593Smuzhiyun 		.set_rate_val = delta_ak4524_set_rate_val
461*4882a593Smuzhiyun 	}
462*4882a593Smuzhiyun };
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun static const struct snd_ak4xxx_private akm_delta410_priv = {
465*4882a593Smuzhiyun 	.caddr = 0,
466*4882a593Smuzhiyun 	.cif = 0,
467*4882a593Smuzhiyun 	.data_mask = ICE1712_DELTA_AP_DOUT,
468*4882a593Smuzhiyun 	.clk_mask = ICE1712_DELTA_AP_CCLK,
469*4882a593Smuzhiyun 	.cs_mask = ICE1712_DELTA_AP_CS_CODEC,
470*4882a593Smuzhiyun 	.cs_addr = ICE1712_DELTA_AP_CS_CODEC,
471*4882a593Smuzhiyun 	.cs_none = 0,
472*4882a593Smuzhiyun 	.add_flags = ICE1712_DELTA_AP_CS_DIGITAL,
473*4882a593Smuzhiyun 	.mask_flags = 0,
474*4882a593Smuzhiyun };
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun static const struct snd_akm4xxx akm_delta1010lt = {
477*4882a593Smuzhiyun 	.type = SND_AK4524,
478*4882a593Smuzhiyun 	.num_adcs = 8,
479*4882a593Smuzhiyun 	.num_dacs = 8,
480*4882a593Smuzhiyun 	.ops = {
481*4882a593Smuzhiyun 		.lock = delta1010lt_ak4524_lock,
482*4882a593Smuzhiyun 		.set_rate_val = delta_ak4524_set_rate_val
483*4882a593Smuzhiyun 	}
484*4882a593Smuzhiyun };
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun static const struct snd_ak4xxx_private akm_delta1010lt_priv = {
487*4882a593Smuzhiyun 	.caddr = 2,
488*4882a593Smuzhiyun 	.cif = 0, /* the default level of the CIF pin from AK4524 */
489*4882a593Smuzhiyun 	.data_mask = ICE1712_DELTA_1010LT_DOUT,
490*4882a593Smuzhiyun 	.clk_mask = ICE1712_DELTA_1010LT_CCLK,
491*4882a593Smuzhiyun 	.cs_mask = 0,
492*4882a593Smuzhiyun 	.cs_addr = 0, /* set later */
493*4882a593Smuzhiyun 	.cs_none = ICE1712_DELTA_1010LT_CS_NONE,
494*4882a593Smuzhiyun 	.add_flags = 0,
495*4882a593Smuzhiyun 	.mask_flags = 0,
496*4882a593Smuzhiyun };
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun static const struct snd_akm4xxx akm_delta66e = {
499*4882a593Smuzhiyun 	.type = SND_AK4524,
500*4882a593Smuzhiyun 	.num_adcs = 4,
501*4882a593Smuzhiyun 	.num_dacs = 4,
502*4882a593Smuzhiyun 	.ops = {
503*4882a593Smuzhiyun 		.lock = delta66e_ak4524_lock,
504*4882a593Smuzhiyun 		.set_rate_val = delta_ak4524_set_rate_val
505*4882a593Smuzhiyun 	}
506*4882a593Smuzhiyun };
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun static const struct snd_ak4xxx_private akm_delta66e_priv = {
509*4882a593Smuzhiyun 	.caddr = 2,
510*4882a593Smuzhiyun 	.cif = 0, /* the default level of the CIF pin from AK4524 */
511*4882a593Smuzhiyun 	.data_mask = ICE1712_DELTA_66E_DOUT,
512*4882a593Smuzhiyun 	.clk_mask = ICE1712_DELTA_66E_CCLK,
513*4882a593Smuzhiyun 	.cs_mask = 0,
514*4882a593Smuzhiyun 	.cs_addr = 0, /* set later */
515*4882a593Smuzhiyun 	.cs_none = 0,
516*4882a593Smuzhiyun 	.add_flags = 0,
517*4882a593Smuzhiyun 	.mask_flags = 0,
518*4882a593Smuzhiyun };
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun static const struct snd_akm4xxx akm_delta44 = {
522*4882a593Smuzhiyun 	.type = SND_AK4524,
523*4882a593Smuzhiyun 	.num_adcs = 4,
524*4882a593Smuzhiyun 	.num_dacs = 4,
525*4882a593Smuzhiyun 	.ops = {
526*4882a593Smuzhiyun 		.lock = delta_ak4524_lock,
527*4882a593Smuzhiyun 		.set_rate_val = delta_ak4524_set_rate_val
528*4882a593Smuzhiyun 	}
529*4882a593Smuzhiyun };
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun static const struct snd_ak4xxx_private akm_delta44_priv = {
532*4882a593Smuzhiyun 	.caddr = 2,
533*4882a593Smuzhiyun 	.cif = 0, /* the default level of the CIF pin from AK4524 */
534*4882a593Smuzhiyun 	.data_mask = ICE1712_DELTA_CODEC_SERIAL_DATA,
535*4882a593Smuzhiyun 	.clk_mask = ICE1712_DELTA_CODEC_SERIAL_CLOCK,
536*4882a593Smuzhiyun 	.cs_mask = 0,
537*4882a593Smuzhiyun 	.cs_addr = 0, /* set later */
538*4882a593Smuzhiyun 	.cs_none = 0,
539*4882a593Smuzhiyun 	.add_flags = 0,
540*4882a593Smuzhiyun 	.mask_flags = 0,
541*4882a593Smuzhiyun };
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun static const struct snd_akm4xxx akm_vx442 = {
544*4882a593Smuzhiyun 	.type = SND_AK4524,
545*4882a593Smuzhiyun 	.num_adcs = 4,
546*4882a593Smuzhiyun 	.num_dacs = 4,
547*4882a593Smuzhiyun 	.ops = {
548*4882a593Smuzhiyun 		.lock = vx442_ak4524_lock,
549*4882a593Smuzhiyun 		.set_rate_val = vx442_ak4524_set_rate_val
550*4882a593Smuzhiyun 	}
551*4882a593Smuzhiyun };
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun static const struct snd_ak4xxx_private akm_vx442_priv = {
554*4882a593Smuzhiyun 	.caddr = 2,
555*4882a593Smuzhiyun 	.cif = 0,
556*4882a593Smuzhiyun 	.data_mask = ICE1712_VX442_DOUT,
557*4882a593Smuzhiyun 	.clk_mask = ICE1712_VX442_CCLK,
558*4882a593Smuzhiyun 	.cs_mask = 0,
559*4882a593Smuzhiyun 	.cs_addr = 0, /* set later */
560*4882a593Smuzhiyun 	.cs_none = 0,
561*4882a593Smuzhiyun 	.add_flags = 0,
562*4882a593Smuzhiyun 	.mask_flags = 0,
563*4882a593Smuzhiyun };
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
snd_ice1712_delta_resume(struct snd_ice1712 * ice)566*4882a593Smuzhiyun static int snd_ice1712_delta_resume(struct snd_ice1712 *ice)
567*4882a593Smuzhiyun {
568*4882a593Smuzhiyun 	unsigned char akm_img_bak[AK4XXX_IMAGE_SIZE];
569*4882a593Smuzhiyun 	unsigned char akm_vol_bak[AK4XXX_IMAGE_SIZE];
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	/* init spdif */
572*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
573*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_AUDIOPHILE:
574*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA410:
575*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010E:
576*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010LT:
577*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_VX442:
578*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66E:
579*4882a593Smuzhiyun 		snd_cs8427_init(ice->i2c, ice->cs8427);
580*4882a593Smuzhiyun 		break;
581*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010:
582*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_MEDIASTATION:
583*4882a593Smuzhiyun 		/* nothing */
584*4882a593Smuzhiyun 		break;
585*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTADIO2496:
586*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66:
587*4882a593Smuzhiyun 		/* Set spdif defaults */
588*4882a593Smuzhiyun 		snd_ice1712_delta_cs8403_spdif_write(ice, ice->spdif.cs8403_bits);
589*4882a593Smuzhiyun 		break;
590*4882a593Smuzhiyun 	}
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	/* init codec and restore registers */
593*4882a593Smuzhiyun 	if (ice->akm_codecs) {
594*4882a593Smuzhiyun 		memcpy(akm_img_bak, ice->akm->images, sizeof(akm_img_bak));
595*4882a593Smuzhiyun 		memcpy(akm_vol_bak, ice->akm->volumes, sizeof(akm_vol_bak));
596*4882a593Smuzhiyun 		snd_akm4xxx_init(ice->akm);
597*4882a593Smuzhiyun 		memcpy(ice->akm->images, akm_img_bak, sizeof(akm_img_bak));
598*4882a593Smuzhiyun 		memcpy(ice->akm->volumes, akm_vol_bak, sizeof(akm_vol_bak));
599*4882a593Smuzhiyun 		snd_akm4xxx_reset(ice->akm, 0);
600*4882a593Smuzhiyun 	}
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	return 0;
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun 
snd_ice1712_delta_suspend(struct snd_ice1712 * ice)605*4882a593Smuzhiyun static int snd_ice1712_delta_suspend(struct snd_ice1712 *ice)
606*4882a593Smuzhiyun {
607*4882a593Smuzhiyun 	if (ice->akm_codecs) /* reset & mute codec */
608*4882a593Smuzhiyun 		snd_akm4xxx_reset(ice->akm, 1);
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	return 0;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun #endif
613*4882a593Smuzhiyun 
snd_ice1712_delta_init(struct snd_ice1712 * ice)614*4882a593Smuzhiyun static int snd_ice1712_delta_init(struct snd_ice1712 *ice)
615*4882a593Smuzhiyun {
616*4882a593Smuzhiyun 	int err;
617*4882a593Smuzhiyun 	struct snd_akm4xxx *ak;
618*4882a593Smuzhiyun 	unsigned char tmp;
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun 	if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DELTA1010 &&
621*4882a593Smuzhiyun 	    ice->eeprom.gpiodir == 0x7b)
622*4882a593Smuzhiyun 		ice->eeprom.subvendor = ICE1712_SUBDEVICE_DELTA1010E;
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DELTA66 &&
625*4882a593Smuzhiyun 	    ice->eeprom.gpiodir == 0xfb)
626*4882a593Smuzhiyun 	    	ice->eeprom.subvendor = ICE1712_SUBDEVICE_DELTA66E;
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 	/* determine I2C, DACs and ADCs */
629*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
630*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_AUDIOPHILE:
631*4882a593Smuzhiyun 		ice->num_total_dacs = 2;
632*4882a593Smuzhiyun 		ice->num_total_adcs = 2;
633*4882a593Smuzhiyun 		break;
634*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA410:
635*4882a593Smuzhiyun 		ice->num_total_dacs = 8;
636*4882a593Smuzhiyun 		ice->num_total_adcs = 2;
637*4882a593Smuzhiyun 		break;
638*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA44:
639*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66:
640*4882a593Smuzhiyun 		ice->num_total_dacs = ice->omni ? 8 : 4;
641*4882a593Smuzhiyun 		ice->num_total_adcs = ice->omni ? 8 : 4;
642*4882a593Smuzhiyun 		break;
643*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010:
644*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010E:
645*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010LT:
646*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_MEDIASTATION:
647*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_EDIROLDA2496:
648*4882a593Smuzhiyun 		ice->num_total_dacs = 8;
649*4882a593Smuzhiyun 		ice->num_total_adcs = 8;
650*4882a593Smuzhiyun 		break;
651*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTADIO2496:
652*4882a593Smuzhiyun 		ice->num_total_dacs = 4;	/* two AK4324 codecs */
653*4882a593Smuzhiyun 		break;
654*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_VX442:
655*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66E:	/* omni not supported yet */
656*4882a593Smuzhiyun 		ice->num_total_dacs = 4;
657*4882a593Smuzhiyun 		ice->num_total_adcs = 4;
658*4882a593Smuzhiyun 		break;
659*4882a593Smuzhiyun 	}
660*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
661*4882a593Smuzhiyun 	ice->pm_resume = snd_ice1712_delta_resume;
662*4882a593Smuzhiyun 	ice->pm_suspend = snd_ice1712_delta_suspend;
663*4882a593Smuzhiyun 	ice->pm_suspend_enabled = 1;
664*4882a593Smuzhiyun #endif
665*4882a593Smuzhiyun 	/* initialize the SPI clock to high */
666*4882a593Smuzhiyun 	tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
667*4882a593Smuzhiyun 	tmp |= ICE1712_DELTA_AP_CCLK;
668*4882a593Smuzhiyun 	snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
669*4882a593Smuzhiyun 	udelay(5);
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	/* initialize spdif */
672*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
673*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_AUDIOPHILE:
674*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA410:
675*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010E:
676*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010LT:
677*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_VX442:
678*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66E:
679*4882a593Smuzhiyun 		if ((err = snd_i2c_bus_create(ice->card, "ICE1712 GPIO 1", NULL, &ice->i2c)) < 0) {
680*4882a593Smuzhiyun 			dev_err(ice->card->dev, "unable to create I2C bus\n");
681*4882a593Smuzhiyun 			return err;
682*4882a593Smuzhiyun 		}
683*4882a593Smuzhiyun 		ice->i2c->private_data = ice;
684*4882a593Smuzhiyun 		ice->i2c->ops = &ap_cs8427_i2c_ops;
685*4882a593Smuzhiyun 		if ((err = snd_ice1712_init_cs8427(ice, CS8427_BASE_ADDR)) < 0)
686*4882a593Smuzhiyun 			return err;
687*4882a593Smuzhiyun 		break;
688*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010:
689*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_MEDIASTATION:
690*4882a593Smuzhiyun 		ice->gpio.set_pro_rate = delta_1010_set_rate_val;
691*4882a593Smuzhiyun 		break;
692*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTADIO2496:
693*4882a593Smuzhiyun 		ice->gpio.set_pro_rate = delta_1010_set_rate_val;
694*4882a593Smuzhiyun 		fallthrough;
695*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66:
696*4882a593Smuzhiyun 		ice->spdif.ops.open = delta_open_spdif;
697*4882a593Smuzhiyun 		ice->spdif.ops.setup_rate = delta_setup_spdif;
698*4882a593Smuzhiyun 		ice->spdif.ops.default_get = delta_spdif_default_get;
699*4882a593Smuzhiyun 		ice->spdif.ops.default_put = delta_spdif_default_put;
700*4882a593Smuzhiyun 		ice->spdif.ops.stream_get = delta_spdif_stream_get;
701*4882a593Smuzhiyun 		ice->spdif.ops.stream_put = delta_spdif_stream_put;
702*4882a593Smuzhiyun 		/* Set spdif defaults */
703*4882a593Smuzhiyun 		snd_ice1712_delta_cs8403_spdif_write(ice, ice->spdif.cs8403_bits);
704*4882a593Smuzhiyun 		break;
705*4882a593Smuzhiyun 	}
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 	/* no analog? */
708*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
709*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010:
710*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010E:
711*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTADIO2496:
712*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_MEDIASTATION:
713*4882a593Smuzhiyun 		return 0;
714*4882a593Smuzhiyun 	}
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun 	/* second stage of initialization, analog parts and others */
717*4882a593Smuzhiyun 	ak = ice->akm = kmalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
718*4882a593Smuzhiyun 	if (! ak)
719*4882a593Smuzhiyun 		return -ENOMEM;
720*4882a593Smuzhiyun 	ice->akm_codecs = 1;
721*4882a593Smuzhiyun 
722*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
723*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_AUDIOPHILE:
724*4882a593Smuzhiyun 		err = snd_ice1712_akm4xxx_init(ak, &akm_audiophile, &akm_audiophile_priv, ice);
725*4882a593Smuzhiyun 		break;
726*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA410:
727*4882a593Smuzhiyun 		err = snd_ice1712_akm4xxx_init(ak, &akm_delta410, &akm_delta410_priv, ice);
728*4882a593Smuzhiyun 		break;
729*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010LT:
730*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_EDIROLDA2496:
731*4882a593Smuzhiyun 		err = snd_ice1712_akm4xxx_init(ak, &akm_delta1010lt, &akm_delta1010lt_priv, ice);
732*4882a593Smuzhiyun 		break;
733*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66:
734*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA44:
735*4882a593Smuzhiyun 		err = snd_ice1712_akm4xxx_init(ak, &akm_delta44, &akm_delta44_priv, ice);
736*4882a593Smuzhiyun 		break;
737*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_VX442:
738*4882a593Smuzhiyun 		err = snd_ice1712_akm4xxx_init(ak, &akm_vx442, &akm_vx442_priv, ice);
739*4882a593Smuzhiyun 		break;
740*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66E:
741*4882a593Smuzhiyun 		err = snd_ice1712_akm4xxx_init(ak, &akm_delta66e, &akm_delta66e_priv, ice);
742*4882a593Smuzhiyun 		break;
743*4882a593Smuzhiyun 	default:
744*4882a593Smuzhiyun 		snd_BUG();
745*4882a593Smuzhiyun 		return -EINVAL;
746*4882a593Smuzhiyun 	}
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 	return err;
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 
752*4882a593Smuzhiyun /*
753*4882a593Smuzhiyun  * additional controls for M-Audio cards
754*4882a593Smuzhiyun  */
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_delta1010_wordclock_select =
757*4882a593Smuzhiyun ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_MIXER, "Word Clock Sync", 0, ICE1712_DELTA_WORD_CLOCK_SELECT, 1, 0);
758*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_delta1010lt_wordclock_select =
759*4882a593Smuzhiyun ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_MIXER, "Word Clock Sync", 0, ICE1712_DELTA_1010LT_WORDCLOCK, 0, 0);
760*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_delta1010_wordclock_status =
761*4882a593Smuzhiyun ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_MIXER, "Word Clock Status", 0, ICE1712_DELTA_WORD_CLOCK_STATUS, 1, SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE);
762*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_deltadio2496_spdif_in_select =
763*4882a593Smuzhiyun ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_MIXER, "IEC958 Input Optical", 0, ICE1712_DELTA_SPDIF_INPUT_SELECT, 0, 0);
764*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ice1712_delta_spdif_in_status =
765*4882a593Smuzhiyun ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_MIXER, "Delta IEC958 Input Status", 0, ICE1712_DELTA_SPDIF_IN_STAT, 1, SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE);
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun 
snd_ice1712_delta_add_controls(struct snd_ice1712 * ice)768*4882a593Smuzhiyun static int snd_ice1712_delta_add_controls(struct snd_ice1712 *ice)
769*4882a593Smuzhiyun {
770*4882a593Smuzhiyun 	int err;
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun 	/* 1010 and dio specific controls */
773*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
774*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010:
775*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_MEDIASTATION:
776*4882a593Smuzhiyun 		err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta1010_wordclock_select, ice));
777*4882a593Smuzhiyun 		if (err < 0)
778*4882a593Smuzhiyun 			return err;
779*4882a593Smuzhiyun 		err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta1010_wordclock_status, ice));
780*4882a593Smuzhiyun 		if (err < 0)
781*4882a593Smuzhiyun 			return err;
782*4882a593Smuzhiyun 		break;
783*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTADIO2496:
784*4882a593Smuzhiyun 		err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_deltadio2496_spdif_in_select, ice));
785*4882a593Smuzhiyun 		if (err < 0)
786*4882a593Smuzhiyun 			return err;
787*4882a593Smuzhiyun 		break;
788*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010E:
789*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010LT:
790*4882a593Smuzhiyun 		err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta1010lt_wordclock_select, ice));
791*4882a593Smuzhiyun 		if (err < 0)
792*4882a593Smuzhiyun 			return err;
793*4882a593Smuzhiyun 		err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta1010lt_wordclock_status, ice));
794*4882a593Smuzhiyun 		if (err < 0)
795*4882a593Smuzhiyun 			return err;
796*4882a593Smuzhiyun 		break;
797*4882a593Smuzhiyun 	}
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 	/* normal spdif controls */
800*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
801*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010:
802*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTADIO2496:
803*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66:
804*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_MEDIASTATION:
805*4882a593Smuzhiyun 		err = snd_ice1712_spdif_build_controls(ice);
806*4882a593Smuzhiyun 		if (err < 0)
807*4882a593Smuzhiyun 			return err;
808*4882a593Smuzhiyun 		break;
809*4882a593Smuzhiyun 	}
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun 	/* spdif status in */
812*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
813*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010:
814*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTADIO2496:
815*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66:
816*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_MEDIASTATION:
817*4882a593Smuzhiyun 		err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta_spdif_in_status, ice));
818*4882a593Smuzhiyun 		if (err < 0)
819*4882a593Smuzhiyun 			return err;
820*4882a593Smuzhiyun 		break;
821*4882a593Smuzhiyun 	}
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun 	/* ak4524 controls */
824*4882a593Smuzhiyun 	switch (ice->eeprom.subvendor) {
825*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA1010LT:
826*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_AUDIOPHILE:
827*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA410:
828*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA44:
829*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66:
830*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_VX442:
831*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_DELTA66E:
832*4882a593Smuzhiyun 	case ICE1712_SUBDEVICE_EDIROLDA2496:
833*4882a593Smuzhiyun 		err = snd_ice1712_akm4xxx_build_controls(ice);
834*4882a593Smuzhiyun 		if (err < 0)
835*4882a593Smuzhiyun 			return err;
836*4882a593Smuzhiyun 		break;
837*4882a593Smuzhiyun 	}
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun 	return 0;
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun /* entry point */
844*4882a593Smuzhiyun struct snd_ice1712_card_info snd_ice1712_delta_cards[] = {
845*4882a593Smuzhiyun 	{
846*4882a593Smuzhiyun 		.subvendor = ICE1712_SUBDEVICE_DELTA1010,
847*4882a593Smuzhiyun 		.name = "M Audio Delta 1010",
848*4882a593Smuzhiyun 		.model = "delta1010",
849*4882a593Smuzhiyun 		.chip_init = snd_ice1712_delta_init,
850*4882a593Smuzhiyun 		.build_controls = snd_ice1712_delta_add_controls,
851*4882a593Smuzhiyun 	},
852*4882a593Smuzhiyun 	{
853*4882a593Smuzhiyun 		.subvendor = ICE1712_SUBDEVICE_DELTADIO2496,
854*4882a593Smuzhiyun 		.name = "M Audio Delta DiO 2496",
855*4882a593Smuzhiyun 		.model = "dio2496",
856*4882a593Smuzhiyun 		.chip_init = snd_ice1712_delta_init,
857*4882a593Smuzhiyun 		.build_controls = snd_ice1712_delta_add_controls,
858*4882a593Smuzhiyun 		.no_mpu401 = 1,
859*4882a593Smuzhiyun 	},
860*4882a593Smuzhiyun 	{
861*4882a593Smuzhiyun 		.subvendor = ICE1712_SUBDEVICE_DELTA66,
862*4882a593Smuzhiyun 		.name = "M Audio Delta 66",
863*4882a593Smuzhiyun 		.model = "delta66",
864*4882a593Smuzhiyun 		.chip_init = snd_ice1712_delta_init,
865*4882a593Smuzhiyun 		.build_controls = snd_ice1712_delta_add_controls,
866*4882a593Smuzhiyun 		.no_mpu401 = 1,
867*4882a593Smuzhiyun 	},
868*4882a593Smuzhiyun 	{
869*4882a593Smuzhiyun 		.subvendor = ICE1712_SUBDEVICE_DELTA44,
870*4882a593Smuzhiyun 		.name = "M Audio Delta 44",
871*4882a593Smuzhiyun 		.model = "delta44",
872*4882a593Smuzhiyun 		.chip_init = snd_ice1712_delta_init,
873*4882a593Smuzhiyun 		.build_controls = snd_ice1712_delta_add_controls,
874*4882a593Smuzhiyun 		.no_mpu401 = 1,
875*4882a593Smuzhiyun 	},
876*4882a593Smuzhiyun 	{
877*4882a593Smuzhiyun 		.subvendor = ICE1712_SUBDEVICE_AUDIOPHILE,
878*4882a593Smuzhiyun 		.name = "M Audio Audiophile 24/96",
879*4882a593Smuzhiyun 		.model = "audiophile",
880*4882a593Smuzhiyun 		.chip_init = snd_ice1712_delta_init,
881*4882a593Smuzhiyun 		.build_controls = snd_ice1712_delta_add_controls,
882*4882a593Smuzhiyun 	},
883*4882a593Smuzhiyun 	{
884*4882a593Smuzhiyun 		.subvendor = ICE1712_SUBDEVICE_DELTA410,
885*4882a593Smuzhiyun 		.name = "M Audio Delta 410",
886*4882a593Smuzhiyun 		.model = "delta410",
887*4882a593Smuzhiyun 		.chip_init = snd_ice1712_delta_init,
888*4882a593Smuzhiyun 		.build_controls = snd_ice1712_delta_add_controls,
889*4882a593Smuzhiyun 	},
890*4882a593Smuzhiyun 	{
891*4882a593Smuzhiyun 		.subvendor = ICE1712_SUBDEVICE_DELTA1010LT,
892*4882a593Smuzhiyun 		.name = "M Audio Delta 1010LT",
893*4882a593Smuzhiyun 		.model = "delta1010lt",
894*4882a593Smuzhiyun 		.chip_init = snd_ice1712_delta_init,
895*4882a593Smuzhiyun 		.build_controls = snd_ice1712_delta_add_controls,
896*4882a593Smuzhiyun 	},
897*4882a593Smuzhiyun 	{
898*4882a593Smuzhiyun 		.subvendor = ICE1712_SUBDEVICE_VX442,
899*4882a593Smuzhiyun 		.name = "Digigram VX442",
900*4882a593Smuzhiyun 		.model = "vx442",
901*4882a593Smuzhiyun 		.chip_init = snd_ice1712_delta_init,
902*4882a593Smuzhiyun 		.build_controls = snd_ice1712_delta_add_controls,
903*4882a593Smuzhiyun 		.no_mpu401 = 1,
904*4882a593Smuzhiyun 	},
905*4882a593Smuzhiyun 	{
906*4882a593Smuzhiyun 		.subvendor = ICE1712_SUBDEVICE_MEDIASTATION,
907*4882a593Smuzhiyun 		.name = "Lionstracs Mediastation",
908*4882a593Smuzhiyun 		.model = "mediastation",
909*4882a593Smuzhiyun 		.chip_init = snd_ice1712_delta_init,
910*4882a593Smuzhiyun 		.build_controls = snd_ice1712_delta_add_controls,
911*4882a593Smuzhiyun 	},
912*4882a593Smuzhiyun 	{
913*4882a593Smuzhiyun 		.subvendor = ICE1712_SUBDEVICE_EDIROLDA2496,
914*4882a593Smuzhiyun 		.name = "Edirol DA2496",
915*4882a593Smuzhiyun 		.model = "da2496",
916*4882a593Smuzhiyun 		.chip_init = snd_ice1712_delta_init,
917*4882a593Smuzhiyun 		.build_controls = snd_ice1712_delta_add_controls,
918*4882a593Smuzhiyun 	},
919*4882a593Smuzhiyun 	{ } /* terminator */
920*4882a593Smuzhiyun };
921