xref: /OK3568_Linux_fs/kernel/sound/pci/ice1712/aureon.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *   ALSA driver for ICEnsemble VT1724 (Envy24HT)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *   Lowlevel functions for Terratec Aureon cards
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *	Copyright (c) 2003 Takashi Iwai <tiwai@suse.de>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * NOTES:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * - we reuse the struct snd_akm4xxx record for storing the wm8770 codec data.
12*4882a593Smuzhiyun  *   both wm and akm codecs are pretty similar, so we can integrate
13*4882a593Smuzhiyun  *   both controls in the future, once if wm codecs are reused in
14*4882a593Smuzhiyun  *   many boards.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * - DAC digital volumes are not implemented in the mixer.
17*4882a593Smuzhiyun  *   if they show better response than DAC analog volumes, we can use them
18*4882a593Smuzhiyun  *   instead.
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  *   Lowlevel functions for AudioTrak Prodigy 7.1 (and possibly 192) cards
21*4882a593Smuzhiyun  *      Copyright (c) 2003 Dimitromanolakis Apostolos <apostol@cs.utoronto.ca>
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  *   version 0.82: Stable / not all features work yet (no communication with AC97 secondary)
24*4882a593Smuzhiyun  *       added 64x/128x oversampling switch (should be 64x only for 96khz)
25*4882a593Smuzhiyun  *       fixed some recording labels (still need to check the rest)
26*4882a593Smuzhiyun  *       recording is working probably thanks to correct wm8770 initialization
27*4882a593Smuzhiyun  *
28*4882a593Smuzhiyun  *   version 0.5: Initial release:
29*4882a593Smuzhiyun  *           working: analog output, mixer, headphone amplifier switch
30*4882a593Smuzhiyun  *       not working: prety much everything else, at least i could verify that
31*4882a593Smuzhiyun  *                    we have no digital output, no capture, pretty bad clicks and poops
32*4882a593Smuzhiyun  *                    on mixer switch and other coll stuff.
33*4882a593Smuzhiyun  */
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #include <linux/delay.h>
36*4882a593Smuzhiyun #include <linux/interrupt.h>
37*4882a593Smuzhiyun #include <linux/init.h>
38*4882a593Smuzhiyun #include <linux/slab.h>
39*4882a593Smuzhiyun #include <linux/mutex.h>
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #include <sound/core.h>
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #include "ice1712.h"
44*4882a593Smuzhiyun #include "envy24ht.h"
45*4882a593Smuzhiyun #include "aureon.h"
46*4882a593Smuzhiyun #include <sound/tlv.h>
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* AC97 register cache for Aureon */
49*4882a593Smuzhiyun struct aureon_spec {
50*4882a593Smuzhiyun 	unsigned short stac9744[64];
51*4882a593Smuzhiyun 	unsigned int cs8415_mux;
52*4882a593Smuzhiyun 	unsigned short master[2];
53*4882a593Smuzhiyun 	unsigned short vol[8];
54*4882a593Smuzhiyun 	unsigned char pca9554_out;
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun /* WM8770 registers */
58*4882a593Smuzhiyun #define WM_DAC_ATTEN		0x00	/* DAC1-8 analog attenuation */
59*4882a593Smuzhiyun #define WM_DAC_MASTER_ATTEN	0x08	/* DAC master analog attenuation */
60*4882a593Smuzhiyun #define WM_DAC_DIG_ATTEN	0x09	/* DAC1-8 digital attenuation */
61*4882a593Smuzhiyun #define WM_DAC_DIG_MASTER_ATTEN	0x11	/* DAC master digital attenuation */
62*4882a593Smuzhiyun #define WM_PHASE_SWAP		0x12	/* DAC phase */
63*4882a593Smuzhiyun #define WM_DAC_CTRL1		0x13	/* DAC control bits */
64*4882a593Smuzhiyun #define WM_MUTE			0x14	/* mute controls */
65*4882a593Smuzhiyun #define WM_DAC_CTRL2		0x15	/* de-emphasis and zefo-flag */
66*4882a593Smuzhiyun #define WM_INT_CTRL		0x16	/* interface control */
67*4882a593Smuzhiyun #define WM_MASTER		0x17	/* master clock and mode */
68*4882a593Smuzhiyun #define WM_POWERDOWN		0x18	/* power-down controls */
69*4882a593Smuzhiyun #define WM_ADC_GAIN		0x19	/* ADC gain L(19)/R(1a) */
70*4882a593Smuzhiyun #define WM_ADC_MUX		0x1b	/* input MUX */
71*4882a593Smuzhiyun #define WM_OUT_MUX1		0x1c	/* output MUX */
72*4882a593Smuzhiyun #define WM_OUT_MUX2		0x1e	/* output MUX */
73*4882a593Smuzhiyun #define WM_RESET		0x1f	/* software reset */
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* CS8415A registers */
76*4882a593Smuzhiyun #define CS8415_CTRL1	0x01
77*4882a593Smuzhiyun #define CS8415_CTRL2	0x02
78*4882a593Smuzhiyun #define CS8415_QSUB		0x14
79*4882a593Smuzhiyun #define CS8415_RATIO	0x1E
80*4882a593Smuzhiyun #define CS8415_C_BUFFER	0x20
81*4882a593Smuzhiyun #define CS8415_ID		0x7F
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /* PCA9554 registers */
84*4882a593Smuzhiyun #define PCA9554_DEV     0x40            /* I2C device address */
85*4882a593Smuzhiyun #define PCA9554_IN      0x00            /* input port */
86*4882a593Smuzhiyun #define PCA9554_OUT     0x01            /* output port */
87*4882a593Smuzhiyun #define PCA9554_INVERT  0x02            /* input invert */
88*4882a593Smuzhiyun #define PCA9554_DIR     0x03            /* port directions */
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun  * Aureon Universe additional controls using PCA9554
92*4882a593Smuzhiyun  */
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /*
95*4882a593Smuzhiyun  * Send data to pca9554
96*4882a593Smuzhiyun  */
aureon_pca9554_write(struct snd_ice1712 * ice,unsigned char reg,unsigned char data)97*4882a593Smuzhiyun static void aureon_pca9554_write(struct snd_ice1712 *ice, unsigned char reg,
98*4882a593Smuzhiyun 				 unsigned char data)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun 	unsigned int tmp;
101*4882a593Smuzhiyun 	int i, j;
102*4882a593Smuzhiyun 	unsigned char dev = PCA9554_DEV;  /* ID 0100000, write */
103*4882a593Smuzhiyun 	unsigned char val = 0;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	tmp = snd_ice1712_gpio_read(ice);
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	snd_ice1712_gpio_set_mask(ice, ~(AUREON_SPI_MOSI|AUREON_SPI_CLK|
108*4882a593Smuzhiyun 					 AUREON_WM_RW|AUREON_WM_CS|
109*4882a593Smuzhiyun 					 AUREON_CS8415_CS));
110*4882a593Smuzhiyun 	tmp |= AUREON_WM_RW;
111*4882a593Smuzhiyun 	tmp |= AUREON_CS8415_CS | AUREON_WM_CS; /* disable SPI devices */
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	tmp &= ~AUREON_SPI_MOSI;
114*4882a593Smuzhiyun 	tmp &= ~AUREON_SPI_CLK;
115*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
116*4882a593Smuzhiyun 	udelay(50);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/*
119*4882a593Smuzhiyun 	 * send i2c stop condition and start condition
120*4882a593Smuzhiyun 	 * to obtain sane state
121*4882a593Smuzhiyun 	 */
122*4882a593Smuzhiyun 	tmp |= AUREON_SPI_CLK;
123*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
124*4882a593Smuzhiyun 	udelay(50);
125*4882a593Smuzhiyun 	tmp |= AUREON_SPI_MOSI;
126*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
127*4882a593Smuzhiyun 	udelay(100);
128*4882a593Smuzhiyun 	tmp &= ~AUREON_SPI_MOSI;
129*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
130*4882a593Smuzhiyun 	udelay(50);
131*4882a593Smuzhiyun 	tmp &= ~AUREON_SPI_CLK;
132*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
133*4882a593Smuzhiyun 	udelay(100);
134*4882a593Smuzhiyun 	/*
135*4882a593Smuzhiyun 	 * send device address, command and value,
136*4882a593Smuzhiyun 	 * skipping ack cycles in between
137*4882a593Smuzhiyun 	 */
138*4882a593Smuzhiyun 	for (j = 0; j < 3; j++) {
139*4882a593Smuzhiyun 		switch (j) {
140*4882a593Smuzhiyun 		case 0:
141*4882a593Smuzhiyun 			val = dev;
142*4882a593Smuzhiyun 			break;
143*4882a593Smuzhiyun 		case 1:
144*4882a593Smuzhiyun 			val = reg;
145*4882a593Smuzhiyun 			break;
146*4882a593Smuzhiyun 		case 2:
147*4882a593Smuzhiyun 			val = data;
148*4882a593Smuzhiyun 			break;
149*4882a593Smuzhiyun 		}
150*4882a593Smuzhiyun 		for (i = 7; i >= 0; i--) {
151*4882a593Smuzhiyun 			tmp &= ~AUREON_SPI_CLK;
152*4882a593Smuzhiyun 			snd_ice1712_gpio_write(ice, tmp);
153*4882a593Smuzhiyun 			udelay(40);
154*4882a593Smuzhiyun 			if (val & (1 << i))
155*4882a593Smuzhiyun 				tmp |= AUREON_SPI_MOSI;
156*4882a593Smuzhiyun 			else
157*4882a593Smuzhiyun 				tmp &= ~AUREON_SPI_MOSI;
158*4882a593Smuzhiyun 			snd_ice1712_gpio_write(ice, tmp);
159*4882a593Smuzhiyun 			udelay(40);
160*4882a593Smuzhiyun 			tmp |= AUREON_SPI_CLK;
161*4882a593Smuzhiyun 			snd_ice1712_gpio_write(ice, tmp);
162*4882a593Smuzhiyun 			udelay(40);
163*4882a593Smuzhiyun 		}
164*4882a593Smuzhiyun 		tmp &= ~AUREON_SPI_CLK;
165*4882a593Smuzhiyun 		snd_ice1712_gpio_write(ice, tmp);
166*4882a593Smuzhiyun 		udelay(40);
167*4882a593Smuzhiyun 		tmp |= AUREON_SPI_CLK;
168*4882a593Smuzhiyun 		snd_ice1712_gpio_write(ice, tmp);
169*4882a593Smuzhiyun 		udelay(40);
170*4882a593Smuzhiyun 		tmp &= ~AUREON_SPI_CLK;
171*4882a593Smuzhiyun 		snd_ice1712_gpio_write(ice, tmp);
172*4882a593Smuzhiyun 		udelay(40);
173*4882a593Smuzhiyun 	}
174*4882a593Smuzhiyun 	tmp &= ~AUREON_SPI_CLK;
175*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
176*4882a593Smuzhiyun 	udelay(40);
177*4882a593Smuzhiyun 	tmp &= ~AUREON_SPI_MOSI;
178*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
179*4882a593Smuzhiyun 	udelay(40);
180*4882a593Smuzhiyun 	tmp |= AUREON_SPI_CLK;
181*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
182*4882a593Smuzhiyun 	udelay(50);
183*4882a593Smuzhiyun 	tmp |= AUREON_SPI_MOSI;
184*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
185*4882a593Smuzhiyun 	udelay(100);
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
aureon_universe_inmux_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)188*4882a593Smuzhiyun static int aureon_universe_inmux_info(struct snd_kcontrol *kcontrol,
189*4882a593Smuzhiyun 				      struct snd_ctl_elem_info *uinfo)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun 	static const char * const texts[3] =
192*4882a593Smuzhiyun 		{"Internal Aux", "Wavetable", "Rear Line-In"};
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	return snd_ctl_enum_info(uinfo, 1, 3, texts);
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun 
aureon_universe_inmux_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)197*4882a593Smuzhiyun static int aureon_universe_inmux_get(struct snd_kcontrol *kcontrol,
198*4882a593Smuzhiyun 				     struct snd_ctl_elem_value *ucontrol)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
201*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
202*4882a593Smuzhiyun 	ucontrol->value.enumerated.item[0] = spec->pca9554_out;
203*4882a593Smuzhiyun 	return 0;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun 
aureon_universe_inmux_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)206*4882a593Smuzhiyun static int aureon_universe_inmux_put(struct snd_kcontrol *kcontrol,
207*4882a593Smuzhiyun 				     struct snd_ctl_elem_value *ucontrol)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
210*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
211*4882a593Smuzhiyun 	unsigned char oval, nval;
212*4882a593Smuzhiyun 	int change;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	nval = ucontrol->value.enumerated.item[0];
215*4882a593Smuzhiyun 	if (nval >= 3)
216*4882a593Smuzhiyun 		return -EINVAL;
217*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
218*4882a593Smuzhiyun 	oval = spec->pca9554_out;
219*4882a593Smuzhiyun 	change = (oval != nval);
220*4882a593Smuzhiyun 	if (change) {
221*4882a593Smuzhiyun 		aureon_pca9554_write(ice, PCA9554_OUT, nval);
222*4882a593Smuzhiyun 		spec->pca9554_out = nval;
223*4882a593Smuzhiyun 	}
224*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
225*4882a593Smuzhiyun 	return change;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 
aureon_ac97_write(struct snd_ice1712 * ice,unsigned short reg,unsigned short val)229*4882a593Smuzhiyun static void aureon_ac97_write(struct snd_ice1712 *ice, unsigned short reg,
230*4882a593Smuzhiyun 			      unsigned short val)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
233*4882a593Smuzhiyun 	unsigned int tmp;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	/* Send address to XILINX chip */
236*4882a593Smuzhiyun 	tmp = (snd_ice1712_gpio_read(ice) & ~0xFF) | (reg & 0x7F);
237*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
238*4882a593Smuzhiyun 	udelay(10);
239*4882a593Smuzhiyun 	tmp |= AUREON_AC97_ADDR;
240*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
241*4882a593Smuzhiyun 	udelay(10);
242*4882a593Smuzhiyun 	tmp &= ~AUREON_AC97_ADDR;
243*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
244*4882a593Smuzhiyun 	udelay(10);
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	/* Send low-order byte to XILINX chip */
247*4882a593Smuzhiyun 	tmp &= ~AUREON_AC97_DATA_MASK;
248*4882a593Smuzhiyun 	tmp |= val & AUREON_AC97_DATA_MASK;
249*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
250*4882a593Smuzhiyun 	udelay(10);
251*4882a593Smuzhiyun 	tmp |= AUREON_AC97_DATA_LOW;
252*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
253*4882a593Smuzhiyun 	udelay(10);
254*4882a593Smuzhiyun 	tmp &= ~AUREON_AC97_DATA_LOW;
255*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
256*4882a593Smuzhiyun 	udelay(10);
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	/* Send high-order byte to XILINX chip */
259*4882a593Smuzhiyun 	tmp &= ~AUREON_AC97_DATA_MASK;
260*4882a593Smuzhiyun 	tmp |= (val >> 8) & AUREON_AC97_DATA_MASK;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
263*4882a593Smuzhiyun 	udelay(10);
264*4882a593Smuzhiyun 	tmp |= AUREON_AC97_DATA_HIGH;
265*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
266*4882a593Smuzhiyun 	udelay(10);
267*4882a593Smuzhiyun 	tmp &= ~AUREON_AC97_DATA_HIGH;
268*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
269*4882a593Smuzhiyun 	udelay(10);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	/* Instruct XILINX chip to parse the data to the STAC9744 chip */
272*4882a593Smuzhiyun 	tmp |= AUREON_AC97_COMMIT;
273*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
274*4882a593Smuzhiyun 	udelay(10);
275*4882a593Smuzhiyun 	tmp &= ~AUREON_AC97_COMMIT;
276*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
277*4882a593Smuzhiyun 	udelay(10);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	/* Store the data in out private buffer */
280*4882a593Smuzhiyun 	spec->stac9744[(reg & 0x7F) >> 1] = val;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
aureon_ac97_read(struct snd_ice1712 * ice,unsigned short reg)283*4882a593Smuzhiyun static unsigned short aureon_ac97_read(struct snd_ice1712 *ice, unsigned short reg)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
286*4882a593Smuzhiyun 	return spec->stac9744[(reg & 0x7F) >> 1];
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun /*
290*4882a593Smuzhiyun  * Initialize STAC9744 chip
291*4882a593Smuzhiyun  */
aureon_ac97_init(struct snd_ice1712 * ice)292*4882a593Smuzhiyun static int aureon_ac97_init(struct snd_ice1712 *ice)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
295*4882a593Smuzhiyun 	int i;
296*4882a593Smuzhiyun 	static const unsigned short ac97_defaults[] = {
297*4882a593Smuzhiyun 		0x00, 0x9640,
298*4882a593Smuzhiyun 		0x02, 0x8000,
299*4882a593Smuzhiyun 		0x04, 0x8000,
300*4882a593Smuzhiyun 		0x06, 0x8000,
301*4882a593Smuzhiyun 		0x0C, 0x8008,
302*4882a593Smuzhiyun 		0x0E, 0x8008,
303*4882a593Smuzhiyun 		0x10, 0x8808,
304*4882a593Smuzhiyun 		0x12, 0x8808,
305*4882a593Smuzhiyun 		0x14, 0x8808,
306*4882a593Smuzhiyun 		0x16, 0x8808,
307*4882a593Smuzhiyun 		0x18, 0x8808,
308*4882a593Smuzhiyun 		0x1C, 0x8000,
309*4882a593Smuzhiyun 		0x26, 0x000F,
310*4882a593Smuzhiyun 		0x28, 0x0201,
311*4882a593Smuzhiyun 		0x2C, 0xBB80,
312*4882a593Smuzhiyun 		0x32, 0xBB80,
313*4882a593Smuzhiyun 		0x7C, 0x8384,
314*4882a593Smuzhiyun 		0x7E, 0x7644,
315*4882a593Smuzhiyun 		(unsigned short)-1
316*4882a593Smuzhiyun 	};
317*4882a593Smuzhiyun 	unsigned int tmp;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	/* Cold reset */
320*4882a593Smuzhiyun 	tmp = (snd_ice1712_gpio_read(ice) | AUREON_AC97_RESET) & ~AUREON_AC97_DATA_MASK;
321*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
322*4882a593Smuzhiyun 	udelay(3);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	tmp &= ~AUREON_AC97_RESET;
325*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
326*4882a593Smuzhiyun 	udelay(3);
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	tmp |= AUREON_AC97_RESET;
329*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
330*4882a593Smuzhiyun 	udelay(3);
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	memset(&spec->stac9744, 0, sizeof(spec->stac9744));
333*4882a593Smuzhiyun 	for (i = 0; ac97_defaults[i] != (unsigned short)-1; i += 2)
334*4882a593Smuzhiyun 		spec->stac9744[(ac97_defaults[i]) >> 1] = ac97_defaults[i+1];
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	/* Unmute AC'97 master volume permanently - muting is done by WM8770 */
337*4882a593Smuzhiyun 	aureon_ac97_write(ice, AC97_MASTER, 0x0000);
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	return 0;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun #define AUREON_AC97_STEREO	0x80
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun /*
345*4882a593Smuzhiyun  * AC'97 volume controls
346*4882a593Smuzhiyun  */
aureon_ac97_vol_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)347*4882a593Smuzhiyun static int aureon_ac97_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
350*4882a593Smuzhiyun 	uinfo->count = kcontrol->private_value & AUREON_AC97_STEREO ? 2 : 1;
351*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
352*4882a593Smuzhiyun 	uinfo->value.integer.max = 31;
353*4882a593Smuzhiyun 	return 0;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun 
aureon_ac97_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)356*4882a593Smuzhiyun static int aureon_ac97_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
359*4882a593Smuzhiyun 	unsigned short vol;
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	vol = aureon_ac97_read(ice, kcontrol->private_value & 0x7F);
364*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = 0x1F - (vol & 0x1F);
365*4882a593Smuzhiyun 	if (kcontrol->private_value & AUREON_AC97_STEREO)
366*4882a593Smuzhiyun 		ucontrol->value.integer.value[1] = 0x1F - ((vol >> 8) & 0x1F);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
369*4882a593Smuzhiyun 	return 0;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun 
aureon_ac97_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)372*4882a593Smuzhiyun static int aureon_ac97_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
375*4882a593Smuzhiyun 	unsigned short ovol, nvol;
376*4882a593Smuzhiyun 	int change;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	ovol = aureon_ac97_read(ice, kcontrol->private_value & 0x7F);
381*4882a593Smuzhiyun 	nvol = (0x1F - ucontrol->value.integer.value[0]) & 0x001F;
382*4882a593Smuzhiyun 	if (kcontrol->private_value & AUREON_AC97_STEREO)
383*4882a593Smuzhiyun 		nvol |= ((0x1F - ucontrol->value.integer.value[1]) << 8) & 0x1F00;
384*4882a593Smuzhiyun 	nvol |= ovol & ~0x1F1F;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	change = (ovol != nvol);
387*4882a593Smuzhiyun 	if (change)
388*4882a593Smuzhiyun 		aureon_ac97_write(ice, kcontrol->private_value & 0x7F, nvol);
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	return change;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun /*
396*4882a593Smuzhiyun  * AC'97 mute controls
397*4882a593Smuzhiyun  */
398*4882a593Smuzhiyun #define aureon_ac97_mute_info	snd_ctl_boolean_mono_info
399*4882a593Smuzhiyun 
aureon_ac97_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)400*4882a593Smuzhiyun static int aureon_ac97_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
401*4882a593Smuzhiyun {
402*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = aureon_ac97_read(ice,
407*4882a593Smuzhiyun 			kcontrol->private_value & 0x7F) & 0x8000 ? 0 : 1;
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
410*4882a593Smuzhiyun 	return 0;
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun 
aureon_ac97_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)413*4882a593Smuzhiyun static int aureon_ac97_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
414*4882a593Smuzhiyun {
415*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
416*4882a593Smuzhiyun 	unsigned short ovol, nvol;
417*4882a593Smuzhiyun 	int change;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	ovol = aureon_ac97_read(ice, kcontrol->private_value & 0x7F);
422*4882a593Smuzhiyun 	nvol = (ucontrol->value.integer.value[0] ? 0x0000 : 0x8000) | (ovol & ~0x8000);
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	change = (ovol != nvol);
425*4882a593Smuzhiyun 	if (change)
426*4882a593Smuzhiyun 		aureon_ac97_write(ice, kcontrol->private_value & 0x7F, nvol);
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	return change;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun /*
434*4882a593Smuzhiyun  * AC'97 mute controls
435*4882a593Smuzhiyun  */
436*4882a593Smuzhiyun #define aureon_ac97_micboost_info	snd_ctl_boolean_mono_info
437*4882a593Smuzhiyun 
aureon_ac97_micboost_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)438*4882a593Smuzhiyun static int aureon_ac97_micboost_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = aureon_ac97_read(ice, AC97_MIC) & 0x0020 ? 0 : 1;
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
447*4882a593Smuzhiyun 	return 0;
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun 
aureon_ac97_micboost_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)450*4882a593Smuzhiyun static int aureon_ac97_micboost_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
453*4882a593Smuzhiyun 	unsigned short ovol, nvol;
454*4882a593Smuzhiyun 	int change;
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	ovol = aureon_ac97_read(ice, AC97_MIC);
459*4882a593Smuzhiyun 	nvol = (ucontrol->value.integer.value[0] ? 0x0000 : 0x0020) | (ovol & ~0x0020);
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	change = (ovol != nvol);
462*4882a593Smuzhiyun 	if (change)
463*4882a593Smuzhiyun 		aureon_ac97_write(ice, AC97_MIC, nvol);
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	return change;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun /*
471*4882a593Smuzhiyun  * write data in the SPI mode
472*4882a593Smuzhiyun  */
aureon_spi_write(struct snd_ice1712 * ice,unsigned int cs,unsigned int data,int bits)473*4882a593Smuzhiyun static void aureon_spi_write(struct snd_ice1712 *ice, unsigned int cs, unsigned int data, int bits)
474*4882a593Smuzhiyun {
475*4882a593Smuzhiyun 	unsigned int tmp;
476*4882a593Smuzhiyun 	int i;
477*4882a593Smuzhiyun 	unsigned int mosi, clk;
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	tmp = snd_ice1712_gpio_read(ice);
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	if (ice->eeprom.subvendor == VT1724_SUBDEVICE_PRODIGY71LT ||
482*4882a593Smuzhiyun 	    ice->eeprom.subvendor == VT1724_SUBDEVICE_PRODIGY71XT) {
483*4882a593Smuzhiyun 		snd_ice1712_gpio_set_mask(ice, ~(PRODIGY_SPI_MOSI|PRODIGY_SPI_CLK|PRODIGY_WM_CS));
484*4882a593Smuzhiyun 		mosi = PRODIGY_SPI_MOSI;
485*4882a593Smuzhiyun 		clk = PRODIGY_SPI_CLK;
486*4882a593Smuzhiyun 	} else {
487*4882a593Smuzhiyun 		snd_ice1712_gpio_set_mask(ice, ~(AUREON_WM_RW|AUREON_SPI_MOSI|AUREON_SPI_CLK|
488*4882a593Smuzhiyun 						 AUREON_WM_CS|AUREON_CS8415_CS));
489*4882a593Smuzhiyun 		mosi = AUREON_SPI_MOSI;
490*4882a593Smuzhiyun 		clk = AUREON_SPI_CLK;
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 		tmp |= AUREON_WM_RW;
493*4882a593Smuzhiyun 	}
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	tmp &= ~cs;
496*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
497*4882a593Smuzhiyun 	udelay(1);
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	for (i = bits - 1; i >= 0; i--) {
500*4882a593Smuzhiyun 		tmp &= ~clk;
501*4882a593Smuzhiyun 		snd_ice1712_gpio_write(ice, tmp);
502*4882a593Smuzhiyun 		udelay(1);
503*4882a593Smuzhiyun 		if (data & (1 << i))
504*4882a593Smuzhiyun 			tmp |= mosi;
505*4882a593Smuzhiyun 		else
506*4882a593Smuzhiyun 			tmp &= ~mosi;
507*4882a593Smuzhiyun 		snd_ice1712_gpio_write(ice, tmp);
508*4882a593Smuzhiyun 		udelay(1);
509*4882a593Smuzhiyun 		tmp |= clk;
510*4882a593Smuzhiyun 		snd_ice1712_gpio_write(ice, tmp);
511*4882a593Smuzhiyun 		udelay(1);
512*4882a593Smuzhiyun 	}
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	tmp &= ~clk;
515*4882a593Smuzhiyun 	tmp |= cs;
516*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
517*4882a593Smuzhiyun 	udelay(1);
518*4882a593Smuzhiyun 	tmp |= clk;
519*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
520*4882a593Smuzhiyun 	udelay(1);
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun /*
524*4882a593Smuzhiyun  * Read data in SPI mode
525*4882a593Smuzhiyun  */
aureon_spi_read(struct snd_ice1712 * ice,unsigned int cs,unsigned int data,int bits,unsigned char * buffer,int size)526*4882a593Smuzhiyun static void aureon_spi_read(struct snd_ice1712 *ice, unsigned int cs,
527*4882a593Smuzhiyun 		unsigned int data, int bits, unsigned char *buffer, int size)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun 	int i, j;
530*4882a593Smuzhiyun 	unsigned int tmp;
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	tmp = (snd_ice1712_gpio_read(ice) & ~AUREON_SPI_CLK) | AUREON_CS8415_CS|AUREON_WM_CS;
533*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
534*4882a593Smuzhiyun 	tmp &= ~cs;
535*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
536*4882a593Smuzhiyun 	udelay(1);
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	for (i = bits-1; i >= 0; i--) {
539*4882a593Smuzhiyun 		if (data & (1 << i))
540*4882a593Smuzhiyun 			tmp |= AUREON_SPI_MOSI;
541*4882a593Smuzhiyun 		else
542*4882a593Smuzhiyun 			tmp &= ~AUREON_SPI_MOSI;
543*4882a593Smuzhiyun 		snd_ice1712_gpio_write(ice, tmp);
544*4882a593Smuzhiyun 		udelay(1);
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 		tmp |= AUREON_SPI_CLK;
547*4882a593Smuzhiyun 		snd_ice1712_gpio_write(ice, tmp);
548*4882a593Smuzhiyun 		udelay(1);
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 		tmp &= ~AUREON_SPI_CLK;
551*4882a593Smuzhiyun 		snd_ice1712_gpio_write(ice, tmp);
552*4882a593Smuzhiyun 		udelay(1);
553*4882a593Smuzhiyun 	}
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	for (j = 0; j < size; j++) {
556*4882a593Smuzhiyun 		unsigned char outdata = 0;
557*4882a593Smuzhiyun 		for (i = 7; i >= 0; i--) {
558*4882a593Smuzhiyun 			tmp = snd_ice1712_gpio_read(ice);
559*4882a593Smuzhiyun 			outdata <<= 1;
560*4882a593Smuzhiyun 			outdata |= (tmp & AUREON_SPI_MISO) ? 1 : 0;
561*4882a593Smuzhiyun 			udelay(1);
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 			tmp |= AUREON_SPI_CLK;
564*4882a593Smuzhiyun 			snd_ice1712_gpio_write(ice, tmp);
565*4882a593Smuzhiyun 			udelay(1);
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 			tmp &= ~AUREON_SPI_CLK;
568*4882a593Smuzhiyun 			snd_ice1712_gpio_write(ice, tmp);
569*4882a593Smuzhiyun 			udelay(1);
570*4882a593Smuzhiyun 		}
571*4882a593Smuzhiyun 		buffer[j] = outdata;
572*4882a593Smuzhiyun 	}
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun 	tmp |= cs;
575*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun 
aureon_cs8415_get(struct snd_ice1712 * ice,int reg)578*4882a593Smuzhiyun static unsigned char aureon_cs8415_get(struct snd_ice1712 *ice, int reg)
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun 	unsigned char val;
581*4882a593Smuzhiyun 	aureon_spi_write(ice, AUREON_CS8415_CS, 0x2000 | reg, 16);
582*4882a593Smuzhiyun 	aureon_spi_read(ice, AUREON_CS8415_CS, 0x21, 8, &val, 1);
583*4882a593Smuzhiyun 	return val;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun 
aureon_cs8415_read(struct snd_ice1712 * ice,int reg,unsigned char * buffer,int size)586*4882a593Smuzhiyun static void aureon_cs8415_read(struct snd_ice1712 *ice, int reg,
587*4882a593Smuzhiyun 				unsigned char *buffer, int size)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun 	aureon_spi_write(ice, AUREON_CS8415_CS, 0x2000 | reg, 16);
590*4882a593Smuzhiyun 	aureon_spi_read(ice, AUREON_CS8415_CS, 0x21, 8, buffer, size);
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun 
aureon_cs8415_put(struct snd_ice1712 * ice,int reg,unsigned char val)593*4882a593Smuzhiyun static void aureon_cs8415_put(struct snd_ice1712 *ice, int reg,
594*4882a593Smuzhiyun 						unsigned char val)
595*4882a593Smuzhiyun {
596*4882a593Smuzhiyun 	aureon_spi_write(ice, AUREON_CS8415_CS, 0x200000 | (reg << 8) | val, 24);
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun /*
600*4882a593Smuzhiyun  * get the current register value of WM codec
601*4882a593Smuzhiyun  */
wm_get(struct snd_ice1712 * ice,int reg)602*4882a593Smuzhiyun static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
603*4882a593Smuzhiyun {
604*4882a593Smuzhiyun 	reg <<= 1;
605*4882a593Smuzhiyun 	return ((unsigned short)ice->akm[0].images[reg] << 8) |
606*4882a593Smuzhiyun 		ice->akm[0].images[reg + 1];
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun /*
610*4882a593Smuzhiyun  * set the register value of WM codec
611*4882a593Smuzhiyun  */
wm_put_nocache(struct snd_ice1712 * ice,int reg,unsigned short val)612*4882a593Smuzhiyun static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
613*4882a593Smuzhiyun {
614*4882a593Smuzhiyun 	aureon_spi_write(ice,
615*4882a593Smuzhiyun 			 ((ice->eeprom.subvendor == VT1724_SUBDEVICE_PRODIGY71LT ||
616*4882a593Smuzhiyun 			   ice->eeprom.subvendor == VT1724_SUBDEVICE_PRODIGY71XT) ?
617*4882a593Smuzhiyun 			 PRODIGY_WM_CS : AUREON_WM_CS),
618*4882a593Smuzhiyun 			(reg << 9) | (val & 0x1ff), 16);
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun /*
622*4882a593Smuzhiyun  * set the register value of WM codec and remember it
623*4882a593Smuzhiyun  */
wm_put(struct snd_ice1712 * ice,int reg,unsigned short val)624*4882a593Smuzhiyun static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
625*4882a593Smuzhiyun {
626*4882a593Smuzhiyun 	wm_put_nocache(ice, reg, val);
627*4882a593Smuzhiyun 	reg <<= 1;
628*4882a593Smuzhiyun 	ice->akm[0].images[reg] = val >> 8;
629*4882a593Smuzhiyun 	ice->akm[0].images[reg + 1] = val;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun /*
633*4882a593Smuzhiyun  */
634*4882a593Smuzhiyun #define aureon_mono_bool_info		snd_ctl_boolean_mono_info
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun /*
637*4882a593Smuzhiyun  * AC'97 master playback mute controls (Mute on WM8770 chip)
638*4882a593Smuzhiyun  */
639*4882a593Smuzhiyun #define aureon_ac97_mmute_info		snd_ctl_boolean_mono_info
640*4882a593Smuzhiyun 
aureon_ac97_mmute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)641*4882a593Smuzhiyun static int aureon_ac97_mmute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (wm_get(ice, WM_OUT_MUX1) >> 1) & 0x01;
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
650*4882a593Smuzhiyun 	return 0;
651*4882a593Smuzhiyun }
652*4882a593Smuzhiyun 
aureon_ac97_mmute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)653*4882a593Smuzhiyun static int aureon_ac97_mmute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
654*4882a593Smuzhiyun {
655*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
656*4882a593Smuzhiyun 	unsigned short ovol, nvol;
657*4882a593Smuzhiyun 	int change;
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	ovol = wm_get(ice, WM_OUT_MUX1);
662*4882a593Smuzhiyun 	nvol = (ovol & ~0x02) | (ucontrol->value.integer.value[0] ? 0x02 : 0x00);
663*4882a593Smuzhiyun 	change = (ovol != nvol);
664*4882a593Smuzhiyun 	if (change)
665*4882a593Smuzhiyun 		wm_put(ice, WM_OUT_MUX1, nvol);
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun 	return change;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -10000, 100, 1);
673*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_wm_pcm, -6400, 50, 1);
674*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_wm_adc, -1200, 100, 0);
675*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_ac97_master, -4650, 150, 0);
676*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_ac97_gain, -3450, 150, 0);
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun #define WM_VOL_MAX	100
679*4882a593Smuzhiyun #define WM_VOL_CNT	101	/* 0dB .. -100dB */
680*4882a593Smuzhiyun #define WM_VOL_MUTE	0x8000
681*4882a593Smuzhiyun 
wm_set_vol(struct snd_ice1712 * ice,unsigned int index,unsigned short vol,unsigned short master)682*4882a593Smuzhiyun static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index, unsigned short vol, unsigned short master)
683*4882a593Smuzhiyun {
684*4882a593Smuzhiyun 	unsigned char nvol;
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun 	if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE)) {
687*4882a593Smuzhiyun 		nvol = 0;
688*4882a593Smuzhiyun 	} else {
689*4882a593Smuzhiyun 		nvol = ((vol % WM_VOL_CNT) * (master % WM_VOL_CNT)) /
690*4882a593Smuzhiyun 								WM_VOL_MAX;
691*4882a593Smuzhiyun 		nvol += 0x1b;
692*4882a593Smuzhiyun 	}
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	wm_put(ice, index, nvol);
695*4882a593Smuzhiyun 	wm_put_nocache(ice, index, 0x180 | nvol);
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun /*
699*4882a593Smuzhiyun  * DAC mute control
700*4882a593Smuzhiyun  */
701*4882a593Smuzhiyun #define wm_pcm_mute_info	snd_ctl_boolean_mono_info
702*4882a593Smuzhiyun 
wm_pcm_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)703*4882a593Smuzhiyun static int wm_pcm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
708*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (wm_get(ice, WM_MUTE) & 0x10) ? 0 : 1;
709*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
710*4882a593Smuzhiyun 	return 0;
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun 
wm_pcm_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)713*4882a593Smuzhiyun static int wm_pcm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
716*4882a593Smuzhiyun 	unsigned short nval, oval;
717*4882a593Smuzhiyun 	int change;
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
720*4882a593Smuzhiyun 	oval = wm_get(ice, WM_MUTE);
721*4882a593Smuzhiyun 	nval = (oval & ~0x10) | (ucontrol->value.integer.value[0] ? 0 : 0x10);
722*4882a593Smuzhiyun 	change = (oval != nval);
723*4882a593Smuzhiyun 	if (change)
724*4882a593Smuzhiyun 		wm_put(ice, WM_MUTE, nval);
725*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	return change;
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun 
730*4882a593Smuzhiyun /*
731*4882a593Smuzhiyun  * Master volume attenuation mixer control
732*4882a593Smuzhiyun  */
wm_master_vol_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)733*4882a593Smuzhiyun static int wm_master_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
734*4882a593Smuzhiyun {
735*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
736*4882a593Smuzhiyun 	uinfo->count = 2;
737*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
738*4882a593Smuzhiyun 	uinfo->value.integer.max = WM_VOL_MAX;
739*4882a593Smuzhiyun 	return 0;
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun 
wm_master_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)742*4882a593Smuzhiyun static int wm_master_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
743*4882a593Smuzhiyun {
744*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
745*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
746*4882a593Smuzhiyun 	int i;
747*4882a593Smuzhiyun 	for (i = 0; i < 2; i++)
748*4882a593Smuzhiyun 		ucontrol->value.integer.value[i] =
749*4882a593Smuzhiyun 			spec->master[i] & ~WM_VOL_MUTE;
750*4882a593Smuzhiyun 	return 0;
751*4882a593Smuzhiyun }
752*4882a593Smuzhiyun 
wm_master_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)753*4882a593Smuzhiyun static int wm_master_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
754*4882a593Smuzhiyun {
755*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
756*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
757*4882a593Smuzhiyun 	int ch, change = 0;
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
760*4882a593Smuzhiyun 	for (ch = 0; ch < 2; ch++) {
761*4882a593Smuzhiyun 		unsigned int vol = ucontrol->value.integer.value[ch];
762*4882a593Smuzhiyun 		if (vol > WM_VOL_MAX)
763*4882a593Smuzhiyun 			vol = WM_VOL_MAX;
764*4882a593Smuzhiyun 		vol |= spec->master[ch] & WM_VOL_MUTE;
765*4882a593Smuzhiyun 		if (vol != spec->master[ch]) {
766*4882a593Smuzhiyun 			int dac;
767*4882a593Smuzhiyun 			spec->master[ch] = vol;
768*4882a593Smuzhiyun 			for (dac = 0; dac < ice->num_total_dacs; dac += 2)
769*4882a593Smuzhiyun 				wm_set_vol(ice, WM_DAC_ATTEN + dac + ch,
770*4882a593Smuzhiyun 					   spec->vol[dac + ch],
771*4882a593Smuzhiyun 					   spec->master[ch]);
772*4882a593Smuzhiyun 			change = 1;
773*4882a593Smuzhiyun 		}
774*4882a593Smuzhiyun 	}
775*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
776*4882a593Smuzhiyun 	return change;
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun 
779*4882a593Smuzhiyun /*
780*4882a593Smuzhiyun  * DAC volume attenuation mixer control
781*4882a593Smuzhiyun  */
wm_vol_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)782*4882a593Smuzhiyun static int wm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
783*4882a593Smuzhiyun {
784*4882a593Smuzhiyun 	int voices = kcontrol->private_value >> 8;
785*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
786*4882a593Smuzhiyun 	uinfo->count = voices;
787*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;		/* mute (-101dB) */
788*4882a593Smuzhiyun 	uinfo->value.integer.max = WM_VOL_MAX;	/* 0dB */
789*4882a593Smuzhiyun 	return 0;
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun 
wm_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)792*4882a593Smuzhiyun static int wm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
793*4882a593Smuzhiyun {
794*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
795*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
796*4882a593Smuzhiyun 	int i, ofs, voices;
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 	voices = kcontrol->private_value >> 8;
799*4882a593Smuzhiyun 	ofs = kcontrol->private_value & 0xff;
800*4882a593Smuzhiyun 	for (i = 0; i < voices; i++)
801*4882a593Smuzhiyun 		ucontrol->value.integer.value[i] =
802*4882a593Smuzhiyun 			spec->vol[ofs+i] & ~WM_VOL_MUTE;
803*4882a593Smuzhiyun 	return 0;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun 
wm_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)806*4882a593Smuzhiyun static int wm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
807*4882a593Smuzhiyun {
808*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
809*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
810*4882a593Smuzhiyun 	int i, idx, ofs, voices;
811*4882a593Smuzhiyun 	int change = 0;
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun 	voices = kcontrol->private_value >> 8;
814*4882a593Smuzhiyun 	ofs = kcontrol->private_value & 0xff;
815*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
816*4882a593Smuzhiyun 	for (i = 0; i < voices; i++) {
817*4882a593Smuzhiyun 		unsigned int vol = ucontrol->value.integer.value[i];
818*4882a593Smuzhiyun 		if (vol > WM_VOL_MAX)
819*4882a593Smuzhiyun 			vol = WM_VOL_MAX;
820*4882a593Smuzhiyun 		vol |= spec->vol[ofs+i] & WM_VOL_MUTE;
821*4882a593Smuzhiyun 		if (vol != spec->vol[ofs+i]) {
822*4882a593Smuzhiyun 			spec->vol[ofs+i] = vol;
823*4882a593Smuzhiyun 			idx  = WM_DAC_ATTEN + ofs + i;
824*4882a593Smuzhiyun 			wm_set_vol(ice, idx, spec->vol[ofs + i],
825*4882a593Smuzhiyun 				   spec->master[i]);
826*4882a593Smuzhiyun 			change = 1;
827*4882a593Smuzhiyun 		}
828*4882a593Smuzhiyun 	}
829*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
830*4882a593Smuzhiyun 	return change;
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun /*
834*4882a593Smuzhiyun  * WM8770 mute control
835*4882a593Smuzhiyun  */
wm_mute_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)836*4882a593Smuzhiyun static int wm_mute_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
839*4882a593Smuzhiyun 	uinfo->count = kcontrol->private_value >> 8;
840*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
841*4882a593Smuzhiyun 	uinfo->value.integer.max = 1;
842*4882a593Smuzhiyun 	return 0;
843*4882a593Smuzhiyun }
844*4882a593Smuzhiyun 
wm_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)845*4882a593Smuzhiyun static int wm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
846*4882a593Smuzhiyun {
847*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
848*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
849*4882a593Smuzhiyun 	int voices, ofs, i;
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	voices = kcontrol->private_value >> 8;
852*4882a593Smuzhiyun 	ofs = kcontrol->private_value & 0xFF;
853*4882a593Smuzhiyun 
854*4882a593Smuzhiyun 	for (i = 0; i < voices; i++)
855*4882a593Smuzhiyun 		ucontrol->value.integer.value[i] =
856*4882a593Smuzhiyun 			(spec->vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1;
857*4882a593Smuzhiyun 	return 0;
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun 
wm_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)860*4882a593Smuzhiyun static int wm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
861*4882a593Smuzhiyun {
862*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
863*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
864*4882a593Smuzhiyun 	int change = 0, voices, ofs, i;
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun 	voices = kcontrol->private_value >> 8;
867*4882a593Smuzhiyun 	ofs = kcontrol->private_value & 0xFF;
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
870*4882a593Smuzhiyun 	for (i = 0; i < voices; i++) {
871*4882a593Smuzhiyun 		int val = (spec->vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1;
872*4882a593Smuzhiyun 		if (ucontrol->value.integer.value[i] != val) {
873*4882a593Smuzhiyun 			spec->vol[ofs + i] &= ~WM_VOL_MUTE;
874*4882a593Smuzhiyun 			spec->vol[ofs + i] |=
875*4882a593Smuzhiyun 				ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
876*4882a593Smuzhiyun 			wm_set_vol(ice, ofs + i, spec->vol[ofs + i],
877*4882a593Smuzhiyun 				   spec->master[i]);
878*4882a593Smuzhiyun 			change = 1;
879*4882a593Smuzhiyun 		}
880*4882a593Smuzhiyun 	}
881*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
882*4882a593Smuzhiyun 
883*4882a593Smuzhiyun 	return change;
884*4882a593Smuzhiyun }
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun /*
887*4882a593Smuzhiyun  * WM8770 master mute control
888*4882a593Smuzhiyun  */
889*4882a593Smuzhiyun #define wm_master_mute_info		snd_ctl_boolean_stereo_info
890*4882a593Smuzhiyun 
wm_master_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)891*4882a593Smuzhiyun static int wm_master_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
892*4882a593Smuzhiyun {
893*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
894*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
895*4882a593Smuzhiyun 
896*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] =
897*4882a593Smuzhiyun 		(spec->master[0] & WM_VOL_MUTE) ? 0 : 1;
898*4882a593Smuzhiyun 	ucontrol->value.integer.value[1] =
899*4882a593Smuzhiyun 		(spec->master[1] & WM_VOL_MUTE) ? 0 : 1;
900*4882a593Smuzhiyun 	return 0;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun 
wm_master_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)903*4882a593Smuzhiyun static int wm_master_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
904*4882a593Smuzhiyun {
905*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
906*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
907*4882a593Smuzhiyun 	int change = 0, i;
908*4882a593Smuzhiyun 
909*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
910*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
911*4882a593Smuzhiyun 		int val = (spec->master[i] & WM_VOL_MUTE) ? 0 : 1;
912*4882a593Smuzhiyun 		if (ucontrol->value.integer.value[i] != val) {
913*4882a593Smuzhiyun 			int dac;
914*4882a593Smuzhiyun 			spec->master[i] &= ~WM_VOL_MUTE;
915*4882a593Smuzhiyun 			spec->master[i] |=
916*4882a593Smuzhiyun 				ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
917*4882a593Smuzhiyun 			for (dac = 0; dac < ice->num_total_dacs; dac += 2)
918*4882a593Smuzhiyun 				wm_set_vol(ice, WM_DAC_ATTEN + dac + i,
919*4882a593Smuzhiyun 					   spec->vol[dac + i],
920*4882a593Smuzhiyun 					   spec->master[i]);
921*4882a593Smuzhiyun 			change = 1;
922*4882a593Smuzhiyun 		}
923*4882a593Smuzhiyun 	}
924*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
925*4882a593Smuzhiyun 
926*4882a593Smuzhiyun 	return change;
927*4882a593Smuzhiyun }
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun /* digital master volume */
930*4882a593Smuzhiyun #define PCM_0dB 0xff
931*4882a593Smuzhiyun #define PCM_RES 128	/* -64dB */
932*4882a593Smuzhiyun #define PCM_MIN (PCM_0dB - PCM_RES)
wm_pcm_vol_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)933*4882a593Smuzhiyun static int wm_pcm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
934*4882a593Smuzhiyun {
935*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
936*4882a593Smuzhiyun 	uinfo->count = 1;
937*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;		/* mute (-64dB) */
938*4882a593Smuzhiyun 	uinfo->value.integer.max = PCM_RES;	/* 0dB */
939*4882a593Smuzhiyun 	return 0;
940*4882a593Smuzhiyun }
941*4882a593Smuzhiyun 
wm_pcm_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)942*4882a593Smuzhiyun static int wm_pcm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
943*4882a593Smuzhiyun {
944*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
945*4882a593Smuzhiyun 	unsigned short val;
946*4882a593Smuzhiyun 
947*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
948*4882a593Smuzhiyun 	val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
949*4882a593Smuzhiyun 	val = val > PCM_MIN ? (val - PCM_MIN) : 0;
950*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = val;
951*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
952*4882a593Smuzhiyun 	return 0;
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun 
wm_pcm_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)955*4882a593Smuzhiyun static int wm_pcm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
956*4882a593Smuzhiyun {
957*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
958*4882a593Smuzhiyun 	unsigned short ovol, nvol;
959*4882a593Smuzhiyun 	int change = 0;
960*4882a593Smuzhiyun 
961*4882a593Smuzhiyun 	nvol = ucontrol->value.integer.value[0];
962*4882a593Smuzhiyun 	if (nvol > PCM_RES)
963*4882a593Smuzhiyun 		return -EINVAL;
964*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
965*4882a593Smuzhiyun 	nvol = (nvol ? (nvol + PCM_MIN) : 0) & 0xff;
966*4882a593Smuzhiyun 	ovol = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
967*4882a593Smuzhiyun 	if (ovol != nvol) {
968*4882a593Smuzhiyun 		wm_put(ice, WM_DAC_DIG_MASTER_ATTEN, nvol); /* prelatch */
969*4882a593Smuzhiyun 		wm_put_nocache(ice, WM_DAC_DIG_MASTER_ATTEN, nvol | 0x100); /* update */
970*4882a593Smuzhiyun 		change = 1;
971*4882a593Smuzhiyun 	}
972*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
973*4882a593Smuzhiyun 	return change;
974*4882a593Smuzhiyun }
975*4882a593Smuzhiyun 
976*4882a593Smuzhiyun /*
977*4882a593Smuzhiyun  * ADC mute control
978*4882a593Smuzhiyun  */
979*4882a593Smuzhiyun #define wm_adc_mute_info		snd_ctl_boolean_stereo_info
980*4882a593Smuzhiyun 
wm_adc_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)981*4882a593Smuzhiyun static int wm_adc_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
982*4882a593Smuzhiyun {
983*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
984*4882a593Smuzhiyun 	unsigned short val;
985*4882a593Smuzhiyun 	int i;
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
988*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
989*4882a593Smuzhiyun 		val = wm_get(ice, WM_ADC_GAIN + i);
990*4882a593Smuzhiyun 		ucontrol->value.integer.value[i] = ~val>>5 & 0x1;
991*4882a593Smuzhiyun 	}
992*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
993*4882a593Smuzhiyun 	return 0;
994*4882a593Smuzhiyun }
995*4882a593Smuzhiyun 
wm_adc_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)996*4882a593Smuzhiyun static int wm_adc_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
997*4882a593Smuzhiyun {
998*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
999*4882a593Smuzhiyun 	unsigned short new, old;
1000*4882a593Smuzhiyun 	int i, change = 0;
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
1003*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
1004*4882a593Smuzhiyun 		old = wm_get(ice, WM_ADC_GAIN + i);
1005*4882a593Smuzhiyun 		new = (~ucontrol->value.integer.value[i]<<5&0x20) | (old&~0x20);
1006*4882a593Smuzhiyun 		if (new != old) {
1007*4882a593Smuzhiyun 			wm_put(ice, WM_ADC_GAIN + i, new);
1008*4882a593Smuzhiyun 			change = 1;
1009*4882a593Smuzhiyun 		}
1010*4882a593Smuzhiyun 	}
1011*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
1012*4882a593Smuzhiyun 
1013*4882a593Smuzhiyun 	return change;
1014*4882a593Smuzhiyun }
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun /*
1017*4882a593Smuzhiyun  * ADC gain mixer control
1018*4882a593Smuzhiyun  */
wm_adc_vol_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1019*4882a593Smuzhiyun static int wm_adc_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1020*4882a593Smuzhiyun {
1021*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1022*4882a593Smuzhiyun 	uinfo->count = 2;
1023*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;		/* -12dB */
1024*4882a593Smuzhiyun 	uinfo->value.integer.max = 0x1f;	/* 19dB */
1025*4882a593Smuzhiyun 	return 0;
1026*4882a593Smuzhiyun }
1027*4882a593Smuzhiyun 
wm_adc_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1028*4882a593Smuzhiyun static int wm_adc_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1029*4882a593Smuzhiyun {
1030*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1031*4882a593Smuzhiyun 	int i, idx;
1032*4882a593Smuzhiyun 	unsigned short vol;
1033*4882a593Smuzhiyun 
1034*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
1035*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
1036*4882a593Smuzhiyun 		idx = WM_ADC_GAIN + i;
1037*4882a593Smuzhiyun 		vol = wm_get(ice, idx) & 0x1f;
1038*4882a593Smuzhiyun 		ucontrol->value.integer.value[i] = vol;
1039*4882a593Smuzhiyun 	}
1040*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
1041*4882a593Smuzhiyun 	return 0;
1042*4882a593Smuzhiyun }
1043*4882a593Smuzhiyun 
wm_adc_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1044*4882a593Smuzhiyun static int wm_adc_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1045*4882a593Smuzhiyun {
1046*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1047*4882a593Smuzhiyun 	int i, idx;
1048*4882a593Smuzhiyun 	unsigned short ovol, nvol;
1049*4882a593Smuzhiyun 	int change = 0;
1050*4882a593Smuzhiyun 
1051*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
1052*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
1053*4882a593Smuzhiyun 		idx  = WM_ADC_GAIN + i;
1054*4882a593Smuzhiyun 		nvol = ucontrol->value.integer.value[i] & 0x1f;
1055*4882a593Smuzhiyun 		ovol = wm_get(ice, idx);
1056*4882a593Smuzhiyun 		if ((ovol & 0x1f) != nvol) {
1057*4882a593Smuzhiyun 			wm_put(ice, idx, nvol | (ovol & ~0x1f));
1058*4882a593Smuzhiyun 			change = 1;
1059*4882a593Smuzhiyun 		}
1060*4882a593Smuzhiyun 	}
1061*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
1062*4882a593Smuzhiyun 	return change;
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun 
1065*4882a593Smuzhiyun /*
1066*4882a593Smuzhiyun  * ADC input mux mixer control
1067*4882a593Smuzhiyun  */
wm_adc_mux_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1068*4882a593Smuzhiyun static int wm_adc_mux_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1069*4882a593Smuzhiyun {
1070*4882a593Smuzhiyun 	static const char * const texts[] = {
1071*4882a593Smuzhiyun 		"CD",		/* AIN1 */
1072*4882a593Smuzhiyun 		"Aux",		/* AIN2 */
1073*4882a593Smuzhiyun 		"Line",		/* AIN3 */
1074*4882a593Smuzhiyun 		"Mic",		/* AIN4 */
1075*4882a593Smuzhiyun 		"AC97"		/* AIN5 */
1076*4882a593Smuzhiyun 	};
1077*4882a593Smuzhiyun 	static const char * const universe_texts[] = {
1078*4882a593Smuzhiyun 		"Aux1",		/* AIN1 */
1079*4882a593Smuzhiyun 		"CD",		/* AIN2 */
1080*4882a593Smuzhiyun 		"Phono",	/* AIN3 */
1081*4882a593Smuzhiyun 		"Line",		/* AIN4 */
1082*4882a593Smuzhiyun 		"Aux2",		/* AIN5 */
1083*4882a593Smuzhiyun 		"Mic",		/* AIN6 */
1084*4882a593Smuzhiyun 		"Aux3",		/* AIN7 */
1085*4882a593Smuzhiyun 		"AC97"		/* AIN8 */
1086*4882a593Smuzhiyun 	};
1087*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun 	if (ice->eeprom.subvendor == VT1724_SUBDEVICE_AUREON71_UNIVERSE)
1090*4882a593Smuzhiyun 		return snd_ctl_enum_info(uinfo, 2, 8, universe_texts);
1091*4882a593Smuzhiyun 	else
1092*4882a593Smuzhiyun 		return snd_ctl_enum_info(uinfo, 2, 5, texts);
1093*4882a593Smuzhiyun }
1094*4882a593Smuzhiyun 
wm_adc_mux_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1095*4882a593Smuzhiyun static int wm_adc_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1096*4882a593Smuzhiyun {
1097*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1098*4882a593Smuzhiyun 	unsigned short val;
1099*4882a593Smuzhiyun 
1100*4882a593Smuzhiyun 	mutex_lock(&ice->gpio_mutex);
1101*4882a593Smuzhiyun 	val = wm_get(ice, WM_ADC_MUX);
1102*4882a593Smuzhiyun 	ucontrol->value.enumerated.item[0] = val & 7;
1103*4882a593Smuzhiyun 	ucontrol->value.enumerated.item[1] = (val >> 4) & 7;
1104*4882a593Smuzhiyun 	mutex_unlock(&ice->gpio_mutex);
1105*4882a593Smuzhiyun 	return 0;
1106*4882a593Smuzhiyun }
1107*4882a593Smuzhiyun 
wm_adc_mux_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1108*4882a593Smuzhiyun static int wm_adc_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1109*4882a593Smuzhiyun {
1110*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1111*4882a593Smuzhiyun 	unsigned short oval, nval;
1112*4882a593Smuzhiyun 	int change;
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
1115*4882a593Smuzhiyun 	oval = wm_get(ice, WM_ADC_MUX);
1116*4882a593Smuzhiyun 	nval = oval & ~0x77;
1117*4882a593Smuzhiyun 	nval |= ucontrol->value.enumerated.item[0] & 7;
1118*4882a593Smuzhiyun 	nval |= (ucontrol->value.enumerated.item[1] & 7) << 4;
1119*4882a593Smuzhiyun 	change = (oval != nval);
1120*4882a593Smuzhiyun 	if (change)
1121*4882a593Smuzhiyun 		wm_put(ice, WM_ADC_MUX, nval);
1122*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
1123*4882a593Smuzhiyun 	return change;
1124*4882a593Smuzhiyun }
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun /*
1127*4882a593Smuzhiyun  * CS8415 Input mux
1128*4882a593Smuzhiyun  */
aureon_cs8415_mux_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1129*4882a593Smuzhiyun static int aureon_cs8415_mux_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1130*4882a593Smuzhiyun {
1131*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1132*4882a593Smuzhiyun 	static const char * const aureon_texts[] = {
1133*4882a593Smuzhiyun 		"CD",		/* RXP0 */
1134*4882a593Smuzhiyun 		"Optical"	/* RXP1 */
1135*4882a593Smuzhiyun 	};
1136*4882a593Smuzhiyun 	static const char * const prodigy_texts[] = {
1137*4882a593Smuzhiyun 		"CD",
1138*4882a593Smuzhiyun 		"Coax"
1139*4882a593Smuzhiyun 	};
1140*4882a593Smuzhiyun 	if (ice->eeprom.subvendor == VT1724_SUBDEVICE_PRODIGY71)
1141*4882a593Smuzhiyun 		return snd_ctl_enum_info(uinfo, 1, 2, prodigy_texts);
1142*4882a593Smuzhiyun 	else
1143*4882a593Smuzhiyun 		return snd_ctl_enum_info(uinfo, 1, 2, aureon_texts);
1144*4882a593Smuzhiyun }
1145*4882a593Smuzhiyun 
aureon_cs8415_mux_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1146*4882a593Smuzhiyun static int aureon_cs8415_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1147*4882a593Smuzhiyun {
1148*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1149*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
1150*4882a593Smuzhiyun 
1151*4882a593Smuzhiyun 	/* snd_ice1712_save_gpio_status(ice); */
1152*4882a593Smuzhiyun 	/* val = aureon_cs8415_get(ice, CS8415_CTRL2); */
1153*4882a593Smuzhiyun 	ucontrol->value.enumerated.item[0] = spec->cs8415_mux;
1154*4882a593Smuzhiyun 	/* snd_ice1712_restore_gpio_status(ice); */
1155*4882a593Smuzhiyun 	return 0;
1156*4882a593Smuzhiyun }
1157*4882a593Smuzhiyun 
aureon_cs8415_mux_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1158*4882a593Smuzhiyun static int aureon_cs8415_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1159*4882a593Smuzhiyun {
1160*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1161*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
1162*4882a593Smuzhiyun 	unsigned short oval, nval;
1163*4882a593Smuzhiyun 	int change;
1164*4882a593Smuzhiyun 
1165*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
1166*4882a593Smuzhiyun 	oval = aureon_cs8415_get(ice, CS8415_CTRL2);
1167*4882a593Smuzhiyun 	nval = oval & ~0x07;
1168*4882a593Smuzhiyun 	nval |= ucontrol->value.enumerated.item[0] & 7;
1169*4882a593Smuzhiyun 	change = (oval != nval);
1170*4882a593Smuzhiyun 	if (change)
1171*4882a593Smuzhiyun 		aureon_cs8415_put(ice, CS8415_CTRL2, nval);
1172*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
1173*4882a593Smuzhiyun 	spec->cs8415_mux = ucontrol->value.enumerated.item[0];
1174*4882a593Smuzhiyun 	return change;
1175*4882a593Smuzhiyun }
1176*4882a593Smuzhiyun 
aureon_cs8415_rate_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1177*4882a593Smuzhiyun static int aureon_cs8415_rate_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1178*4882a593Smuzhiyun {
1179*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1180*4882a593Smuzhiyun 	uinfo->count = 1;
1181*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
1182*4882a593Smuzhiyun 	uinfo->value.integer.max = 192000;
1183*4882a593Smuzhiyun 	return 0;
1184*4882a593Smuzhiyun }
1185*4882a593Smuzhiyun 
aureon_cs8415_rate_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1186*4882a593Smuzhiyun static int aureon_cs8415_rate_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1187*4882a593Smuzhiyun {
1188*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1189*4882a593Smuzhiyun 	unsigned char ratio;
1190*4882a593Smuzhiyun 	ratio = aureon_cs8415_get(ice, CS8415_RATIO);
1191*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (int)((unsigned int)ratio * 750);
1192*4882a593Smuzhiyun 	return 0;
1193*4882a593Smuzhiyun }
1194*4882a593Smuzhiyun 
1195*4882a593Smuzhiyun /*
1196*4882a593Smuzhiyun  * CS8415A Mute
1197*4882a593Smuzhiyun  */
1198*4882a593Smuzhiyun #define aureon_cs8415_mute_info		snd_ctl_boolean_mono_info
1199*4882a593Smuzhiyun 
aureon_cs8415_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1200*4882a593Smuzhiyun static int aureon_cs8415_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1201*4882a593Smuzhiyun {
1202*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1203*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
1204*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (aureon_cs8415_get(ice, CS8415_CTRL1) & 0x20) ? 0 : 1;
1205*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
1206*4882a593Smuzhiyun 	return 0;
1207*4882a593Smuzhiyun }
1208*4882a593Smuzhiyun 
aureon_cs8415_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1209*4882a593Smuzhiyun static int aureon_cs8415_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1210*4882a593Smuzhiyun {
1211*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1212*4882a593Smuzhiyun 	unsigned char oval, nval;
1213*4882a593Smuzhiyun 	int change;
1214*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
1215*4882a593Smuzhiyun 	oval = aureon_cs8415_get(ice, CS8415_CTRL1);
1216*4882a593Smuzhiyun 	if (ucontrol->value.integer.value[0])
1217*4882a593Smuzhiyun 		nval = oval & ~0x20;
1218*4882a593Smuzhiyun 	else
1219*4882a593Smuzhiyun 		nval = oval | 0x20;
1220*4882a593Smuzhiyun 	change = (oval != nval);
1221*4882a593Smuzhiyun 	if (change)
1222*4882a593Smuzhiyun 		aureon_cs8415_put(ice, CS8415_CTRL1, nval);
1223*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
1224*4882a593Smuzhiyun 	return change;
1225*4882a593Smuzhiyun }
1226*4882a593Smuzhiyun 
1227*4882a593Smuzhiyun /*
1228*4882a593Smuzhiyun  * CS8415A Q-Sub info
1229*4882a593Smuzhiyun  */
aureon_cs8415_qsub_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1230*4882a593Smuzhiyun static int aureon_cs8415_qsub_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1231*4882a593Smuzhiyun {
1232*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1233*4882a593Smuzhiyun 	uinfo->count = 10;
1234*4882a593Smuzhiyun 	return 0;
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun 
aureon_cs8415_qsub_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1237*4882a593Smuzhiyun static int aureon_cs8415_qsub_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1238*4882a593Smuzhiyun {
1239*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1240*4882a593Smuzhiyun 
1241*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
1242*4882a593Smuzhiyun 	aureon_cs8415_read(ice, CS8415_QSUB, ucontrol->value.bytes.data, 10);
1243*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
1244*4882a593Smuzhiyun 
1245*4882a593Smuzhiyun 	return 0;
1246*4882a593Smuzhiyun }
1247*4882a593Smuzhiyun 
aureon_cs8415_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1248*4882a593Smuzhiyun static int aureon_cs8415_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1249*4882a593Smuzhiyun {
1250*4882a593Smuzhiyun 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1251*4882a593Smuzhiyun 	uinfo->count = 1;
1252*4882a593Smuzhiyun 	return 0;
1253*4882a593Smuzhiyun }
1254*4882a593Smuzhiyun 
aureon_cs8415_mask_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1255*4882a593Smuzhiyun static int aureon_cs8415_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1256*4882a593Smuzhiyun {
1257*4882a593Smuzhiyun 	memset(ucontrol->value.iec958.status, 0xFF, 24);
1258*4882a593Smuzhiyun 	return 0;
1259*4882a593Smuzhiyun }
1260*4882a593Smuzhiyun 
aureon_cs8415_spdif_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1261*4882a593Smuzhiyun static int aureon_cs8415_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1262*4882a593Smuzhiyun {
1263*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1264*4882a593Smuzhiyun 
1265*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
1266*4882a593Smuzhiyun 	aureon_cs8415_read(ice, CS8415_C_BUFFER, ucontrol->value.iec958.status, 24);
1267*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
1268*4882a593Smuzhiyun 	return 0;
1269*4882a593Smuzhiyun }
1270*4882a593Smuzhiyun 
1271*4882a593Smuzhiyun /*
1272*4882a593Smuzhiyun  * Headphone Amplifier
1273*4882a593Smuzhiyun  */
aureon_set_headphone_amp(struct snd_ice1712 * ice,int enable)1274*4882a593Smuzhiyun static int aureon_set_headphone_amp(struct snd_ice1712 *ice, int enable)
1275*4882a593Smuzhiyun {
1276*4882a593Smuzhiyun 	unsigned int tmp, tmp2;
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 	tmp2 = tmp = snd_ice1712_gpio_read(ice);
1279*4882a593Smuzhiyun 	if (enable)
1280*4882a593Smuzhiyun 		if (ice->eeprom.subvendor != VT1724_SUBDEVICE_PRODIGY71LT &&
1281*4882a593Smuzhiyun 		    ice->eeprom.subvendor != VT1724_SUBDEVICE_PRODIGY71XT)
1282*4882a593Smuzhiyun 			tmp |= AUREON_HP_SEL;
1283*4882a593Smuzhiyun 		else
1284*4882a593Smuzhiyun 			tmp |= PRODIGY_HP_SEL;
1285*4882a593Smuzhiyun 	else
1286*4882a593Smuzhiyun 		if (ice->eeprom.subvendor != VT1724_SUBDEVICE_PRODIGY71LT &&
1287*4882a593Smuzhiyun 		    ice->eeprom.subvendor != VT1724_SUBDEVICE_PRODIGY71XT)
1288*4882a593Smuzhiyun 			tmp &= ~AUREON_HP_SEL;
1289*4882a593Smuzhiyun 		else
1290*4882a593Smuzhiyun 			tmp &= ~PRODIGY_HP_SEL;
1291*4882a593Smuzhiyun 	if (tmp != tmp2) {
1292*4882a593Smuzhiyun 		snd_ice1712_gpio_write(ice, tmp);
1293*4882a593Smuzhiyun 		return 1;
1294*4882a593Smuzhiyun 	}
1295*4882a593Smuzhiyun 	return 0;
1296*4882a593Smuzhiyun }
1297*4882a593Smuzhiyun 
aureon_get_headphone_amp(struct snd_ice1712 * ice)1298*4882a593Smuzhiyun static int aureon_get_headphone_amp(struct snd_ice1712 *ice)
1299*4882a593Smuzhiyun {
1300*4882a593Smuzhiyun 	unsigned int tmp = snd_ice1712_gpio_read(ice);
1301*4882a593Smuzhiyun 
1302*4882a593Smuzhiyun 	return (tmp & AUREON_HP_SEL) != 0;
1303*4882a593Smuzhiyun }
1304*4882a593Smuzhiyun 
1305*4882a593Smuzhiyun #define aureon_hpamp_info	snd_ctl_boolean_mono_info
1306*4882a593Smuzhiyun 
aureon_hpamp_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1307*4882a593Smuzhiyun static int aureon_hpamp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1308*4882a593Smuzhiyun {
1309*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1310*4882a593Smuzhiyun 
1311*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = aureon_get_headphone_amp(ice);
1312*4882a593Smuzhiyun 	return 0;
1313*4882a593Smuzhiyun }
1314*4882a593Smuzhiyun 
1315*4882a593Smuzhiyun 
aureon_hpamp_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1316*4882a593Smuzhiyun static int aureon_hpamp_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1317*4882a593Smuzhiyun {
1318*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1319*4882a593Smuzhiyun 
1320*4882a593Smuzhiyun 	return aureon_set_headphone_amp(ice, ucontrol->value.integer.value[0]);
1321*4882a593Smuzhiyun }
1322*4882a593Smuzhiyun 
1323*4882a593Smuzhiyun /*
1324*4882a593Smuzhiyun  * Deemphasis
1325*4882a593Smuzhiyun  */
1326*4882a593Smuzhiyun 
1327*4882a593Smuzhiyun #define aureon_deemp_info	snd_ctl_boolean_mono_info
1328*4882a593Smuzhiyun 
aureon_deemp_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1329*4882a593Smuzhiyun static int aureon_deemp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1330*4882a593Smuzhiyun {
1331*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1332*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL2) & 0xf) == 0xf;
1333*4882a593Smuzhiyun 	return 0;
1334*4882a593Smuzhiyun }
1335*4882a593Smuzhiyun 
aureon_deemp_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1336*4882a593Smuzhiyun static int aureon_deemp_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1337*4882a593Smuzhiyun {
1338*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1339*4882a593Smuzhiyun 	int temp, temp2;
1340*4882a593Smuzhiyun 	temp2 = temp = wm_get(ice, WM_DAC_CTRL2);
1341*4882a593Smuzhiyun 	if (ucontrol->value.integer.value[0])
1342*4882a593Smuzhiyun 		temp |= 0xf;
1343*4882a593Smuzhiyun 	else
1344*4882a593Smuzhiyun 		temp &= ~0xf;
1345*4882a593Smuzhiyun 	if (temp != temp2) {
1346*4882a593Smuzhiyun 		wm_put(ice, WM_DAC_CTRL2, temp);
1347*4882a593Smuzhiyun 		return 1;
1348*4882a593Smuzhiyun 	}
1349*4882a593Smuzhiyun 	return 0;
1350*4882a593Smuzhiyun }
1351*4882a593Smuzhiyun 
1352*4882a593Smuzhiyun /*
1353*4882a593Smuzhiyun  * ADC Oversampling
1354*4882a593Smuzhiyun  */
aureon_oversampling_info(struct snd_kcontrol * k,struct snd_ctl_elem_info * uinfo)1355*4882a593Smuzhiyun static int aureon_oversampling_info(struct snd_kcontrol *k, struct snd_ctl_elem_info *uinfo)
1356*4882a593Smuzhiyun {
1357*4882a593Smuzhiyun 	static const char * const texts[2] = { "128x", "64x"	};
1358*4882a593Smuzhiyun 
1359*4882a593Smuzhiyun 	return snd_ctl_enum_info(uinfo, 1, 2, texts);
1360*4882a593Smuzhiyun }
1361*4882a593Smuzhiyun 
aureon_oversampling_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1362*4882a593Smuzhiyun static int aureon_oversampling_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1363*4882a593Smuzhiyun {
1364*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1365*4882a593Smuzhiyun 	ucontrol->value.enumerated.item[0] = (wm_get(ice, WM_MASTER) & 0x8) == 0x8;
1366*4882a593Smuzhiyun 	return 0;
1367*4882a593Smuzhiyun }
1368*4882a593Smuzhiyun 
aureon_oversampling_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1369*4882a593Smuzhiyun static int aureon_oversampling_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1370*4882a593Smuzhiyun {
1371*4882a593Smuzhiyun 	int temp, temp2;
1372*4882a593Smuzhiyun 	struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1373*4882a593Smuzhiyun 
1374*4882a593Smuzhiyun 	temp2 = temp = wm_get(ice, WM_MASTER);
1375*4882a593Smuzhiyun 
1376*4882a593Smuzhiyun 	if (ucontrol->value.enumerated.item[0])
1377*4882a593Smuzhiyun 		temp |= 0x8;
1378*4882a593Smuzhiyun 	else
1379*4882a593Smuzhiyun 		temp &= ~0x8;
1380*4882a593Smuzhiyun 
1381*4882a593Smuzhiyun 	if (temp != temp2) {
1382*4882a593Smuzhiyun 		wm_put(ice, WM_MASTER, temp);
1383*4882a593Smuzhiyun 		return 1;
1384*4882a593Smuzhiyun 	}
1385*4882a593Smuzhiyun 	return 0;
1386*4882a593Smuzhiyun }
1387*4882a593Smuzhiyun 
1388*4882a593Smuzhiyun /*
1389*4882a593Smuzhiyun  * mixers
1390*4882a593Smuzhiyun  */
1391*4882a593Smuzhiyun 
1392*4882a593Smuzhiyun static const struct snd_kcontrol_new aureon_dac_controls[] = {
1393*4882a593Smuzhiyun 	{
1394*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1395*4882a593Smuzhiyun 		.name = "Master Playback Switch",
1396*4882a593Smuzhiyun 		.info = wm_master_mute_info,
1397*4882a593Smuzhiyun 		.get = wm_master_mute_get,
1398*4882a593Smuzhiyun 		.put = wm_master_mute_put
1399*4882a593Smuzhiyun 	},
1400*4882a593Smuzhiyun 	{
1401*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1402*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1403*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1404*4882a593Smuzhiyun 		.name = "Master Playback Volume",
1405*4882a593Smuzhiyun 		.info = wm_master_vol_info,
1406*4882a593Smuzhiyun 		.get = wm_master_vol_get,
1407*4882a593Smuzhiyun 		.put = wm_master_vol_put,
1408*4882a593Smuzhiyun 		.tlv = { .p = db_scale_wm_dac }
1409*4882a593Smuzhiyun 	},
1410*4882a593Smuzhiyun 	{
1411*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1412*4882a593Smuzhiyun 		.name = "Front Playback Switch",
1413*4882a593Smuzhiyun 		.info = wm_mute_info,
1414*4882a593Smuzhiyun 		.get = wm_mute_get,
1415*4882a593Smuzhiyun 		.put = wm_mute_put,
1416*4882a593Smuzhiyun 		.private_value = (2 << 8) | 0
1417*4882a593Smuzhiyun 	},
1418*4882a593Smuzhiyun 	{
1419*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1420*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1421*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1422*4882a593Smuzhiyun 		.name = "Front Playback Volume",
1423*4882a593Smuzhiyun 		.info = wm_vol_info,
1424*4882a593Smuzhiyun 		.get = wm_vol_get,
1425*4882a593Smuzhiyun 		.put = wm_vol_put,
1426*4882a593Smuzhiyun 		.private_value = (2 << 8) | 0,
1427*4882a593Smuzhiyun 		.tlv = { .p = db_scale_wm_dac }
1428*4882a593Smuzhiyun 	},
1429*4882a593Smuzhiyun 	{
1430*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1431*4882a593Smuzhiyun 		.name = "Rear Playback Switch",
1432*4882a593Smuzhiyun 		.info = wm_mute_info,
1433*4882a593Smuzhiyun 		.get = wm_mute_get,
1434*4882a593Smuzhiyun 		.put = wm_mute_put,
1435*4882a593Smuzhiyun 		.private_value = (2 << 8) | 2
1436*4882a593Smuzhiyun 	},
1437*4882a593Smuzhiyun 	{
1438*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1439*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1440*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1441*4882a593Smuzhiyun 		.name = "Rear Playback Volume",
1442*4882a593Smuzhiyun 		.info = wm_vol_info,
1443*4882a593Smuzhiyun 		.get = wm_vol_get,
1444*4882a593Smuzhiyun 		.put = wm_vol_put,
1445*4882a593Smuzhiyun 		.private_value = (2 << 8) | 2,
1446*4882a593Smuzhiyun 		.tlv = { .p = db_scale_wm_dac }
1447*4882a593Smuzhiyun 	},
1448*4882a593Smuzhiyun 	{
1449*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1450*4882a593Smuzhiyun 		.name = "Center Playback Switch",
1451*4882a593Smuzhiyun 		.info = wm_mute_info,
1452*4882a593Smuzhiyun 		.get = wm_mute_get,
1453*4882a593Smuzhiyun 		.put = wm_mute_put,
1454*4882a593Smuzhiyun 		.private_value = (1 << 8) | 4
1455*4882a593Smuzhiyun 	},
1456*4882a593Smuzhiyun 	{
1457*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1458*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1459*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1460*4882a593Smuzhiyun 		.name = "Center Playback Volume",
1461*4882a593Smuzhiyun 		.info = wm_vol_info,
1462*4882a593Smuzhiyun 		.get = wm_vol_get,
1463*4882a593Smuzhiyun 		.put = wm_vol_put,
1464*4882a593Smuzhiyun 		.private_value = (1 << 8) | 4,
1465*4882a593Smuzhiyun 		.tlv = { .p = db_scale_wm_dac }
1466*4882a593Smuzhiyun 	},
1467*4882a593Smuzhiyun 	{
1468*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1469*4882a593Smuzhiyun 		.name = "LFE Playback Switch",
1470*4882a593Smuzhiyun 		.info = wm_mute_info,
1471*4882a593Smuzhiyun 		.get = wm_mute_get,
1472*4882a593Smuzhiyun 		.put = wm_mute_put,
1473*4882a593Smuzhiyun 		.private_value = (1 << 8) | 5
1474*4882a593Smuzhiyun 	},
1475*4882a593Smuzhiyun 	{
1476*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1477*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1478*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1479*4882a593Smuzhiyun 		.name = "LFE Playback Volume",
1480*4882a593Smuzhiyun 		.info = wm_vol_info,
1481*4882a593Smuzhiyun 		.get = wm_vol_get,
1482*4882a593Smuzhiyun 		.put = wm_vol_put,
1483*4882a593Smuzhiyun 		.private_value = (1 << 8) | 5,
1484*4882a593Smuzhiyun 		.tlv = { .p = db_scale_wm_dac }
1485*4882a593Smuzhiyun 	},
1486*4882a593Smuzhiyun 	{
1487*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1488*4882a593Smuzhiyun 		.name = "Side Playback Switch",
1489*4882a593Smuzhiyun 		.info = wm_mute_info,
1490*4882a593Smuzhiyun 		.get = wm_mute_get,
1491*4882a593Smuzhiyun 		.put = wm_mute_put,
1492*4882a593Smuzhiyun 		.private_value = (2 << 8) | 6
1493*4882a593Smuzhiyun 	},
1494*4882a593Smuzhiyun 	{
1495*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1496*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1497*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1498*4882a593Smuzhiyun 		.name = "Side Playback Volume",
1499*4882a593Smuzhiyun 		.info = wm_vol_info,
1500*4882a593Smuzhiyun 		.get = wm_vol_get,
1501*4882a593Smuzhiyun 		.put = wm_vol_put,
1502*4882a593Smuzhiyun 		.private_value = (2 << 8) | 6,
1503*4882a593Smuzhiyun 		.tlv = { .p = db_scale_wm_dac }
1504*4882a593Smuzhiyun 	}
1505*4882a593Smuzhiyun };
1506*4882a593Smuzhiyun 
1507*4882a593Smuzhiyun static const struct snd_kcontrol_new wm_controls[] = {
1508*4882a593Smuzhiyun 	{
1509*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1510*4882a593Smuzhiyun 		.name = "PCM Playback Switch",
1511*4882a593Smuzhiyun 		.info = wm_pcm_mute_info,
1512*4882a593Smuzhiyun 		.get = wm_pcm_mute_get,
1513*4882a593Smuzhiyun 		.put = wm_pcm_mute_put
1514*4882a593Smuzhiyun 	},
1515*4882a593Smuzhiyun 	{
1516*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1517*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1518*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1519*4882a593Smuzhiyun 		.name = "PCM Playback Volume",
1520*4882a593Smuzhiyun 		.info = wm_pcm_vol_info,
1521*4882a593Smuzhiyun 		.get = wm_pcm_vol_get,
1522*4882a593Smuzhiyun 		.put = wm_pcm_vol_put,
1523*4882a593Smuzhiyun 		.tlv = { .p = db_scale_wm_pcm }
1524*4882a593Smuzhiyun 	},
1525*4882a593Smuzhiyun 	{
1526*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1527*4882a593Smuzhiyun 		.name = "Capture Switch",
1528*4882a593Smuzhiyun 		.info = wm_adc_mute_info,
1529*4882a593Smuzhiyun 		.get = wm_adc_mute_get,
1530*4882a593Smuzhiyun 		.put = wm_adc_mute_put,
1531*4882a593Smuzhiyun 	},
1532*4882a593Smuzhiyun 	{
1533*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1534*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1535*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1536*4882a593Smuzhiyun 		.name = "Capture Volume",
1537*4882a593Smuzhiyun 		.info = wm_adc_vol_info,
1538*4882a593Smuzhiyun 		.get = wm_adc_vol_get,
1539*4882a593Smuzhiyun 		.put = wm_adc_vol_put,
1540*4882a593Smuzhiyun 		.tlv = { .p = db_scale_wm_adc }
1541*4882a593Smuzhiyun 	},
1542*4882a593Smuzhiyun 	{
1543*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1544*4882a593Smuzhiyun 		.name = "Capture Source",
1545*4882a593Smuzhiyun 		.info = wm_adc_mux_info,
1546*4882a593Smuzhiyun 		.get = wm_adc_mux_get,
1547*4882a593Smuzhiyun 		.put = wm_adc_mux_put,
1548*4882a593Smuzhiyun 		.private_value = 5
1549*4882a593Smuzhiyun 	},
1550*4882a593Smuzhiyun 	{
1551*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1552*4882a593Smuzhiyun 		.name = "External Amplifier",
1553*4882a593Smuzhiyun 		.info = aureon_hpamp_info,
1554*4882a593Smuzhiyun 		.get = aureon_hpamp_get,
1555*4882a593Smuzhiyun 		.put = aureon_hpamp_put
1556*4882a593Smuzhiyun 	},
1557*4882a593Smuzhiyun 	{
1558*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1559*4882a593Smuzhiyun 		.name = "DAC Deemphasis Switch",
1560*4882a593Smuzhiyun 		.info = aureon_deemp_info,
1561*4882a593Smuzhiyun 		.get = aureon_deemp_get,
1562*4882a593Smuzhiyun 		.put = aureon_deemp_put
1563*4882a593Smuzhiyun 	},
1564*4882a593Smuzhiyun 	{
1565*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1566*4882a593Smuzhiyun 		.name = "ADC Oversampling",
1567*4882a593Smuzhiyun 		.info = aureon_oversampling_info,
1568*4882a593Smuzhiyun 		.get = aureon_oversampling_get,
1569*4882a593Smuzhiyun 		.put = aureon_oversampling_put
1570*4882a593Smuzhiyun 	}
1571*4882a593Smuzhiyun };
1572*4882a593Smuzhiyun 
1573*4882a593Smuzhiyun static const struct snd_kcontrol_new ac97_controls[] = {
1574*4882a593Smuzhiyun 	{
1575*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1576*4882a593Smuzhiyun 		.name = "AC97 Playback Switch",
1577*4882a593Smuzhiyun 		.info = aureon_ac97_mmute_info,
1578*4882a593Smuzhiyun 		.get = aureon_ac97_mmute_get,
1579*4882a593Smuzhiyun 		.put = aureon_ac97_mmute_put,
1580*4882a593Smuzhiyun 		.private_value = AC97_MASTER
1581*4882a593Smuzhiyun 	},
1582*4882a593Smuzhiyun 	{
1583*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1584*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1585*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1586*4882a593Smuzhiyun 		.name = "AC97 Playback Volume",
1587*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1588*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1589*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1590*4882a593Smuzhiyun 		.private_value = AC97_MASTER|AUREON_AC97_STEREO,
1591*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_master }
1592*4882a593Smuzhiyun 	},
1593*4882a593Smuzhiyun 	{
1594*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1595*4882a593Smuzhiyun 		.name = "CD Playback Switch",
1596*4882a593Smuzhiyun 		.info = aureon_ac97_mute_info,
1597*4882a593Smuzhiyun 		.get = aureon_ac97_mute_get,
1598*4882a593Smuzhiyun 		.put = aureon_ac97_mute_put,
1599*4882a593Smuzhiyun 		.private_value = AC97_CD
1600*4882a593Smuzhiyun 	},
1601*4882a593Smuzhiyun 	{
1602*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1603*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1604*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1605*4882a593Smuzhiyun 		.name = "CD Playback Volume",
1606*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1607*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1608*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1609*4882a593Smuzhiyun 		.private_value = AC97_CD|AUREON_AC97_STEREO,
1610*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_gain }
1611*4882a593Smuzhiyun 	},
1612*4882a593Smuzhiyun 	{
1613*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1614*4882a593Smuzhiyun 		.name = "Aux Playback Switch",
1615*4882a593Smuzhiyun 		.info = aureon_ac97_mute_info,
1616*4882a593Smuzhiyun 		.get = aureon_ac97_mute_get,
1617*4882a593Smuzhiyun 		.put = aureon_ac97_mute_put,
1618*4882a593Smuzhiyun 		.private_value = AC97_AUX,
1619*4882a593Smuzhiyun 	},
1620*4882a593Smuzhiyun 	{
1621*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1622*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1623*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1624*4882a593Smuzhiyun 		.name = "Aux Playback Volume",
1625*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1626*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1627*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1628*4882a593Smuzhiyun 		.private_value = AC97_AUX|AUREON_AC97_STEREO,
1629*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_gain }
1630*4882a593Smuzhiyun 	},
1631*4882a593Smuzhiyun 	{
1632*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1633*4882a593Smuzhiyun 		.name = "Line Playback Switch",
1634*4882a593Smuzhiyun 		.info = aureon_ac97_mute_info,
1635*4882a593Smuzhiyun 		.get = aureon_ac97_mute_get,
1636*4882a593Smuzhiyun 		.put = aureon_ac97_mute_put,
1637*4882a593Smuzhiyun 		.private_value = AC97_LINE
1638*4882a593Smuzhiyun 	},
1639*4882a593Smuzhiyun 	{
1640*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1641*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1642*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1643*4882a593Smuzhiyun 		.name = "Line Playback Volume",
1644*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1645*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1646*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1647*4882a593Smuzhiyun 		.private_value = AC97_LINE|AUREON_AC97_STEREO,
1648*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_gain }
1649*4882a593Smuzhiyun 	},
1650*4882a593Smuzhiyun 	{
1651*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1652*4882a593Smuzhiyun 		.name = "Mic Playback Switch",
1653*4882a593Smuzhiyun 		.info = aureon_ac97_mute_info,
1654*4882a593Smuzhiyun 		.get = aureon_ac97_mute_get,
1655*4882a593Smuzhiyun 		.put = aureon_ac97_mute_put,
1656*4882a593Smuzhiyun 		.private_value = AC97_MIC
1657*4882a593Smuzhiyun 	},
1658*4882a593Smuzhiyun 	{
1659*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1660*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1661*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1662*4882a593Smuzhiyun 		.name = "Mic Playback Volume",
1663*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1664*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1665*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1666*4882a593Smuzhiyun 		.private_value = AC97_MIC,
1667*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_gain }
1668*4882a593Smuzhiyun 	},
1669*4882a593Smuzhiyun 	{
1670*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1671*4882a593Smuzhiyun 		.name = "Mic Boost (+20dB)",
1672*4882a593Smuzhiyun 		.info = aureon_ac97_micboost_info,
1673*4882a593Smuzhiyun 		.get = aureon_ac97_micboost_get,
1674*4882a593Smuzhiyun 		.put = aureon_ac97_micboost_put
1675*4882a593Smuzhiyun 	}
1676*4882a593Smuzhiyun };
1677*4882a593Smuzhiyun 
1678*4882a593Smuzhiyun static const struct snd_kcontrol_new universe_ac97_controls[] = {
1679*4882a593Smuzhiyun 	{
1680*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1681*4882a593Smuzhiyun 		.name = "AC97 Playback Switch",
1682*4882a593Smuzhiyun 		.info = aureon_ac97_mmute_info,
1683*4882a593Smuzhiyun 		.get = aureon_ac97_mmute_get,
1684*4882a593Smuzhiyun 		.put = aureon_ac97_mmute_put,
1685*4882a593Smuzhiyun 		.private_value = AC97_MASTER
1686*4882a593Smuzhiyun 	},
1687*4882a593Smuzhiyun 	{
1688*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1689*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1690*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1691*4882a593Smuzhiyun 		.name = "AC97 Playback Volume",
1692*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1693*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1694*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1695*4882a593Smuzhiyun 		.private_value = AC97_MASTER|AUREON_AC97_STEREO,
1696*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_master }
1697*4882a593Smuzhiyun 	},
1698*4882a593Smuzhiyun 	{
1699*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1700*4882a593Smuzhiyun 		.name = "CD Playback Switch",
1701*4882a593Smuzhiyun 		.info = aureon_ac97_mute_info,
1702*4882a593Smuzhiyun 		.get = aureon_ac97_mute_get,
1703*4882a593Smuzhiyun 		.put = aureon_ac97_mute_put,
1704*4882a593Smuzhiyun 		.private_value = AC97_AUX
1705*4882a593Smuzhiyun 	},
1706*4882a593Smuzhiyun 	{
1707*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1708*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1709*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1710*4882a593Smuzhiyun 		.name = "CD Playback Volume",
1711*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1712*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1713*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1714*4882a593Smuzhiyun 		.private_value = AC97_AUX|AUREON_AC97_STEREO,
1715*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_gain }
1716*4882a593Smuzhiyun 	},
1717*4882a593Smuzhiyun 	{
1718*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1719*4882a593Smuzhiyun 		.name = "Phono Playback Switch",
1720*4882a593Smuzhiyun 		.info = aureon_ac97_mute_info,
1721*4882a593Smuzhiyun 		.get = aureon_ac97_mute_get,
1722*4882a593Smuzhiyun 		.put = aureon_ac97_mute_put,
1723*4882a593Smuzhiyun 		.private_value = AC97_CD
1724*4882a593Smuzhiyun 	},
1725*4882a593Smuzhiyun 	{
1726*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1727*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1728*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1729*4882a593Smuzhiyun 		.name = "Phono Playback Volume",
1730*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1731*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1732*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1733*4882a593Smuzhiyun 		.private_value = AC97_CD|AUREON_AC97_STEREO,
1734*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_gain }
1735*4882a593Smuzhiyun 	},
1736*4882a593Smuzhiyun 	{
1737*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1738*4882a593Smuzhiyun 		.name = "Line Playback Switch",
1739*4882a593Smuzhiyun 		.info = aureon_ac97_mute_info,
1740*4882a593Smuzhiyun 		.get = aureon_ac97_mute_get,
1741*4882a593Smuzhiyun 		.put = aureon_ac97_mute_put,
1742*4882a593Smuzhiyun 		.private_value = AC97_LINE
1743*4882a593Smuzhiyun 	},
1744*4882a593Smuzhiyun 	{
1745*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1746*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1747*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1748*4882a593Smuzhiyun 		.name = "Line Playback Volume",
1749*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1750*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1751*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1752*4882a593Smuzhiyun 		.private_value = AC97_LINE|AUREON_AC97_STEREO,
1753*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_gain }
1754*4882a593Smuzhiyun 	},
1755*4882a593Smuzhiyun 	{
1756*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1757*4882a593Smuzhiyun 		.name = "Mic Playback Switch",
1758*4882a593Smuzhiyun 		.info = aureon_ac97_mute_info,
1759*4882a593Smuzhiyun 		.get = aureon_ac97_mute_get,
1760*4882a593Smuzhiyun 		.put = aureon_ac97_mute_put,
1761*4882a593Smuzhiyun 		.private_value = AC97_MIC
1762*4882a593Smuzhiyun 	},
1763*4882a593Smuzhiyun 	{
1764*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1765*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1766*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1767*4882a593Smuzhiyun 		.name = "Mic Playback Volume",
1768*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1769*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1770*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1771*4882a593Smuzhiyun 		.private_value = AC97_MIC,
1772*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_gain }
1773*4882a593Smuzhiyun 	},
1774*4882a593Smuzhiyun 	{
1775*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1776*4882a593Smuzhiyun 		.name = "Mic Boost (+20dB)",
1777*4882a593Smuzhiyun 		.info = aureon_ac97_micboost_info,
1778*4882a593Smuzhiyun 		.get = aureon_ac97_micboost_get,
1779*4882a593Smuzhiyun 		.put = aureon_ac97_micboost_put
1780*4882a593Smuzhiyun 	},
1781*4882a593Smuzhiyun 	{
1782*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1783*4882a593Smuzhiyun 		.name = "Aux Playback Switch",
1784*4882a593Smuzhiyun 		.info = aureon_ac97_mute_info,
1785*4882a593Smuzhiyun 		.get = aureon_ac97_mute_get,
1786*4882a593Smuzhiyun 		.put = aureon_ac97_mute_put,
1787*4882a593Smuzhiyun 		.private_value = AC97_VIDEO,
1788*4882a593Smuzhiyun 	},
1789*4882a593Smuzhiyun 	{
1790*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1791*4882a593Smuzhiyun 		.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1792*4882a593Smuzhiyun 				SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1793*4882a593Smuzhiyun 		.name = "Aux Playback Volume",
1794*4882a593Smuzhiyun 		.info = aureon_ac97_vol_info,
1795*4882a593Smuzhiyun 		.get = aureon_ac97_vol_get,
1796*4882a593Smuzhiyun 		.put = aureon_ac97_vol_put,
1797*4882a593Smuzhiyun 		.private_value = AC97_VIDEO|AUREON_AC97_STEREO,
1798*4882a593Smuzhiyun 		.tlv = { .p = db_scale_ac97_gain }
1799*4882a593Smuzhiyun 	},
1800*4882a593Smuzhiyun 	{
1801*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1802*4882a593Smuzhiyun 		.name = "Aux Source",
1803*4882a593Smuzhiyun 		.info = aureon_universe_inmux_info,
1804*4882a593Smuzhiyun 		.get = aureon_universe_inmux_get,
1805*4882a593Smuzhiyun 		.put = aureon_universe_inmux_put
1806*4882a593Smuzhiyun 	}
1807*4882a593Smuzhiyun 
1808*4882a593Smuzhiyun };
1809*4882a593Smuzhiyun 
1810*4882a593Smuzhiyun static const struct snd_kcontrol_new cs8415_controls[] = {
1811*4882a593Smuzhiyun 	{
1812*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1813*4882a593Smuzhiyun 		.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, SWITCH),
1814*4882a593Smuzhiyun 		.info = aureon_cs8415_mute_info,
1815*4882a593Smuzhiyun 		.get = aureon_cs8415_mute_get,
1816*4882a593Smuzhiyun 		.put = aureon_cs8415_mute_put
1817*4882a593Smuzhiyun 	},
1818*4882a593Smuzhiyun 	{
1819*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1820*4882a593Smuzhiyun 		.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Source",
1821*4882a593Smuzhiyun 		.info = aureon_cs8415_mux_info,
1822*4882a593Smuzhiyun 		.get = aureon_cs8415_mux_get,
1823*4882a593Smuzhiyun 		.put = aureon_cs8415_mux_put,
1824*4882a593Smuzhiyun 	},
1825*4882a593Smuzhiyun 	{
1826*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1827*4882a593Smuzhiyun 		.name = SNDRV_CTL_NAME_IEC958("Q-subcode ", CAPTURE, DEFAULT),
1828*4882a593Smuzhiyun 		.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1829*4882a593Smuzhiyun 		.info = aureon_cs8415_qsub_info,
1830*4882a593Smuzhiyun 		.get = aureon_cs8415_qsub_get,
1831*4882a593Smuzhiyun 	},
1832*4882a593Smuzhiyun 	{
1833*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1834*4882a593Smuzhiyun 		.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK),
1835*4882a593Smuzhiyun 		.access = SNDRV_CTL_ELEM_ACCESS_READ,
1836*4882a593Smuzhiyun 		.info = aureon_cs8415_spdif_info,
1837*4882a593Smuzhiyun 		.get = aureon_cs8415_mask_get
1838*4882a593Smuzhiyun 	},
1839*4882a593Smuzhiyun 	{
1840*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1841*4882a593Smuzhiyun 		.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
1842*4882a593Smuzhiyun 		.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1843*4882a593Smuzhiyun 		.info = aureon_cs8415_spdif_info,
1844*4882a593Smuzhiyun 		.get = aureon_cs8415_spdif_get
1845*4882a593Smuzhiyun 	},
1846*4882a593Smuzhiyun 	{
1847*4882a593Smuzhiyun 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1848*4882a593Smuzhiyun 		.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Rate",
1849*4882a593Smuzhiyun 		.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1850*4882a593Smuzhiyun 		.info = aureon_cs8415_rate_info,
1851*4882a593Smuzhiyun 		.get = aureon_cs8415_rate_get
1852*4882a593Smuzhiyun 	}
1853*4882a593Smuzhiyun };
1854*4882a593Smuzhiyun 
aureon_add_controls(struct snd_ice1712 * ice)1855*4882a593Smuzhiyun static int aureon_add_controls(struct snd_ice1712 *ice)
1856*4882a593Smuzhiyun {
1857*4882a593Smuzhiyun 	unsigned int i, counts;
1858*4882a593Smuzhiyun 	int err;
1859*4882a593Smuzhiyun 
1860*4882a593Smuzhiyun 	counts = ARRAY_SIZE(aureon_dac_controls);
1861*4882a593Smuzhiyun 	if (ice->eeprom.subvendor == VT1724_SUBDEVICE_AUREON51_SKY)
1862*4882a593Smuzhiyun 		counts -= 2; /* no side */
1863*4882a593Smuzhiyun 	for (i = 0; i < counts; i++) {
1864*4882a593Smuzhiyun 		err = snd_ctl_add(ice->card, snd_ctl_new1(&aureon_dac_controls[i], ice));
1865*4882a593Smuzhiyun 		if (err < 0)
1866*4882a593Smuzhiyun 			return err;
1867*4882a593Smuzhiyun 	}
1868*4882a593Smuzhiyun 
1869*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(wm_controls); i++) {
1870*4882a593Smuzhiyun 		err = snd_ctl_add(ice->card, snd_ctl_new1(&wm_controls[i], ice));
1871*4882a593Smuzhiyun 		if (err < 0)
1872*4882a593Smuzhiyun 			return err;
1873*4882a593Smuzhiyun 	}
1874*4882a593Smuzhiyun 
1875*4882a593Smuzhiyun 	if (ice->eeprom.subvendor == VT1724_SUBDEVICE_AUREON71_UNIVERSE) {
1876*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(universe_ac97_controls); i++) {
1877*4882a593Smuzhiyun 			err = snd_ctl_add(ice->card, snd_ctl_new1(&universe_ac97_controls[i], ice));
1878*4882a593Smuzhiyun 			if (err < 0)
1879*4882a593Smuzhiyun 				return err;
1880*4882a593Smuzhiyun 		}
1881*4882a593Smuzhiyun 	} else if (ice->eeprom.subvendor != VT1724_SUBDEVICE_PRODIGY71LT &&
1882*4882a593Smuzhiyun 		 ice->eeprom.subvendor != VT1724_SUBDEVICE_PRODIGY71XT) {
1883*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(ac97_controls); i++) {
1884*4882a593Smuzhiyun 			err = snd_ctl_add(ice->card, snd_ctl_new1(&ac97_controls[i], ice));
1885*4882a593Smuzhiyun 			if (err < 0)
1886*4882a593Smuzhiyun 				return err;
1887*4882a593Smuzhiyun 		}
1888*4882a593Smuzhiyun 	}
1889*4882a593Smuzhiyun 
1890*4882a593Smuzhiyun 	if (ice->eeprom.subvendor != VT1724_SUBDEVICE_PRODIGY71LT &&
1891*4882a593Smuzhiyun 	    ice->eeprom.subvendor != VT1724_SUBDEVICE_PRODIGY71XT) {
1892*4882a593Smuzhiyun 		unsigned char id;
1893*4882a593Smuzhiyun 		snd_ice1712_save_gpio_status(ice);
1894*4882a593Smuzhiyun 		id = aureon_cs8415_get(ice, CS8415_ID);
1895*4882a593Smuzhiyun 		if (id != 0x41)
1896*4882a593Smuzhiyun 			dev_info(ice->card->dev,
1897*4882a593Smuzhiyun 				 "No CS8415 chip. Skipping CS8415 controls.\n");
1898*4882a593Smuzhiyun 		else if ((id & 0x0F) != 0x01)
1899*4882a593Smuzhiyun 			dev_info(ice->card->dev,
1900*4882a593Smuzhiyun 				 "Detected unsupported CS8415 rev. (%c)\n",
1901*4882a593Smuzhiyun 				 (char)((id & 0x0F) + 'A' - 1));
1902*4882a593Smuzhiyun 		else {
1903*4882a593Smuzhiyun 			for (i = 0; i < ARRAY_SIZE(cs8415_controls); i++) {
1904*4882a593Smuzhiyun 				struct snd_kcontrol *kctl;
1905*4882a593Smuzhiyun 				err = snd_ctl_add(ice->card, (kctl = snd_ctl_new1(&cs8415_controls[i], ice)));
1906*4882a593Smuzhiyun 				if (err < 0)
1907*4882a593Smuzhiyun 					return err;
1908*4882a593Smuzhiyun 				if (i > 1)
1909*4882a593Smuzhiyun 					kctl->id.device = ice->pcm->device;
1910*4882a593Smuzhiyun 			}
1911*4882a593Smuzhiyun 		}
1912*4882a593Smuzhiyun 		snd_ice1712_restore_gpio_status(ice);
1913*4882a593Smuzhiyun 	}
1914*4882a593Smuzhiyun 
1915*4882a593Smuzhiyun 	return 0;
1916*4882a593Smuzhiyun }
1917*4882a593Smuzhiyun 
1918*4882a593Smuzhiyun /*
1919*4882a593Smuzhiyun  * reset the chip
1920*4882a593Smuzhiyun  */
aureon_reset(struct snd_ice1712 * ice)1921*4882a593Smuzhiyun static int aureon_reset(struct snd_ice1712 *ice)
1922*4882a593Smuzhiyun {
1923*4882a593Smuzhiyun 	static const unsigned short wm_inits_aureon[] = {
1924*4882a593Smuzhiyun 		/* These come first to reduce init pop noise */
1925*4882a593Smuzhiyun 		0x1b, 0x044,		/* ADC Mux (AC'97 source) */
1926*4882a593Smuzhiyun 		0x1c, 0x00B,		/* Out Mux1 (VOUT1 = DAC+AUX, VOUT2 = DAC) */
1927*4882a593Smuzhiyun 		0x1d, 0x009,		/* Out Mux2 (VOUT2 = DAC, VOUT3 = DAC) */
1928*4882a593Smuzhiyun 
1929*4882a593Smuzhiyun 		0x18, 0x000,		/* All power-up */
1930*4882a593Smuzhiyun 
1931*4882a593Smuzhiyun 		0x16, 0x122,		/* I2S, normal polarity, 24bit */
1932*4882a593Smuzhiyun 		0x17, 0x022,		/* 256fs, slave mode */
1933*4882a593Smuzhiyun 		0x00, 0,		/* DAC1 analog mute */
1934*4882a593Smuzhiyun 		0x01, 0,		/* DAC2 analog mute */
1935*4882a593Smuzhiyun 		0x02, 0,		/* DAC3 analog mute */
1936*4882a593Smuzhiyun 		0x03, 0,		/* DAC4 analog mute */
1937*4882a593Smuzhiyun 		0x04, 0,		/* DAC5 analog mute */
1938*4882a593Smuzhiyun 		0x05, 0,		/* DAC6 analog mute */
1939*4882a593Smuzhiyun 		0x06, 0,		/* DAC7 analog mute */
1940*4882a593Smuzhiyun 		0x07, 0,		/* DAC8 analog mute */
1941*4882a593Smuzhiyun 		0x08, 0x100,		/* master analog mute */
1942*4882a593Smuzhiyun 		0x09, 0xff,		/* DAC1 digital full */
1943*4882a593Smuzhiyun 		0x0a, 0xff,		/* DAC2 digital full */
1944*4882a593Smuzhiyun 		0x0b, 0xff,		/* DAC3 digital full */
1945*4882a593Smuzhiyun 		0x0c, 0xff,		/* DAC4 digital full */
1946*4882a593Smuzhiyun 		0x0d, 0xff,		/* DAC5 digital full */
1947*4882a593Smuzhiyun 		0x0e, 0xff,		/* DAC6 digital full */
1948*4882a593Smuzhiyun 		0x0f, 0xff,		/* DAC7 digital full */
1949*4882a593Smuzhiyun 		0x10, 0xff,		/* DAC8 digital full */
1950*4882a593Smuzhiyun 		0x11, 0x1ff,		/* master digital full */
1951*4882a593Smuzhiyun 		0x12, 0x000,		/* phase normal */
1952*4882a593Smuzhiyun 		0x13, 0x090,		/* unmute DAC L/R */
1953*4882a593Smuzhiyun 		0x14, 0x000,		/* all unmute */
1954*4882a593Smuzhiyun 		0x15, 0x000,		/* no deemphasis, no ZFLG */
1955*4882a593Smuzhiyun 		0x19, 0x000,		/* -12dB ADC/L */
1956*4882a593Smuzhiyun 		0x1a, 0x000,		/* -12dB ADC/R */
1957*4882a593Smuzhiyun 		(unsigned short)-1
1958*4882a593Smuzhiyun 	};
1959*4882a593Smuzhiyun 	static const unsigned short wm_inits_prodigy[] = {
1960*4882a593Smuzhiyun 
1961*4882a593Smuzhiyun 		/* These come first to reduce init pop noise */
1962*4882a593Smuzhiyun 		0x1b, 0x000,		/* ADC Mux */
1963*4882a593Smuzhiyun 		0x1c, 0x009,		/* Out Mux1 */
1964*4882a593Smuzhiyun 		0x1d, 0x009,		/* Out Mux2 */
1965*4882a593Smuzhiyun 
1966*4882a593Smuzhiyun 		0x18, 0x000,		/* All power-up */
1967*4882a593Smuzhiyun 
1968*4882a593Smuzhiyun 		0x16, 0x022,		/* I2S, normal polarity, 24bit, high-pass on */
1969*4882a593Smuzhiyun 		0x17, 0x006,		/* 128fs, slave mode */
1970*4882a593Smuzhiyun 
1971*4882a593Smuzhiyun 		0x00, 0,		/* DAC1 analog mute */
1972*4882a593Smuzhiyun 		0x01, 0,		/* DAC2 analog mute */
1973*4882a593Smuzhiyun 		0x02, 0,		/* DAC3 analog mute */
1974*4882a593Smuzhiyun 		0x03, 0,		/* DAC4 analog mute */
1975*4882a593Smuzhiyun 		0x04, 0,		/* DAC5 analog mute */
1976*4882a593Smuzhiyun 		0x05, 0,		/* DAC6 analog mute */
1977*4882a593Smuzhiyun 		0x06, 0,		/* DAC7 analog mute */
1978*4882a593Smuzhiyun 		0x07, 0,		/* DAC8 analog mute */
1979*4882a593Smuzhiyun 		0x08, 0x100,		/* master analog mute */
1980*4882a593Smuzhiyun 
1981*4882a593Smuzhiyun 		0x09, 0x7f,		/* DAC1 digital full */
1982*4882a593Smuzhiyun 		0x0a, 0x7f,		/* DAC2 digital full */
1983*4882a593Smuzhiyun 		0x0b, 0x7f,		/* DAC3 digital full */
1984*4882a593Smuzhiyun 		0x0c, 0x7f,		/* DAC4 digital full */
1985*4882a593Smuzhiyun 		0x0d, 0x7f,		/* DAC5 digital full */
1986*4882a593Smuzhiyun 		0x0e, 0x7f,		/* DAC6 digital full */
1987*4882a593Smuzhiyun 		0x0f, 0x7f,		/* DAC7 digital full */
1988*4882a593Smuzhiyun 		0x10, 0x7f,		/* DAC8 digital full */
1989*4882a593Smuzhiyun 		0x11, 0x1FF,		/* master digital full */
1990*4882a593Smuzhiyun 
1991*4882a593Smuzhiyun 		0x12, 0x000,		/* phase normal */
1992*4882a593Smuzhiyun 		0x13, 0x090,		/* unmute DAC L/R */
1993*4882a593Smuzhiyun 		0x14, 0x000,		/* all unmute */
1994*4882a593Smuzhiyun 		0x15, 0x000,		/* no deemphasis, no ZFLG */
1995*4882a593Smuzhiyun 
1996*4882a593Smuzhiyun 		0x19, 0x000,		/* -12dB ADC/L */
1997*4882a593Smuzhiyun 		0x1a, 0x000,		/* -12dB ADC/R */
1998*4882a593Smuzhiyun 		(unsigned short)-1
1999*4882a593Smuzhiyun 
2000*4882a593Smuzhiyun 	};
2001*4882a593Smuzhiyun 	static const unsigned short cs_inits[] = {
2002*4882a593Smuzhiyun 		0x0441, /* RUN */
2003*4882a593Smuzhiyun 		0x0180, /* no mute, OMCK output on RMCK pin */
2004*4882a593Smuzhiyun 		0x0201, /* S/PDIF source on RXP1 */
2005*4882a593Smuzhiyun 		0x0605, /* slave, 24bit, MSB on second OSCLK, SDOUT for right channel when OLRCK is high */
2006*4882a593Smuzhiyun 		(unsigned short)-1
2007*4882a593Smuzhiyun 	};
2008*4882a593Smuzhiyun 	unsigned int tmp;
2009*4882a593Smuzhiyun 	const unsigned short *p;
2010*4882a593Smuzhiyun 	int err;
2011*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
2012*4882a593Smuzhiyun 
2013*4882a593Smuzhiyun 	err = aureon_ac97_init(ice);
2014*4882a593Smuzhiyun 	if (err != 0)
2015*4882a593Smuzhiyun 		return err;
2016*4882a593Smuzhiyun 
2017*4882a593Smuzhiyun 	snd_ice1712_gpio_set_dir(ice, 0x5fffff); /* fix this for the time being */
2018*4882a593Smuzhiyun 
2019*4882a593Smuzhiyun 	/* reset the wm codec as the SPI mode */
2020*4882a593Smuzhiyun 	snd_ice1712_save_gpio_status(ice);
2021*4882a593Smuzhiyun 	snd_ice1712_gpio_set_mask(ice, ~(AUREON_WM_RESET|AUREON_WM_CS|AUREON_CS8415_CS|AUREON_HP_SEL));
2022*4882a593Smuzhiyun 
2023*4882a593Smuzhiyun 	tmp = snd_ice1712_gpio_read(ice);
2024*4882a593Smuzhiyun 	tmp &= ~AUREON_WM_RESET;
2025*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
2026*4882a593Smuzhiyun 	udelay(1);
2027*4882a593Smuzhiyun 	tmp |= AUREON_WM_CS | AUREON_CS8415_CS;
2028*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
2029*4882a593Smuzhiyun 	udelay(1);
2030*4882a593Smuzhiyun 	tmp |= AUREON_WM_RESET;
2031*4882a593Smuzhiyun 	snd_ice1712_gpio_write(ice, tmp);
2032*4882a593Smuzhiyun 	udelay(1);
2033*4882a593Smuzhiyun 
2034*4882a593Smuzhiyun 	/* initialize WM8770 codec */
2035*4882a593Smuzhiyun 	if (ice->eeprom.subvendor == VT1724_SUBDEVICE_PRODIGY71 ||
2036*4882a593Smuzhiyun 		ice->eeprom.subvendor == VT1724_SUBDEVICE_PRODIGY71LT ||
2037*4882a593Smuzhiyun 		ice->eeprom.subvendor == VT1724_SUBDEVICE_PRODIGY71XT)
2038*4882a593Smuzhiyun 		p = wm_inits_prodigy;
2039*4882a593Smuzhiyun 	else
2040*4882a593Smuzhiyun 		p = wm_inits_aureon;
2041*4882a593Smuzhiyun 	for (; *p != (unsigned short)-1; p += 2)
2042*4882a593Smuzhiyun 		wm_put(ice, p[0], p[1]);
2043*4882a593Smuzhiyun 
2044*4882a593Smuzhiyun 	/* initialize CS8415A codec */
2045*4882a593Smuzhiyun 	if (ice->eeprom.subvendor != VT1724_SUBDEVICE_PRODIGY71LT &&
2046*4882a593Smuzhiyun 	    ice->eeprom.subvendor != VT1724_SUBDEVICE_PRODIGY71XT) {
2047*4882a593Smuzhiyun 		for (p = cs_inits; *p != (unsigned short)-1; p++)
2048*4882a593Smuzhiyun 			aureon_spi_write(ice, AUREON_CS8415_CS, *p | 0x200000, 24);
2049*4882a593Smuzhiyun 		spec->cs8415_mux = 1;
2050*4882a593Smuzhiyun 
2051*4882a593Smuzhiyun 		aureon_set_headphone_amp(ice, 1);
2052*4882a593Smuzhiyun 	}
2053*4882a593Smuzhiyun 
2054*4882a593Smuzhiyun 	snd_ice1712_restore_gpio_status(ice);
2055*4882a593Smuzhiyun 
2056*4882a593Smuzhiyun 	/* initialize PCA9554 pin directions & set default input */
2057*4882a593Smuzhiyun 	aureon_pca9554_write(ice, PCA9554_DIR, 0x00);
2058*4882a593Smuzhiyun 	aureon_pca9554_write(ice, PCA9554_OUT, 0x00);   /* internal AUX */
2059*4882a593Smuzhiyun 	return 0;
2060*4882a593Smuzhiyun }
2061*4882a593Smuzhiyun 
2062*4882a593Smuzhiyun /*
2063*4882a593Smuzhiyun  * suspend/resume
2064*4882a593Smuzhiyun  */
2065*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
aureon_resume(struct snd_ice1712 * ice)2066*4882a593Smuzhiyun static int aureon_resume(struct snd_ice1712 *ice)
2067*4882a593Smuzhiyun {
2068*4882a593Smuzhiyun 	struct aureon_spec *spec = ice->spec;
2069*4882a593Smuzhiyun 	int err, i;
2070*4882a593Smuzhiyun 
2071*4882a593Smuzhiyun 	err = aureon_reset(ice);
2072*4882a593Smuzhiyun 	if (err != 0)
2073*4882a593Smuzhiyun 		return err;
2074*4882a593Smuzhiyun 
2075*4882a593Smuzhiyun 	/* workaround for poking volume with alsamixer after resume:
2076*4882a593Smuzhiyun 	 * just set stored volume again */
2077*4882a593Smuzhiyun 	for (i = 0; i < ice->num_total_dacs; i++)
2078*4882a593Smuzhiyun 		wm_set_vol(ice, i, spec->vol[i], spec->master[i % 2]);
2079*4882a593Smuzhiyun 	return 0;
2080*4882a593Smuzhiyun }
2081*4882a593Smuzhiyun #endif
2082*4882a593Smuzhiyun 
2083*4882a593Smuzhiyun /*
2084*4882a593Smuzhiyun  * initialize the chip
2085*4882a593Smuzhiyun  */
aureon_init(struct snd_ice1712 * ice)2086*4882a593Smuzhiyun static int aureon_init(struct snd_ice1712 *ice)
2087*4882a593Smuzhiyun {
2088*4882a593Smuzhiyun 	struct aureon_spec *spec;
2089*4882a593Smuzhiyun 	int i, err;
2090*4882a593Smuzhiyun 
2091*4882a593Smuzhiyun 	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2092*4882a593Smuzhiyun 	if (!spec)
2093*4882a593Smuzhiyun 		return -ENOMEM;
2094*4882a593Smuzhiyun 	ice->spec = spec;
2095*4882a593Smuzhiyun 
2096*4882a593Smuzhiyun 	if (ice->eeprom.subvendor == VT1724_SUBDEVICE_AUREON51_SKY) {
2097*4882a593Smuzhiyun 		ice->num_total_dacs = 6;
2098*4882a593Smuzhiyun 		ice->num_total_adcs = 2;
2099*4882a593Smuzhiyun 	} else {
2100*4882a593Smuzhiyun 		/* aureon 7.1 and prodigy 7.1 */
2101*4882a593Smuzhiyun 		ice->num_total_dacs = 8;
2102*4882a593Smuzhiyun 		ice->num_total_adcs = 2;
2103*4882a593Smuzhiyun 	}
2104*4882a593Smuzhiyun 
2105*4882a593Smuzhiyun 	/* to remember the register values of CS8415 */
2106*4882a593Smuzhiyun 	ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
2107*4882a593Smuzhiyun 	if (!ice->akm)
2108*4882a593Smuzhiyun 		return -ENOMEM;
2109*4882a593Smuzhiyun 	ice->akm_codecs = 1;
2110*4882a593Smuzhiyun 
2111*4882a593Smuzhiyun 	err = aureon_reset(ice);
2112*4882a593Smuzhiyun 	if (err != 0)
2113*4882a593Smuzhiyun 		return err;
2114*4882a593Smuzhiyun 
2115*4882a593Smuzhiyun 	spec->master[0] = WM_VOL_MUTE;
2116*4882a593Smuzhiyun 	spec->master[1] = WM_VOL_MUTE;
2117*4882a593Smuzhiyun 	for (i = 0; i < ice->num_total_dacs; i++) {
2118*4882a593Smuzhiyun 		spec->vol[i] = WM_VOL_MUTE;
2119*4882a593Smuzhiyun 		wm_set_vol(ice, i, spec->vol[i], spec->master[i % 2]);
2120*4882a593Smuzhiyun 	}
2121*4882a593Smuzhiyun 
2122*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
2123*4882a593Smuzhiyun 	ice->pm_resume = aureon_resume;
2124*4882a593Smuzhiyun 	ice->pm_suspend_enabled = 1;
2125*4882a593Smuzhiyun #endif
2126*4882a593Smuzhiyun 
2127*4882a593Smuzhiyun 	return 0;
2128*4882a593Smuzhiyun }
2129*4882a593Smuzhiyun 
2130*4882a593Smuzhiyun 
2131*4882a593Smuzhiyun /*
2132*4882a593Smuzhiyun  * Aureon boards don't provide the EEPROM data except for the vendor IDs.
2133*4882a593Smuzhiyun  * hence the driver needs to sets up it properly.
2134*4882a593Smuzhiyun  */
2135*4882a593Smuzhiyun 
2136*4882a593Smuzhiyun static const unsigned char aureon51_eeprom[] = {
2137*4882a593Smuzhiyun 	[ICE_EEP2_SYSCONF]     = 0x0a,	/* clock 512, spdif-in/ADC, 3DACs */
2138*4882a593Smuzhiyun 	[ICE_EEP2_ACLINK]      = 0x80,	/* I2S */
2139*4882a593Smuzhiyun 	[ICE_EEP2_I2S]         = 0xfc,	/* vol, 96k, 24bit, 192k */
2140*4882a593Smuzhiyun 	[ICE_EEP2_SPDIF]       = 0xc3,	/* out-en, out-int, spdif-in */
2141*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR]    = 0xff,
2142*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR1]   = 0xff,
2143*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR2]   = 0x5f,
2144*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK]   = 0x00,
2145*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK1]  = 0x00,
2146*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK2]  = 0x00,
2147*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE]  = 0x00,
2148*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE1] = 0x00,
2149*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE2] = 0x00,
2150*4882a593Smuzhiyun };
2151*4882a593Smuzhiyun 
2152*4882a593Smuzhiyun static const unsigned char aureon71_eeprom[] = {
2153*4882a593Smuzhiyun 	[ICE_EEP2_SYSCONF]     = 0x0b,	/* clock 512, spdif-in/ADC, 4DACs */
2154*4882a593Smuzhiyun 	[ICE_EEP2_ACLINK]      = 0x80,	/* I2S */
2155*4882a593Smuzhiyun 	[ICE_EEP2_I2S]         = 0xfc,	/* vol, 96k, 24bit, 192k */
2156*4882a593Smuzhiyun 	[ICE_EEP2_SPDIF]       = 0xc3,	/* out-en, out-int, spdif-in */
2157*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR]    = 0xff,
2158*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR1]   = 0xff,
2159*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR2]   = 0x5f,
2160*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK]   = 0x00,
2161*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK1]  = 0x00,
2162*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK2]  = 0x00,
2163*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE]  = 0x00,
2164*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE1] = 0x00,
2165*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE2] = 0x00,
2166*4882a593Smuzhiyun };
2167*4882a593Smuzhiyun #define prodigy71_eeprom aureon71_eeprom
2168*4882a593Smuzhiyun 
2169*4882a593Smuzhiyun static const unsigned char aureon71_universe_eeprom[] = {
2170*4882a593Smuzhiyun 	[ICE_EEP2_SYSCONF]     = 0x2b,	/* clock 512, mpu401, spdif-in/ADC,
2171*4882a593Smuzhiyun 					 * 4DACs
2172*4882a593Smuzhiyun 					 */
2173*4882a593Smuzhiyun 	[ICE_EEP2_ACLINK]      = 0x80,	/* I2S */
2174*4882a593Smuzhiyun 	[ICE_EEP2_I2S]         = 0xfc,	/* vol, 96k, 24bit, 192k */
2175*4882a593Smuzhiyun 	[ICE_EEP2_SPDIF]       = 0xc3,	/* out-en, out-int, spdif-in */
2176*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR]    = 0xff,
2177*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR1]   = 0xff,
2178*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR2]   = 0x5f,
2179*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK]   = 0x00,
2180*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK1]  = 0x00,
2181*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK2]  = 0x00,
2182*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE]  = 0x00,
2183*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE1] = 0x00,
2184*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE2] = 0x00,
2185*4882a593Smuzhiyun };
2186*4882a593Smuzhiyun 
2187*4882a593Smuzhiyun static const unsigned char prodigy71lt_eeprom[] = {
2188*4882a593Smuzhiyun 	[ICE_EEP2_SYSCONF]     = 0x4b,	/* clock 384, spdif-in/ADC, 4DACs */
2189*4882a593Smuzhiyun 	[ICE_EEP2_ACLINK]      = 0x80,	/* I2S */
2190*4882a593Smuzhiyun 	[ICE_EEP2_I2S]         = 0xfc,	/* vol, 96k, 24bit, 192k */
2191*4882a593Smuzhiyun 	[ICE_EEP2_SPDIF]       = 0xc3,	/* out-en, out-int, spdif-in */
2192*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR]    = 0xff,
2193*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR1]   = 0xff,
2194*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_DIR2]   = 0x5f,
2195*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK]   = 0x00,
2196*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK1]  = 0x00,
2197*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_MASK2]  = 0x00,
2198*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE]  = 0x00,
2199*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE1] = 0x00,
2200*4882a593Smuzhiyun 	[ICE_EEP2_GPIO_STATE2] = 0x00,
2201*4882a593Smuzhiyun };
2202*4882a593Smuzhiyun #define prodigy71xt_eeprom prodigy71lt_eeprom
2203*4882a593Smuzhiyun 
2204*4882a593Smuzhiyun /* entry point */
2205*4882a593Smuzhiyun struct snd_ice1712_card_info snd_vt1724_aureon_cards[] = {
2206*4882a593Smuzhiyun 	{
2207*4882a593Smuzhiyun 		.subvendor = VT1724_SUBDEVICE_AUREON51_SKY,
2208*4882a593Smuzhiyun 		.name = "Terratec Aureon 5.1-Sky",
2209*4882a593Smuzhiyun 		.model = "aureon51",
2210*4882a593Smuzhiyun 		.chip_init = aureon_init,
2211*4882a593Smuzhiyun 		.build_controls = aureon_add_controls,
2212*4882a593Smuzhiyun 		.eeprom_size = sizeof(aureon51_eeprom),
2213*4882a593Smuzhiyun 		.eeprom_data = aureon51_eeprom,
2214*4882a593Smuzhiyun 		.driver = "Aureon51",
2215*4882a593Smuzhiyun 	},
2216*4882a593Smuzhiyun 	{
2217*4882a593Smuzhiyun 		.subvendor = VT1724_SUBDEVICE_AUREON71_SPACE,
2218*4882a593Smuzhiyun 		.name = "Terratec Aureon 7.1-Space",
2219*4882a593Smuzhiyun 		.model = "aureon71",
2220*4882a593Smuzhiyun 		.chip_init = aureon_init,
2221*4882a593Smuzhiyun 		.build_controls = aureon_add_controls,
2222*4882a593Smuzhiyun 		.eeprom_size = sizeof(aureon71_eeprom),
2223*4882a593Smuzhiyun 		.eeprom_data = aureon71_eeprom,
2224*4882a593Smuzhiyun 		.driver = "Aureon71",
2225*4882a593Smuzhiyun 	},
2226*4882a593Smuzhiyun 	{
2227*4882a593Smuzhiyun 		.subvendor = VT1724_SUBDEVICE_AUREON71_UNIVERSE,
2228*4882a593Smuzhiyun 		.name = "Terratec Aureon 7.1-Universe",
2229*4882a593Smuzhiyun 		.model = "universe",
2230*4882a593Smuzhiyun 		.chip_init = aureon_init,
2231*4882a593Smuzhiyun 		.build_controls = aureon_add_controls,
2232*4882a593Smuzhiyun 		.eeprom_size = sizeof(aureon71_universe_eeprom),
2233*4882a593Smuzhiyun 		.eeprom_data = aureon71_universe_eeprom,
2234*4882a593Smuzhiyun 		.driver = "Aureon71Univ", /* keep in 15 letters */
2235*4882a593Smuzhiyun 	},
2236*4882a593Smuzhiyun 	{
2237*4882a593Smuzhiyun 		.subvendor = VT1724_SUBDEVICE_PRODIGY71,
2238*4882a593Smuzhiyun 		.name = "Audiotrak Prodigy 7.1",
2239*4882a593Smuzhiyun 		.model = "prodigy71",
2240*4882a593Smuzhiyun 		.chip_init = aureon_init,
2241*4882a593Smuzhiyun 		.build_controls = aureon_add_controls,
2242*4882a593Smuzhiyun 		.eeprom_size = sizeof(prodigy71_eeprom),
2243*4882a593Smuzhiyun 		.eeprom_data = prodigy71_eeprom,
2244*4882a593Smuzhiyun 		.driver = "Prodigy71", /* should be identical with Aureon71 */
2245*4882a593Smuzhiyun 	},
2246*4882a593Smuzhiyun 	{
2247*4882a593Smuzhiyun 		.subvendor = VT1724_SUBDEVICE_PRODIGY71LT,
2248*4882a593Smuzhiyun 		.name = "Audiotrak Prodigy 7.1 LT",
2249*4882a593Smuzhiyun 		.model = "prodigy71lt",
2250*4882a593Smuzhiyun 		.chip_init = aureon_init,
2251*4882a593Smuzhiyun 		.build_controls = aureon_add_controls,
2252*4882a593Smuzhiyun 		.eeprom_size = sizeof(prodigy71lt_eeprom),
2253*4882a593Smuzhiyun 		.eeprom_data = prodigy71lt_eeprom,
2254*4882a593Smuzhiyun 		.driver = "Prodigy71LT",
2255*4882a593Smuzhiyun 	},
2256*4882a593Smuzhiyun 	{
2257*4882a593Smuzhiyun 		.subvendor = VT1724_SUBDEVICE_PRODIGY71XT,
2258*4882a593Smuzhiyun 		.name = "Audiotrak Prodigy 7.1 XT",
2259*4882a593Smuzhiyun 		.model = "prodigy71xt",
2260*4882a593Smuzhiyun 		.chip_init = aureon_init,
2261*4882a593Smuzhiyun 		.build_controls = aureon_add_controls,
2262*4882a593Smuzhiyun 		.eeprom_size = sizeof(prodigy71xt_eeprom),
2263*4882a593Smuzhiyun 		.eeprom_data = prodigy71xt_eeprom,
2264*4882a593Smuzhiyun 		.driver = "Prodigy71LT",
2265*4882a593Smuzhiyun 	},
2266*4882a593Smuzhiyun 	{ } /* terminator */
2267*4882a593Smuzhiyun };
2268