xref: /OK3568_Linux_fs/kernel/sound/pci/fm801.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  The driver for the ForteMedia FM801 based soundcards
4*4882a593Smuzhiyun  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <sound/core.h>
15*4882a593Smuzhiyun #include <sound/pcm.h>
16*4882a593Smuzhiyun #include <sound/tlv.h>
17*4882a593Smuzhiyun #include <sound/ac97_codec.h>
18*4882a593Smuzhiyun #include <sound/mpu401.h>
19*4882a593Smuzhiyun #include <sound/opl3.h>
20*4882a593Smuzhiyun #include <sound/initval.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #ifdef CONFIG_SND_FM801_TEA575X_BOOL
23*4882a593Smuzhiyun #include <media/drv-intf/tea575x.h>
24*4882a593Smuzhiyun #endif
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
27*4882a593Smuzhiyun MODULE_DESCRIPTION("ForteMedia FM801");
28*4882a593Smuzhiyun MODULE_LICENSE("GPL");
29*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{{ForteMedia,FM801},"
30*4882a593Smuzhiyun 		"{Genius,SoundMaker Live 5.1}}");
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
33*4882a593Smuzhiyun static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
34*4882a593Smuzhiyun static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun  *  Enable TEA575x tuner
37*4882a593Smuzhiyun  *    1 = MediaForte 256-PCS
38*4882a593Smuzhiyun  *    2 = MediaForte 256-PCP
39*4882a593Smuzhiyun  *    3 = MediaForte 64-PCR
40*4882a593Smuzhiyun  *   16 = setup tuner only (this is additional bit), i.e. SF64-PCR FM card
41*4882a593Smuzhiyun  *  High 16-bits are video (radio) device number + 1
42*4882a593Smuzhiyun  */
43*4882a593Smuzhiyun static int tea575x_tuner[SNDRV_CARDS];
44*4882a593Smuzhiyun static int radio_nr[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun module_param_array(index, int, NULL, 0444);
47*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for the FM801 soundcard.");
48*4882a593Smuzhiyun module_param_array(id, charp, NULL, 0444);
49*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for the FM801 soundcard.");
50*4882a593Smuzhiyun module_param_array(enable, bool, NULL, 0444);
51*4882a593Smuzhiyun MODULE_PARM_DESC(enable, "Enable FM801 soundcard.");
52*4882a593Smuzhiyun module_param_array(tea575x_tuner, int, NULL, 0444);
53*4882a593Smuzhiyun MODULE_PARM_DESC(tea575x_tuner, "TEA575x tuner access method (0 = auto, 1 = SF256-PCS, 2=SF256-PCP, 3=SF64-PCR, 8=disable, +16=tuner-only).");
54*4882a593Smuzhiyun module_param_array(radio_nr, int, NULL, 0444);
55*4882a593Smuzhiyun MODULE_PARM_DESC(radio_nr, "Radio device numbers");
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define TUNER_DISABLED		(1<<3)
59*4882a593Smuzhiyun #define TUNER_ONLY		(1<<4)
60*4882a593Smuzhiyun #define TUNER_TYPE_MASK		(~TUNER_ONLY & 0xFFFF)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun  *  Direct registers
64*4882a593Smuzhiyun  */
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define fm801_writew(chip,reg,value)	outw((value), chip->port + FM801_##reg)
67*4882a593Smuzhiyun #define fm801_readw(chip,reg)		inw(chip->port + FM801_##reg)
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define fm801_writel(chip,reg,value)	outl((value), chip->port + FM801_##reg)
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define FM801_PCM_VOL		0x00	/* PCM Output Volume */
72*4882a593Smuzhiyun #define FM801_FM_VOL		0x02	/* FM Output Volume */
73*4882a593Smuzhiyun #define FM801_I2S_VOL		0x04	/* I2S Volume */
74*4882a593Smuzhiyun #define FM801_REC_SRC		0x06	/* Record Source */
75*4882a593Smuzhiyun #define FM801_PLY_CTRL		0x08	/* Playback Control */
76*4882a593Smuzhiyun #define FM801_PLY_COUNT		0x0a	/* Playback Count */
77*4882a593Smuzhiyun #define FM801_PLY_BUF1		0x0c	/* Playback Bufer I */
78*4882a593Smuzhiyun #define FM801_PLY_BUF2		0x10	/* Playback Buffer II */
79*4882a593Smuzhiyun #define FM801_CAP_CTRL		0x14	/* Capture Control */
80*4882a593Smuzhiyun #define FM801_CAP_COUNT		0x16	/* Capture Count */
81*4882a593Smuzhiyun #define FM801_CAP_BUF1		0x18	/* Capture Buffer I */
82*4882a593Smuzhiyun #define FM801_CAP_BUF2		0x1c	/* Capture Buffer II */
83*4882a593Smuzhiyun #define FM801_CODEC_CTRL	0x22	/* Codec Control */
84*4882a593Smuzhiyun #define FM801_I2S_MODE		0x24	/* I2S Mode Control */
85*4882a593Smuzhiyun #define FM801_VOLUME		0x26	/* Volume Up/Down/Mute Status */
86*4882a593Smuzhiyun #define FM801_I2C_CTRL		0x29	/* I2C Control */
87*4882a593Smuzhiyun #define FM801_AC97_CMD		0x2a	/* AC'97 Command */
88*4882a593Smuzhiyun #define FM801_AC97_DATA		0x2c	/* AC'97 Data */
89*4882a593Smuzhiyun #define FM801_MPU401_DATA	0x30	/* MPU401 Data */
90*4882a593Smuzhiyun #define FM801_MPU401_CMD	0x31	/* MPU401 Command */
91*4882a593Smuzhiyun #define FM801_GPIO_CTRL		0x52	/* General Purpose I/O Control */
92*4882a593Smuzhiyun #define FM801_GEN_CTRL		0x54	/* General Control */
93*4882a593Smuzhiyun #define FM801_IRQ_MASK		0x56	/* Interrupt Mask */
94*4882a593Smuzhiyun #define FM801_IRQ_STATUS	0x5a	/* Interrupt Status */
95*4882a593Smuzhiyun #define FM801_OPL3_BANK0	0x68	/* OPL3 Status Read / Bank 0 Write */
96*4882a593Smuzhiyun #define FM801_OPL3_DATA0	0x69	/* OPL3 Data 0 Write */
97*4882a593Smuzhiyun #define FM801_OPL3_BANK1	0x6a	/* OPL3 Bank 1 Write */
98*4882a593Smuzhiyun #define FM801_OPL3_DATA1	0x6b	/* OPL3 Bank 1 Write */
99*4882a593Smuzhiyun #define FM801_POWERDOWN		0x70	/* Blocks Power Down Control */
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* codec access */
102*4882a593Smuzhiyun #define FM801_AC97_READ		(1<<7)	/* read=1, write=0 */
103*4882a593Smuzhiyun #define FM801_AC97_VALID	(1<<8)	/* port valid=1 */
104*4882a593Smuzhiyun #define FM801_AC97_BUSY		(1<<9)	/* busy=1 */
105*4882a593Smuzhiyun #define FM801_AC97_ADDR_SHIFT	10	/* codec id (2bit) */
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* playback and record control register bits */
108*4882a593Smuzhiyun #define FM801_BUF1_LAST		(1<<1)
109*4882a593Smuzhiyun #define FM801_BUF2_LAST		(1<<2)
110*4882a593Smuzhiyun #define FM801_START		(1<<5)
111*4882a593Smuzhiyun #define FM801_PAUSE		(1<<6)
112*4882a593Smuzhiyun #define FM801_IMMED_STOP	(1<<7)
113*4882a593Smuzhiyun #define FM801_RATE_SHIFT	8
114*4882a593Smuzhiyun #define FM801_RATE_MASK		(15 << FM801_RATE_SHIFT)
115*4882a593Smuzhiyun #define FM801_CHANNELS_4	(1<<12)	/* playback only */
116*4882a593Smuzhiyun #define FM801_CHANNELS_6	(2<<12)	/* playback only */
117*4882a593Smuzhiyun #define FM801_CHANNELS_6MS	(3<<12)	/* playback only */
118*4882a593Smuzhiyun #define FM801_CHANNELS_MASK	(3<<12)
119*4882a593Smuzhiyun #define FM801_16BIT		(1<<14)
120*4882a593Smuzhiyun #define FM801_STEREO		(1<<15)
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /* IRQ status bits */
123*4882a593Smuzhiyun #define FM801_IRQ_PLAYBACK	(1<<8)
124*4882a593Smuzhiyun #define FM801_IRQ_CAPTURE	(1<<9)
125*4882a593Smuzhiyun #define FM801_IRQ_VOLUME	(1<<14)
126*4882a593Smuzhiyun #define FM801_IRQ_MPU		(1<<15)
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun /* GPIO control register */
129*4882a593Smuzhiyun #define FM801_GPIO_GP0		(1<<0)	/* read/write */
130*4882a593Smuzhiyun #define FM801_GPIO_GP1		(1<<1)
131*4882a593Smuzhiyun #define FM801_GPIO_GP2		(1<<2)
132*4882a593Smuzhiyun #define FM801_GPIO_GP3		(1<<3)
133*4882a593Smuzhiyun #define FM801_GPIO_GP(x)	(1<<(0+(x)))
134*4882a593Smuzhiyun #define FM801_GPIO_GD0		(1<<8)	/* directions: 1 = input, 0 = output*/
135*4882a593Smuzhiyun #define FM801_GPIO_GD1		(1<<9)
136*4882a593Smuzhiyun #define FM801_GPIO_GD2		(1<<10)
137*4882a593Smuzhiyun #define FM801_GPIO_GD3		(1<<11)
138*4882a593Smuzhiyun #define FM801_GPIO_GD(x)	(1<<(8+(x)))
139*4882a593Smuzhiyun #define FM801_GPIO_GS0		(1<<12)	/* function select: */
140*4882a593Smuzhiyun #define FM801_GPIO_GS1		(1<<13)	/*    1 = GPIO */
141*4882a593Smuzhiyun #define FM801_GPIO_GS2		(1<<14)	/*    0 = other (S/PDIF, VOL) */
142*4882a593Smuzhiyun #define FM801_GPIO_GS3		(1<<15)
143*4882a593Smuzhiyun #define FM801_GPIO_GS(x)	(1<<(12+(x)))
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /**
146*4882a593Smuzhiyun  * struct fm801 - describes FM801 chip
147*4882a593Smuzhiyun  * @dev:		device for this chio
148*4882a593Smuzhiyun  * @irq:		irq number
149*4882a593Smuzhiyun  * @port:		I/O port number
150*4882a593Smuzhiyun  * @multichannel:	multichannel support
151*4882a593Smuzhiyun  * @secondary:		secondary codec
152*4882a593Smuzhiyun  * @secondary_addr:	address of the secondary codec
153*4882a593Smuzhiyun  * @tea575x_tuner:	tuner access method & flags
154*4882a593Smuzhiyun  * @ply_ctrl:		playback control
155*4882a593Smuzhiyun  * @cap_ctrl:		capture control
156*4882a593Smuzhiyun  * @ply_buffer:		playback buffer
157*4882a593Smuzhiyun  * @ply_buf:		playback buffer index
158*4882a593Smuzhiyun  * @ply_count:		playback buffer count
159*4882a593Smuzhiyun  * @ply_size:		playback buffer size
160*4882a593Smuzhiyun  * @ply_pos:		playback position
161*4882a593Smuzhiyun  * @cap_buffer:		capture buffer
162*4882a593Smuzhiyun  * @cap_buf:		capture buffer index
163*4882a593Smuzhiyun  * @cap_count:		capture buffer count
164*4882a593Smuzhiyun  * @cap_size:		capture buffer size
165*4882a593Smuzhiyun  * @cap_pos:		capture position
166*4882a593Smuzhiyun  * @ac97_bus:		ac97 bus handle
167*4882a593Smuzhiyun  * @ac97:		ac97 handle
168*4882a593Smuzhiyun  * @ac97_sec:		ac97 secondary handle
169*4882a593Smuzhiyun  * @card:		ALSA card
170*4882a593Smuzhiyun  * @pcm:		PCM devices
171*4882a593Smuzhiyun  * @rmidi:		rmidi device
172*4882a593Smuzhiyun  * @playback_substream:	substream for playback
173*4882a593Smuzhiyun  * @capture_substream:	substream for capture
174*4882a593Smuzhiyun  * @p_dma_size:		playback DMA size
175*4882a593Smuzhiyun  * @c_dma_size:		capture DMA size
176*4882a593Smuzhiyun  * @reg_lock:		lock
177*4882a593Smuzhiyun  * @proc_entry:		/proc entry
178*4882a593Smuzhiyun  * @v4l2_dev:		v4l2 device
179*4882a593Smuzhiyun  * @tea:		tea575a structure
180*4882a593Smuzhiyun  * @saved_regs:		context saved during suspend
181*4882a593Smuzhiyun  */
182*4882a593Smuzhiyun struct fm801 {
183*4882a593Smuzhiyun 	struct device *dev;
184*4882a593Smuzhiyun 	int irq;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	unsigned long port;
187*4882a593Smuzhiyun 	unsigned int multichannel: 1,
188*4882a593Smuzhiyun 		     secondary: 1;
189*4882a593Smuzhiyun 	unsigned char secondary_addr;
190*4882a593Smuzhiyun 	unsigned int tea575x_tuner;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	unsigned short ply_ctrl;
193*4882a593Smuzhiyun 	unsigned short cap_ctrl;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	unsigned long ply_buffer;
196*4882a593Smuzhiyun 	unsigned int ply_buf;
197*4882a593Smuzhiyun 	unsigned int ply_count;
198*4882a593Smuzhiyun 	unsigned int ply_size;
199*4882a593Smuzhiyun 	unsigned int ply_pos;
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	unsigned long cap_buffer;
202*4882a593Smuzhiyun 	unsigned int cap_buf;
203*4882a593Smuzhiyun 	unsigned int cap_count;
204*4882a593Smuzhiyun 	unsigned int cap_size;
205*4882a593Smuzhiyun 	unsigned int cap_pos;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	struct snd_ac97_bus *ac97_bus;
208*4882a593Smuzhiyun 	struct snd_ac97 *ac97;
209*4882a593Smuzhiyun 	struct snd_ac97 *ac97_sec;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	struct snd_card *card;
212*4882a593Smuzhiyun 	struct snd_pcm *pcm;
213*4882a593Smuzhiyun 	struct snd_rawmidi *rmidi;
214*4882a593Smuzhiyun 	struct snd_pcm_substream *playback_substream;
215*4882a593Smuzhiyun 	struct snd_pcm_substream *capture_substream;
216*4882a593Smuzhiyun 	unsigned int p_dma_size;
217*4882a593Smuzhiyun 	unsigned int c_dma_size;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	spinlock_t reg_lock;
220*4882a593Smuzhiyun 	struct snd_info_entry *proc_entry;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun #ifdef CONFIG_SND_FM801_TEA575X_BOOL
223*4882a593Smuzhiyun 	struct v4l2_device v4l2_dev;
224*4882a593Smuzhiyun 	struct snd_tea575x tea;
225*4882a593Smuzhiyun #endif
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
228*4882a593Smuzhiyun 	u16 saved_regs[0x20];
229*4882a593Smuzhiyun #endif
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun /*
233*4882a593Smuzhiyun  * IO accessors
234*4882a593Smuzhiyun  */
235*4882a593Smuzhiyun 
fm801_iowrite16(struct fm801 * chip,unsigned short offset,u16 value)236*4882a593Smuzhiyun static inline void fm801_iowrite16(struct fm801 *chip, unsigned short offset, u16 value)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun 	outw(value, chip->port + offset);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun 
fm801_ioread16(struct fm801 * chip,unsigned short offset)241*4882a593Smuzhiyun static inline u16 fm801_ioread16(struct fm801 *chip, unsigned short offset)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	return inw(chip->port + offset);
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun static const struct pci_device_id snd_fm801_ids[] = {
247*4882a593Smuzhiyun 	{ 0x1319, 0x0801, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, },   /* FM801 */
248*4882a593Smuzhiyun 	{ 0x5213, 0x0510, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, },   /* Gallant Odyssey Sound 4 */
249*4882a593Smuzhiyun 	{ 0, }
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, snd_fm801_ids);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun /*
255*4882a593Smuzhiyun  *  common I/O routines
256*4882a593Smuzhiyun  */
257*4882a593Smuzhiyun 
fm801_ac97_is_ready(struct fm801 * chip,unsigned int iterations)258*4882a593Smuzhiyun static bool fm801_ac97_is_ready(struct fm801 *chip, unsigned int iterations)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	unsigned int idx;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	for (idx = 0; idx < iterations; idx++) {
263*4882a593Smuzhiyun 		if (!(fm801_readw(chip, AC97_CMD) & FM801_AC97_BUSY))
264*4882a593Smuzhiyun 			return true;
265*4882a593Smuzhiyun 		udelay(10);
266*4882a593Smuzhiyun 	}
267*4882a593Smuzhiyun 	return false;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun 
fm801_ac97_is_valid(struct fm801 * chip,unsigned int iterations)270*4882a593Smuzhiyun static bool fm801_ac97_is_valid(struct fm801 *chip, unsigned int iterations)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun 	unsigned int idx;
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	for (idx = 0; idx < iterations; idx++) {
275*4882a593Smuzhiyun 		if (fm801_readw(chip, AC97_CMD) & FM801_AC97_VALID)
276*4882a593Smuzhiyun 			return true;
277*4882a593Smuzhiyun 		udelay(10);
278*4882a593Smuzhiyun 	}
279*4882a593Smuzhiyun 	return false;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun 
snd_fm801_update_bits(struct fm801 * chip,unsigned short reg,unsigned short mask,unsigned short value)282*4882a593Smuzhiyun static int snd_fm801_update_bits(struct fm801 *chip, unsigned short reg,
283*4882a593Smuzhiyun 				 unsigned short mask, unsigned short value)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	int change;
286*4882a593Smuzhiyun 	unsigned long flags;
287*4882a593Smuzhiyun 	unsigned short old, new;
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
290*4882a593Smuzhiyun 	old = fm801_ioread16(chip, reg);
291*4882a593Smuzhiyun 	new = (old & ~mask) | value;
292*4882a593Smuzhiyun 	change = old != new;
293*4882a593Smuzhiyun 	if (change)
294*4882a593Smuzhiyun 		fm801_iowrite16(chip, reg, new);
295*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
296*4882a593Smuzhiyun 	return change;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun 
snd_fm801_codec_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)299*4882a593Smuzhiyun static void snd_fm801_codec_write(struct snd_ac97 *ac97,
300*4882a593Smuzhiyun 				  unsigned short reg,
301*4882a593Smuzhiyun 				  unsigned short val)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	struct fm801 *chip = ac97->private_data;
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	/*
306*4882a593Smuzhiyun 	 *  Wait until the codec interface is not ready..
307*4882a593Smuzhiyun 	 */
308*4882a593Smuzhiyun 	if (!fm801_ac97_is_ready(chip, 100)) {
309*4882a593Smuzhiyun 		dev_err(chip->card->dev, "AC'97 interface is busy (1)\n");
310*4882a593Smuzhiyun 		return;
311*4882a593Smuzhiyun 	}
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	/* write data and address */
314*4882a593Smuzhiyun 	fm801_writew(chip, AC97_DATA, val);
315*4882a593Smuzhiyun 	fm801_writew(chip, AC97_CMD, reg | (ac97->addr << FM801_AC97_ADDR_SHIFT));
316*4882a593Smuzhiyun 	/*
317*4882a593Smuzhiyun 	 *  Wait until the write command is not completed..
318*4882a593Smuzhiyun 	 */
319*4882a593Smuzhiyun 	if (!fm801_ac97_is_ready(chip, 1000))
320*4882a593Smuzhiyun 		dev_err(chip->card->dev, "AC'97 interface #%d is busy (2)\n",
321*4882a593Smuzhiyun 		ac97->num);
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun 
snd_fm801_codec_read(struct snd_ac97 * ac97,unsigned short reg)324*4882a593Smuzhiyun static unsigned short snd_fm801_codec_read(struct snd_ac97 *ac97, unsigned short reg)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	struct fm801 *chip = ac97->private_data;
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	/*
329*4882a593Smuzhiyun 	 *  Wait until the codec interface is not ready..
330*4882a593Smuzhiyun 	 */
331*4882a593Smuzhiyun 	if (!fm801_ac97_is_ready(chip, 100)) {
332*4882a593Smuzhiyun 		dev_err(chip->card->dev, "AC'97 interface is busy (1)\n");
333*4882a593Smuzhiyun 		return 0;
334*4882a593Smuzhiyun 	}
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	/* read command */
337*4882a593Smuzhiyun 	fm801_writew(chip, AC97_CMD,
338*4882a593Smuzhiyun 		     reg | (ac97->addr << FM801_AC97_ADDR_SHIFT) | FM801_AC97_READ);
339*4882a593Smuzhiyun 	if (!fm801_ac97_is_ready(chip, 100)) {
340*4882a593Smuzhiyun 		dev_err(chip->card->dev, "AC'97 interface #%d is busy (2)\n",
341*4882a593Smuzhiyun 			ac97->num);
342*4882a593Smuzhiyun 		return 0;
343*4882a593Smuzhiyun 	}
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	if (!fm801_ac97_is_valid(chip, 1000)) {
346*4882a593Smuzhiyun 		dev_err(chip->card->dev,
347*4882a593Smuzhiyun 			"AC'97 interface #%d is not valid (2)\n", ac97->num);
348*4882a593Smuzhiyun 		return 0;
349*4882a593Smuzhiyun 	}
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	return fm801_readw(chip, AC97_DATA);
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun static const unsigned int rates[] = {
355*4882a593Smuzhiyun   5500,  8000,  9600, 11025,
356*4882a593Smuzhiyun   16000, 19200, 22050, 32000,
357*4882a593Smuzhiyun   38400, 44100, 48000
358*4882a593Smuzhiyun };
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
361*4882a593Smuzhiyun 	.count = ARRAY_SIZE(rates),
362*4882a593Smuzhiyun 	.list = rates,
363*4882a593Smuzhiyun 	.mask = 0,
364*4882a593Smuzhiyun };
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun static const unsigned int channels[] = {
367*4882a593Smuzhiyun   2, 4, 6
368*4882a593Smuzhiyun };
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list hw_constraints_channels = {
371*4882a593Smuzhiyun 	.count = ARRAY_SIZE(channels),
372*4882a593Smuzhiyun 	.list = channels,
373*4882a593Smuzhiyun 	.mask = 0,
374*4882a593Smuzhiyun };
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun /*
377*4882a593Smuzhiyun  *  Sample rate routines
378*4882a593Smuzhiyun  */
379*4882a593Smuzhiyun 
snd_fm801_rate_bits(unsigned int rate)380*4882a593Smuzhiyun static unsigned short snd_fm801_rate_bits(unsigned int rate)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	unsigned int idx;
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	for (idx = 0; idx < ARRAY_SIZE(rates); idx++)
385*4882a593Smuzhiyun 		if (rates[idx] == rate)
386*4882a593Smuzhiyun 			return idx;
387*4882a593Smuzhiyun 	snd_BUG();
388*4882a593Smuzhiyun 	return ARRAY_SIZE(rates) - 1;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun /*
392*4882a593Smuzhiyun  *  PCM part
393*4882a593Smuzhiyun  */
394*4882a593Smuzhiyun 
snd_fm801_playback_trigger(struct snd_pcm_substream * substream,int cmd)395*4882a593Smuzhiyun static int snd_fm801_playback_trigger(struct snd_pcm_substream *substream,
396*4882a593Smuzhiyun 				      int cmd)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun 	struct fm801 *chip = snd_pcm_substream_chip(substream);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	spin_lock(&chip->reg_lock);
401*4882a593Smuzhiyun 	switch (cmd) {
402*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_START:
403*4882a593Smuzhiyun 		chip->ply_ctrl &= ~(FM801_BUF1_LAST |
404*4882a593Smuzhiyun 				     FM801_BUF2_LAST |
405*4882a593Smuzhiyun 				     FM801_PAUSE);
406*4882a593Smuzhiyun 		chip->ply_ctrl |= FM801_START |
407*4882a593Smuzhiyun 				   FM801_IMMED_STOP;
408*4882a593Smuzhiyun 		break;
409*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_STOP:
410*4882a593Smuzhiyun 		chip->ply_ctrl &= ~(FM801_START | FM801_PAUSE);
411*4882a593Smuzhiyun 		break;
412*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
413*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_SUSPEND:
414*4882a593Smuzhiyun 		chip->ply_ctrl |= FM801_PAUSE;
415*4882a593Smuzhiyun 		break;
416*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
417*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_RESUME:
418*4882a593Smuzhiyun 		chip->ply_ctrl &= ~FM801_PAUSE;
419*4882a593Smuzhiyun 		break;
420*4882a593Smuzhiyun 	default:
421*4882a593Smuzhiyun 		spin_unlock(&chip->reg_lock);
422*4882a593Smuzhiyun 		snd_BUG();
423*4882a593Smuzhiyun 		return -EINVAL;
424*4882a593Smuzhiyun 	}
425*4882a593Smuzhiyun 	fm801_writew(chip, PLY_CTRL, chip->ply_ctrl);
426*4882a593Smuzhiyun 	spin_unlock(&chip->reg_lock);
427*4882a593Smuzhiyun 	return 0;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun 
snd_fm801_capture_trigger(struct snd_pcm_substream * substream,int cmd)430*4882a593Smuzhiyun static int snd_fm801_capture_trigger(struct snd_pcm_substream *substream,
431*4882a593Smuzhiyun 				     int cmd)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun 	struct fm801 *chip = snd_pcm_substream_chip(substream);
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	spin_lock(&chip->reg_lock);
436*4882a593Smuzhiyun 	switch (cmd) {
437*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_START:
438*4882a593Smuzhiyun 		chip->cap_ctrl &= ~(FM801_BUF1_LAST |
439*4882a593Smuzhiyun 				     FM801_BUF2_LAST |
440*4882a593Smuzhiyun 				     FM801_PAUSE);
441*4882a593Smuzhiyun 		chip->cap_ctrl |= FM801_START |
442*4882a593Smuzhiyun 				   FM801_IMMED_STOP;
443*4882a593Smuzhiyun 		break;
444*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_STOP:
445*4882a593Smuzhiyun 		chip->cap_ctrl &= ~(FM801_START | FM801_PAUSE);
446*4882a593Smuzhiyun 		break;
447*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
448*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_SUSPEND:
449*4882a593Smuzhiyun 		chip->cap_ctrl |= FM801_PAUSE;
450*4882a593Smuzhiyun 		break;
451*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
452*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_RESUME:
453*4882a593Smuzhiyun 		chip->cap_ctrl &= ~FM801_PAUSE;
454*4882a593Smuzhiyun 		break;
455*4882a593Smuzhiyun 	default:
456*4882a593Smuzhiyun 		spin_unlock(&chip->reg_lock);
457*4882a593Smuzhiyun 		snd_BUG();
458*4882a593Smuzhiyun 		return -EINVAL;
459*4882a593Smuzhiyun 	}
460*4882a593Smuzhiyun 	fm801_writew(chip, CAP_CTRL, chip->cap_ctrl);
461*4882a593Smuzhiyun 	spin_unlock(&chip->reg_lock);
462*4882a593Smuzhiyun 	return 0;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun 
snd_fm801_playback_prepare(struct snd_pcm_substream * substream)465*4882a593Smuzhiyun static int snd_fm801_playback_prepare(struct snd_pcm_substream *substream)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun 	struct fm801 *chip = snd_pcm_substream_chip(substream);
468*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	chip->ply_size = snd_pcm_lib_buffer_bytes(substream);
471*4882a593Smuzhiyun 	chip->ply_count = snd_pcm_lib_period_bytes(substream);
472*4882a593Smuzhiyun 	spin_lock_irq(&chip->reg_lock);
473*4882a593Smuzhiyun 	chip->ply_ctrl &= ~(FM801_START | FM801_16BIT |
474*4882a593Smuzhiyun 			     FM801_STEREO | FM801_RATE_MASK |
475*4882a593Smuzhiyun 			     FM801_CHANNELS_MASK);
476*4882a593Smuzhiyun 	if (snd_pcm_format_width(runtime->format) == 16)
477*4882a593Smuzhiyun 		chip->ply_ctrl |= FM801_16BIT;
478*4882a593Smuzhiyun 	if (runtime->channels > 1) {
479*4882a593Smuzhiyun 		chip->ply_ctrl |= FM801_STEREO;
480*4882a593Smuzhiyun 		if (runtime->channels == 4)
481*4882a593Smuzhiyun 			chip->ply_ctrl |= FM801_CHANNELS_4;
482*4882a593Smuzhiyun 		else if (runtime->channels == 6)
483*4882a593Smuzhiyun 			chip->ply_ctrl |= FM801_CHANNELS_6;
484*4882a593Smuzhiyun 	}
485*4882a593Smuzhiyun 	chip->ply_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
486*4882a593Smuzhiyun 	chip->ply_buf = 0;
487*4882a593Smuzhiyun 	fm801_writew(chip, PLY_CTRL, chip->ply_ctrl);
488*4882a593Smuzhiyun 	fm801_writew(chip, PLY_COUNT, chip->ply_count - 1);
489*4882a593Smuzhiyun 	chip->ply_buffer = runtime->dma_addr;
490*4882a593Smuzhiyun 	chip->ply_pos = 0;
491*4882a593Smuzhiyun 	fm801_writel(chip, PLY_BUF1, chip->ply_buffer);
492*4882a593Smuzhiyun 	fm801_writel(chip, PLY_BUF2,
493*4882a593Smuzhiyun 		     chip->ply_buffer + (chip->ply_count % chip->ply_size));
494*4882a593Smuzhiyun 	spin_unlock_irq(&chip->reg_lock);
495*4882a593Smuzhiyun 	return 0;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun 
snd_fm801_capture_prepare(struct snd_pcm_substream * substream)498*4882a593Smuzhiyun static int snd_fm801_capture_prepare(struct snd_pcm_substream *substream)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun 	struct fm801 *chip = snd_pcm_substream_chip(substream);
501*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	chip->cap_size = snd_pcm_lib_buffer_bytes(substream);
504*4882a593Smuzhiyun 	chip->cap_count = snd_pcm_lib_period_bytes(substream);
505*4882a593Smuzhiyun 	spin_lock_irq(&chip->reg_lock);
506*4882a593Smuzhiyun 	chip->cap_ctrl &= ~(FM801_START | FM801_16BIT |
507*4882a593Smuzhiyun 			     FM801_STEREO | FM801_RATE_MASK);
508*4882a593Smuzhiyun 	if (snd_pcm_format_width(runtime->format) == 16)
509*4882a593Smuzhiyun 		chip->cap_ctrl |= FM801_16BIT;
510*4882a593Smuzhiyun 	if (runtime->channels > 1)
511*4882a593Smuzhiyun 		chip->cap_ctrl |= FM801_STEREO;
512*4882a593Smuzhiyun 	chip->cap_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
513*4882a593Smuzhiyun 	chip->cap_buf = 0;
514*4882a593Smuzhiyun 	fm801_writew(chip, CAP_CTRL, chip->cap_ctrl);
515*4882a593Smuzhiyun 	fm801_writew(chip, CAP_COUNT, chip->cap_count - 1);
516*4882a593Smuzhiyun 	chip->cap_buffer = runtime->dma_addr;
517*4882a593Smuzhiyun 	chip->cap_pos = 0;
518*4882a593Smuzhiyun 	fm801_writel(chip, CAP_BUF1, chip->cap_buffer);
519*4882a593Smuzhiyun 	fm801_writel(chip, CAP_BUF2,
520*4882a593Smuzhiyun 		     chip->cap_buffer + (chip->cap_count % chip->cap_size));
521*4882a593Smuzhiyun 	spin_unlock_irq(&chip->reg_lock);
522*4882a593Smuzhiyun 	return 0;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun 
snd_fm801_playback_pointer(struct snd_pcm_substream * substream)525*4882a593Smuzhiyun static snd_pcm_uframes_t snd_fm801_playback_pointer(struct snd_pcm_substream *substream)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun 	struct fm801 *chip = snd_pcm_substream_chip(substream);
528*4882a593Smuzhiyun 	size_t ptr;
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	if (!(chip->ply_ctrl & FM801_START))
531*4882a593Smuzhiyun 		return 0;
532*4882a593Smuzhiyun 	spin_lock(&chip->reg_lock);
533*4882a593Smuzhiyun 	ptr = chip->ply_pos + (chip->ply_count - 1) - fm801_readw(chip, PLY_COUNT);
534*4882a593Smuzhiyun 	if (fm801_readw(chip, IRQ_STATUS) & FM801_IRQ_PLAYBACK) {
535*4882a593Smuzhiyun 		ptr += chip->ply_count;
536*4882a593Smuzhiyun 		ptr %= chip->ply_size;
537*4882a593Smuzhiyun 	}
538*4882a593Smuzhiyun 	spin_unlock(&chip->reg_lock);
539*4882a593Smuzhiyun 	return bytes_to_frames(substream->runtime, ptr);
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun 
snd_fm801_capture_pointer(struct snd_pcm_substream * substream)542*4882a593Smuzhiyun static snd_pcm_uframes_t snd_fm801_capture_pointer(struct snd_pcm_substream *substream)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun 	struct fm801 *chip = snd_pcm_substream_chip(substream);
545*4882a593Smuzhiyun 	size_t ptr;
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 	if (!(chip->cap_ctrl & FM801_START))
548*4882a593Smuzhiyun 		return 0;
549*4882a593Smuzhiyun 	spin_lock(&chip->reg_lock);
550*4882a593Smuzhiyun 	ptr = chip->cap_pos + (chip->cap_count - 1) - fm801_readw(chip, CAP_COUNT);
551*4882a593Smuzhiyun 	if (fm801_readw(chip, IRQ_STATUS) & FM801_IRQ_CAPTURE) {
552*4882a593Smuzhiyun 		ptr += chip->cap_count;
553*4882a593Smuzhiyun 		ptr %= chip->cap_size;
554*4882a593Smuzhiyun 	}
555*4882a593Smuzhiyun 	spin_unlock(&chip->reg_lock);
556*4882a593Smuzhiyun 	return bytes_to_frames(substream->runtime, ptr);
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun 
snd_fm801_interrupt(int irq,void * dev_id)559*4882a593Smuzhiyun static irqreturn_t snd_fm801_interrupt(int irq, void *dev_id)
560*4882a593Smuzhiyun {
561*4882a593Smuzhiyun 	struct fm801 *chip = dev_id;
562*4882a593Smuzhiyun 	unsigned short status;
563*4882a593Smuzhiyun 	unsigned int tmp;
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun 	status = fm801_readw(chip, IRQ_STATUS);
566*4882a593Smuzhiyun 	status &= FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU|FM801_IRQ_VOLUME;
567*4882a593Smuzhiyun 	if (! status)
568*4882a593Smuzhiyun 		return IRQ_NONE;
569*4882a593Smuzhiyun 	/* ack first */
570*4882a593Smuzhiyun 	fm801_writew(chip, IRQ_STATUS, status);
571*4882a593Smuzhiyun 	if (chip->pcm && (status & FM801_IRQ_PLAYBACK) && chip->playback_substream) {
572*4882a593Smuzhiyun 		spin_lock(&chip->reg_lock);
573*4882a593Smuzhiyun 		chip->ply_buf++;
574*4882a593Smuzhiyun 		chip->ply_pos += chip->ply_count;
575*4882a593Smuzhiyun 		chip->ply_pos %= chip->ply_size;
576*4882a593Smuzhiyun 		tmp = chip->ply_pos + chip->ply_count;
577*4882a593Smuzhiyun 		tmp %= chip->ply_size;
578*4882a593Smuzhiyun 		if (chip->ply_buf & 1)
579*4882a593Smuzhiyun 			fm801_writel(chip, PLY_BUF1, chip->ply_buffer + tmp);
580*4882a593Smuzhiyun 		else
581*4882a593Smuzhiyun 			fm801_writel(chip, PLY_BUF2, chip->ply_buffer + tmp);
582*4882a593Smuzhiyun 		spin_unlock(&chip->reg_lock);
583*4882a593Smuzhiyun 		snd_pcm_period_elapsed(chip->playback_substream);
584*4882a593Smuzhiyun 	}
585*4882a593Smuzhiyun 	if (chip->pcm && (status & FM801_IRQ_CAPTURE) && chip->capture_substream) {
586*4882a593Smuzhiyun 		spin_lock(&chip->reg_lock);
587*4882a593Smuzhiyun 		chip->cap_buf++;
588*4882a593Smuzhiyun 		chip->cap_pos += chip->cap_count;
589*4882a593Smuzhiyun 		chip->cap_pos %= chip->cap_size;
590*4882a593Smuzhiyun 		tmp = chip->cap_pos + chip->cap_count;
591*4882a593Smuzhiyun 		tmp %= chip->cap_size;
592*4882a593Smuzhiyun 		if (chip->cap_buf & 1)
593*4882a593Smuzhiyun 			fm801_writel(chip, CAP_BUF1, chip->cap_buffer + tmp);
594*4882a593Smuzhiyun 		else
595*4882a593Smuzhiyun 			fm801_writel(chip, CAP_BUF2, chip->cap_buffer + tmp);
596*4882a593Smuzhiyun 		spin_unlock(&chip->reg_lock);
597*4882a593Smuzhiyun 		snd_pcm_period_elapsed(chip->capture_substream);
598*4882a593Smuzhiyun 	}
599*4882a593Smuzhiyun 	if (chip->rmidi && (status & FM801_IRQ_MPU))
600*4882a593Smuzhiyun 		snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
601*4882a593Smuzhiyun 	if (status & FM801_IRQ_VOLUME) {
602*4882a593Smuzhiyun 		/* TODO */
603*4882a593Smuzhiyun 	}
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun 	return IRQ_HANDLED;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_fm801_playback =
609*4882a593Smuzhiyun {
610*4882a593Smuzhiyun 	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
611*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
612*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
613*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_MMAP_VALID),
614*4882a593Smuzhiyun 	.formats =		SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
615*4882a593Smuzhiyun 	.rates =		SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
616*4882a593Smuzhiyun 	.rate_min =		5500,
617*4882a593Smuzhiyun 	.rate_max =		48000,
618*4882a593Smuzhiyun 	.channels_min =		1,
619*4882a593Smuzhiyun 	.channels_max =		2,
620*4882a593Smuzhiyun 	.buffer_bytes_max =	(128*1024),
621*4882a593Smuzhiyun 	.period_bytes_min =	64,
622*4882a593Smuzhiyun 	.period_bytes_max =	(128*1024),
623*4882a593Smuzhiyun 	.periods_min =		1,
624*4882a593Smuzhiyun 	.periods_max =		1024,
625*4882a593Smuzhiyun 	.fifo_size =		0,
626*4882a593Smuzhiyun };
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_fm801_capture =
629*4882a593Smuzhiyun {
630*4882a593Smuzhiyun 	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
631*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
632*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
633*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_MMAP_VALID),
634*4882a593Smuzhiyun 	.formats =		SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
635*4882a593Smuzhiyun 	.rates =		SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
636*4882a593Smuzhiyun 	.rate_min =		5500,
637*4882a593Smuzhiyun 	.rate_max =		48000,
638*4882a593Smuzhiyun 	.channels_min =		1,
639*4882a593Smuzhiyun 	.channels_max =		2,
640*4882a593Smuzhiyun 	.buffer_bytes_max =	(128*1024),
641*4882a593Smuzhiyun 	.period_bytes_min =	64,
642*4882a593Smuzhiyun 	.period_bytes_max =	(128*1024),
643*4882a593Smuzhiyun 	.periods_min =		1,
644*4882a593Smuzhiyun 	.periods_max =		1024,
645*4882a593Smuzhiyun 	.fifo_size =		0,
646*4882a593Smuzhiyun };
647*4882a593Smuzhiyun 
snd_fm801_playback_open(struct snd_pcm_substream * substream)648*4882a593Smuzhiyun static int snd_fm801_playback_open(struct snd_pcm_substream *substream)
649*4882a593Smuzhiyun {
650*4882a593Smuzhiyun 	struct fm801 *chip = snd_pcm_substream_chip(substream);
651*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
652*4882a593Smuzhiyun 	int err;
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	chip->playback_substream = substream;
655*4882a593Smuzhiyun 	runtime->hw = snd_fm801_playback;
656*4882a593Smuzhiyun 	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
657*4882a593Smuzhiyun 				   &hw_constraints_rates);
658*4882a593Smuzhiyun 	if (chip->multichannel) {
659*4882a593Smuzhiyun 		runtime->hw.channels_max = 6;
660*4882a593Smuzhiyun 		snd_pcm_hw_constraint_list(runtime, 0,
661*4882a593Smuzhiyun 					   SNDRV_PCM_HW_PARAM_CHANNELS,
662*4882a593Smuzhiyun 					   &hw_constraints_channels);
663*4882a593Smuzhiyun 	}
664*4882a593Smuzhiyun 	if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
665*4882a593Smuzhiyun 		return err;
666*4882a593Smuzhiyun 	return 0;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun 
snd_fm801_capture_open(struct snd_pcm_substream * substream)669*4882a593Smuzhiyun static int snd_fm801_capture_open(struct snd_pcm_substream *substream)
670*4882a593Smuzhiyun {
671*4882a593Smuzhiyun 	struct fm801 *chip = snd_pcm_substream_chip(substream);
672*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
673*4882a593Smuzhiyun 	int err;
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	chip->capture_substream = substream;
676*4882a593Smuzhiyun 	runtime->hw = snd_fm801_capture;
677*4882a593Smuzhiyun 	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
678*4882a593Smuzhiyun 				   &hw_constraints_rates);
679*4882a593Smuzhiyun 	if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
680*4882a593Smuzhiyun 		return err;
681*4882a593Smuzhiyun 	return 0;
682*4882a593Smuzhiyun }
683*4882a593Smuzhiyun 
snd_fm801_playback_close(struct snd_pcm_substream * substream)684*4882a593Smuzhiyun static int snd_fm801_playback_close(struct snd_pcm_substream *substream)
685*4882a593Smuzhiyun {
686*4882a593Smuzhiyun 	struct fm801 *chip = snd_pcm_substream_chip(substream);
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	chip->playback_substream = NULL;
689*4882a593Smuzhiyun 	return 0;
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun 
snd_fm801_capture_close(struct snd_pcm_substream * substream)692*4882a593Smuzhiyun static int snd_fm801_capture_close(struct snd_pcm_substream *substream)
693*4882a593Smuzhiyun {
694*4882a593Smuzhiyun 	struct fm801 *chip = snd_pcm_substream_chip(substream);
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 	chip->capture_substream = NULL;
697*4882a593Smuzhiyun 	return 0;
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun static const struct snd_pcm_ops snd_fm801_playback_ops = {
701*4882a593Smuzhiyun 	.open =		snd_fm801_playback_open,
702*4882a593Smuzhiyun 	.close =	snd_fm801_playback_close,
703*4882a593Smuzhiyun 	.prepare =	snd_fm801_playback_prepare,
704*4882a593Smuzhiyun 	.trigger =	snd_fm801_playback_trigger,
705*4882a593Smuzhiyun 	.pointer =	snd_fm801_playback_pointer,
706*4882a593Smuzhiyun };
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun static const struct snd_pcm_ops snd_fm801_capture_ops = {
709*4882a593Smuzhiyun 	.open =		snd_fm801_capture_open,
710*4882a593Smuzhiyun 	.close =	snd_fm801_capture_close,
711*4882a593Smuzhiyun 	.prepare =	snd_fm801_capture_prepare,
712*4882a593Smuzhiyun 	.trigger =	snd_fm801_capture_trigger,
713*4882a593Smuzhiyun 	.pointer =	snd_fm801_capture_pointer,
714*4882a593Smuzhiyun };
715*4882a593Smuzhiyun 
snd_fm801_pcm(struct fm801 * chip,int device)716*4882a593Smuzhiyun static int snd_fm801_pcm(struct fm801 *chip, int device)
717*4882a593Smuzhiyun {
718*4882a593Smuzhiyun 	struct pci_dev *pdev = to_pci_dev(chip->dev);
719*4882a593Smuzhiyun 	struct snd_pcm *pcm;
720*4882a593Smuzhiyun 	int err;
721*4882a593Smuzhiyun 
722*4882a593Smuzhiyun 	if ((err = snd_pcm_new(chip->card, "FM801", device, 1, 1, &pcm)) < 0)
723*4882a593Smuzhiyun 		return err;
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_fm801_playback_ops);
726*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_fm801_capture_ops);
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	pcm->private_data = chip;
729*4882a593Smuzhiyun 	pcm->info_flags = 0;
730*4882a593Smuzhiyun 	strcpy(pcm->name, "FM801");
731*4882a593Smuzhiyun 	chip->pcm = pcm;
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &pdev->dev,
734*4882a593Smuzhiyun 				       chip->multichannel ? 128*1024 : 64*1024, 128*1024);
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun 	return snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
737*4882a593Smuzhiyun 				     snd_pcm_alt_chmaps,
738*4882a593Smuzhiyun 				     chip->multichannel ? 6 : 2, 0,
739*4882a593Smuzhiyun 				     NULL);
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun /*
743*4882a593Smuzhiyun  *  TEA5757 radio
744*4882a593Smuzhiyun  */
745*4882a593Smuzhiyun 
746*4882a593Smuzhiyun #ifdef CONFIG_SND_FM801_TEA575X_BOOL
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun /* GPIO to TEA575x maps */
749*4882a593Smuzhiyun struct snd_fm801_tea575x_gpio {
750*4882a593Smuzhiyun 	u8 data, clk, wren, most;
751*4882a593Smuzhiyun 	char *name;
752*4882a593Smuzhiyun };
753*4882a593Smuzhiyun 
754*4882a593Smuzhiyun static const struct snd_fm801_tea575x_gpio snd_fm801_tea575x_gpios[] = {
755*4882a593Smuzhiyun 	{ .data = 1, .clk = 3, .wren = 2, .most = 0, .name = "SF256-PCS" },
756*4882a593Smuzhiyun 	{ .data = 1, .clk = 0, .wren = 2, .most = 3, .name = "SF256-PCP" },
757*4882a593Smuzhiyun 	{ .data = 2, .clk = 0, .wren = 1, .most = 3, .name = "SF64-PCR" },
758*4882a593Smuzhiyun };
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun #define get_tea575x_gpio(chip) \
761*4882a593Smuzhiyun 	(&snd_fm801_tea575x_gpios[((chip)->tea575x_tuner & TUNER_TYPE_MASK) - 1])
762*4882a593Smuzhiyun 
snd_fm801_tea575x_set_pins(struct snd_tea575x * tea,u8 pins)763*4882a593Smuzhiyun static void snd_fm801_tea575x_set_pins(struct snd_tea575x *tea, u8 pins)
764*4882a593Smuzhiyun {
765*4882a593Smuzhiyun 	struct fm801 *chip = tea->private_data;
766*4882a593Smuzhiyun 	unsigned short reg = fm801_readw(chip, GPIO_CTRL);
767*4882a593Smuzhiyun 	struct snd_fm801_tea575x_gpio gpio = *get_tea575x_gpio(chip);
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun 	reg &= ~(FM801_GPIO_GP(gpio.data) |
770*4882a593Smuzhiyun 		 FM801_GPIO_GP(gpio.clk) |
771*4882a593Smuzhiyun 		 FM801_GPIO_GP(gpio.wren));
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	reg |= (pins & TEA575X_DATA) ? FM801_GPIO_GP(gpio.data) : 0;
774*4882a593Smuzhiyun 	reg |= (pins & TEA575X_CLK)  ? FM801_GPIO_GP(gpio.clk) : 0;
775*4882a593Smuzhiyun 	/* WRITE_ENABLE is inverted */
776*4882a593Smuzhiyun 	reg |= (pins & TEA575X_WREN) ? 0 : FM801_GPIO_GP(gpio.wren);
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun 	fm801_writew(chip, GPIO_CTRL, reg);
779*4882a593Smuzhiyun }
780*4882a593Smuzhiyun 
snd_fm801_tea575x_get_pins(struct snd_tea575x * tea)781*4882a593Smuzhiyun static u8 snd_fm801_tea575x_get_pins(struct snd_tea575x *tea)
782*4882a593Smuzhiyun {
783*4882a593Smuzhiyun 	struct fm801 *chip = tea->private_data;
784*4882a593Smuzhiyun 	unsigned short reg = fm801_readw(chip, GPIO_CTRL);
785*4882a593Smuzhiyun 	struct snd_fm801_tea575x_gpio gpio = *get_tea575x_gpio(chip);
786*4882a593Smuzhiyun 	u8 ret;
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun 	ret = 0;
789*4882a593Smuzhiyun 	if (reg & FM801_GPIO_GP(gpio.data))
790*4882a593Smuzhiyun 		ret |= TEA575X_DATA;
791*4882a593Smuzhiyun 	if (reg & FM801_GPIO_GP(gpio.most))
792*4882a593Smuzhiyun 		ret |= TEA575X_MOST;
793*4882a593Smuzhiyun 	return ret;
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun 
snd_fm801_tea575x_set_direction(struct snd_tea575x * tea,bool output)796*4882a593Smuzhiyun static void snd_fm801_tea575x_set_direction(struct snd_tea575x *tea, bool output)
797*4882a593Smuzhiyun {
798*4882a593Smuzhiyun 	struct fm801 *chip = tea->private_data;
799*4882a593Smuzhiyun 	unsigned short reg = fm801_readw(chip, GPIO_CTRL);
800*4882a593Smuzhiyun 	struct snd_fm801_tea575x_gpio gpio = *get_tea575x_gpio(chip);
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 	/* use GPIO lines and set write enable bit */
803*4882a593Smuzhiyun 	reg |= FM801_GPIO_GS(gpio.data) |
804*4882a593Smuzhiyun 	       FM801_GPIO_GS(gpio.wren) |
805*4882a593Smuzhiyun 	       FM801_GPIO_GS(gpio.clk) |
806*4882a593Smuzhiyun 	       FM801_GPIO_GS(gpio.most);
807*4882a593Smuzhiyun 	if (output) {
808*4882a593Smuzhiyun 		/* all of lines are in the write direction */
809*4882a593Smuzhiyun 		/* clear data and clock lines */
810*4882a593Smuzhiyun 		reg &= ~(FM801_GPIO_GD(gpio.data) |
811*4882a593Smuzhiyun 			 FM801_GPIO_GD(gpio.wren) |
812*4882a593Smuzhiyun 			 FM801_GPIO_GD(gpio.clk) |
813*4882a593Smuzhiyun 			 FM801_GPIO_GP(gpio.data) |
814*4882a593Smuzhiyun 			 FM801_GPIO_GP(gpio.clk) |
815*4882a593Smuzhiyun 			 FM801_GPIO_GP(gpio.wren));
816*4882a593Smuzhiyun 	} else {
817*4882a593Smuzhiyun 		/* use GPIO lines, set data direction to input */
818*4882a593Smuzhiyun 		reg |= FM801_GPIO_GD(gpio.data) |
819*4882a593Smuzhiyun 		       FM801_GPIO_GD(gpio.most) |
820*4882a593Smuzhiyun 		       FM801_GPIO_GP(gpio.data) |
821*4882a593Smuzhiyun 		       FM801_GPIO_GP(gpio.most) |
822*4882a593Smuzhiyun 		       FM801_GPIO_GP(gpio.wren);
823*4882a593Smuzhiyun 		/* all of lines are in the write direction, except data */
824*4882a593Smuzhiyun 		/* clear data, write enable and clock lines */
825*4882a593Smuzhiyun 		reg &= ~(FM801_GPIO_GD(gpio.wren) |
826*4882a593Smuzhiyun 			 FM801_GPIO_GD(gpio.clk) |
827*4882a593Smuzhiyun 			 FM801_GPIO_GP(gpio.clk));
828*4882a593Smuzhiyun 	}
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun 	fm801_writew(chip, GPIO_CTRL, reg);
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun static const struct snd_tea575x_ops snd_fm801_tea_ops = {
834*4882a593Smuzhiyun 	.set_pins = snd_fm801_tea575x_set_pins,
835*4882a593Smuzhiyun 	.get_pins = snd_fm801_tea575x_get_pins,
836*4882a593Smuzhiyun 	.set_direction = snd_fm801_tea575x_set_direction,
837*4882a593Smuzhiyun };
838*4882a593Smuzhiyun #endif
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun /*
841*4882a593Smuzhiyun  *  Mixer routines
842*4882a593Smuzhiyun  */
843*4882a593Smuzhiyun 
844*4882a593Smuzhiyun #define FM801_SINGLE(xname, reg, shift, mask, invert) \
845*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_single, \
846*4882a593Smuzhiyun   .get = snd_fm801_get_single, .put = snd_fm801_put_single, \
847*4882a593Smuzhiyun   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
848*4882a593Smuzhiyun 
snd_fm801_info_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)849*4882a593Smuzhiyun static int snd_fm801_info_single(struct snd_kcontrol *kcontrol,
850*4882a593Smuzhiyun 				 struct snd_ctl_elem_info *uinfo)
851*4882a593Smuzhiyun {
852*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
853*4882a593Smuzhiyun 
854*4882a593Smuzhiyun 	uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
855*4882a593Smuzhiyun 	uinfo->count = 1;
856*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
857*4882a593Smuzhiyun 	uinfo->value.integer.max = mask;
858*4882a593Smuzhiyun 	return 0;
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun 
snd_fm801_get_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)861*4882a593Smuzhiyun static int snd_fm801_get_single(struct snd_kcontrol *kcontrol,
862*4882a593Smuzhiyun 				struct snd_ctl_elem_value *ucontrol)
863*4882a593Smuzhiyun {
864*4882a593Smuzhiyun 	struct fm801 *chip = snd_kcontrol_chip(kcontrol);
865*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
866*4882a593Smuzhiyun 	int shift = (kcontrol->private_value >> 8) & 0xff;
867*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
868*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
869*4882a593Smuzhiyun 	long *value = ucontrol->value.integer.value;
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun 	value[0] = (fm801_ioread16(chip, reg) >> shift) & mask;
872*4882a593Smuzhiyun 	if (invert)
873*4882a593Smuzhiyun 		value[0] = mask - value[0];
874*4882a593Smuzhiyun 	return 0;
875*4882a593Smuzhiyun }
876*4882a593Smuzhiyun 
snd_fm801_put_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)877*4882a593Smuzhiyun static int snd_fm801_put_single(struct snd_kcontrol *kcontrol,
878*4882a593Smuzhiyun 				struct snd_ctl_elem_value *ucontrol)
879*4882a593Smuzhiyun {
880*4882a593Smuzhiyun 	struct fm801 *chip = snd_kcontrol_chip(kcontrol);
881*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
882*4882a593Smuzhiyun 	int shift = (kcontrol->private_value >> 8) & 0xff;
883*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
884*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
885*4882a593Smuzhiyun 	unsigned short val;
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun 	val = (ucontrol->value.integer.value[0] & mask);
888*4882a593Smuzhiyun 	if (invert)
889*4882a593Smuzhiyun 		val = mask - val;
890*4882a593Smuzhiyun 	return snd_fm801_update_bits(chip, reg, mask << shift, val << shift);
891*4882a593Smuzhiyun }
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun #define FM801_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \
894*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_double, \
895*4882a593Smuzhiyun   .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
896*4882a593Smuzhiyun   .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) }
897*4882a593Smuzhiyun #define FM801_DOUBLE_TLV(xname, reg, shift_left, shift_right, mask, invert, xtlv) \
898*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
899*4882a593Smuzhiyun   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
900*4882a593Smuzhiyun   .name = xname, .info = snd_fm801_info_double, \
901*4882a593Smuzhiyun   .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
902*4882a593Smuzhiyun   .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24), \
903*4882a593Smuzhiyun   .tlv = { .p = (xtlv) } }
904*4882a593Smuzhiyun 
snd_fm801_info_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)905*4882a593Smuzhiyun static int snd_fm801_info_double(struct snd_kcontrol *kcontrol,
906*4882a593Smuzhiyun 				 struct snd_ctl_elem_info *uinfo)
907*4882a593Smuzhiyun {
908*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun 	uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
911*4882a593Smuzhiyun 	uinfo->count = 2;
912*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
913*4882a593Smuzhiyun 	uinfo->value.integer.max = mask;
914*4882a593Smuzhiyun 	return 0;
915*4882a593Smuzhiyun }
916*4882a593Smuzhiyun 
snd_fm801_get_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)917*4882a593Smuzhiyun static int snd_fm801_get_double(struct snd_kcontrol *kcontrol,
918*4882a593Smuzhiyun 				struct snd_ctl_elem_value *ucontrol)
919*4882a593Smuzhiyun {
920*4882a593Smuzhiyun 	struct fm801 *chip = snd_kcontrol_chip(kcontrol);
921*4882a593Smuzhiyun         int reg = kcontrol->private_value & 0xff;
922*4882a593Smuzhiyun 	int shift_left = (kcontrol->private_value >> 8) & 0x0f;
923*4882a593Smuzhiyun 	int shift_right = (kcontrol->private_value >> 12) & 0x0f;
924*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
925*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
926*4882a593Smuzhiyun 	long *value = ucontrol->value.integer.value;
927*4882a593Smuzhiyun 
928*4882a593Smuzhiyun 	spin_lock_irq(&chip->reg_lock);
929*4882a593Smuzhiyun 	value[0] = (fm801_ioread16(chip, reg) >> shift_left) & mask;
930*4882a593Smuzhiyun 	value[1] = (fm801_ioread16(chip, reg) >> shift_right) & mask;
931*4882a593Smuzhiyun 	spin_unlock_irq(&chip->reg_lock);
932*4882a593Smuzhiyun 	if (invert) {
933*4882a593Smuzhiyun 		value[0] = mask - value[0];
934*4882a593Smuzhiyun 		value[1] = mask - value[1];
935*4882a593Smuzhiyun 	}
936*4882a593Smuzhiyun 	return 0;
937*4882a593Smuzhiyun }
938*4882a593Smuzhiyun 
snd_fm801_put_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)939*4882a593Smuzhiyun static int snd_fm801_put_double(struct snd_kcontrol *kcontrol,
940*4882a593Smuzhiyun 				struct snd_ctl_elem_value *ucontrol)
941*4882a593Smuzhiyun {
942*4882a593Smuzhiyun 	struct fm801 *chip = snd_kcontrol_chip(kcontrol);
943*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
944*4882a593Smuzhiyun 	int shift_left = (kcontrol->private_value >> 8) & 0x0f;
945*4882a593Smuzhiyun 	int shift_right = (kcontrol->private_value >> 12) & 0x0f;
946*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
947*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
948*4882a593Smuzhiyun 	unsigned short val1, val2;
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun 	val1 = ucontrol->value.integer.value[0] & mask;
951*4882a593Smuzhiyun 	val2 = ucontrol->value.integer.value[1] & mask;
952*4882a593Smuzhiyun 	if (invert) {
953*4882a593Smuzhiyun 		val1 = mask - val1;
954*4882a593Smuzhiyun 		val2 = mask - val2;
955*4882a593Smuzhiyun 	}
956*4882a593Smuzhiyun 	return snd_fm801_update_bits(chip, reg,
957*4882a593Smuzhiyun 				     (mask << shift_left) | (mask << shift_right),
958*4882a593Smuzhiyun 				     (val1 << shift_left ) | (val2 << shift_right));
959*4882a593Smuzhiyun }
960*4882a593Smuzhiyun 
snd_fm801_info_mux(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)961*4882a593Smuzhiyun static int snd_fm801_info_mux(struct snd_kcontrol *kcontrol,
962*4882a593Smuzhiyun 			      struct snd_ctl_elem_info *uinfo)
963*4882a593Smuzhiyun {
964*4882a593Smuzhiyun 	static const char * const texts[5] = {
965*4882a593Smuzhiyun 		"AC97 Primary", "FM", "I2S", "PCM", "AC97 Secondary"
966*4882a593Smuzhiyun 	};
967*4882a593Smuzhiyun 
968*4882a593Smuzhiyun 	return snd_ctl_enum_info(uinfo, 1, 5, texts);
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun 
snd_fm801_get_mux(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)971*4882a593Smuzhiyun static int snd_fm801_get_mux(struct snd_kcontrol *kcontrol,
972*4882a593Smuzhiyun 			     struct snd_ctl_elem_value *ucontrol)
973*4882a593Smuzhiyun {
974*4882a593Smuzhiyun 	struct fm801 *chip = snd_kcontrol_chip(kcontrol);
975*4882a593Smuzhiyun         unsigned short val;
976*4882a593Smuzhiyun 
977*4882a593Smuzhiyun 	val = fm801_readw(chip, REC_SRC) & 7;
978*4882a593Smuzhiyun 	if (val > 4)
979*4882a593Smuzhiyun 		val = 4;
980*4882a593Smuzhiyun         ucontrol->value.enumerated.item[0] = val;
981*4882a593Smuzhiyun         return 0;
982*4882a593Smuzhiyun }
983*4882a593Smuzhiyun 
snd_fm801_put_mux(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)984*4882a593Smuzhiyun static int snd_fm801_put_mux(struct snd_kcontrol *kcontrol,
985*4882a593Smuzhiyun 			     struct snd_ctl_elem_value *ucontrol)
986*4882a593Smuzhiyun {
987*4882a593Smuzhiyun 	struct fm801 *chip = snd_kcontrol_chip(kcontrol);
988*4882a593Smuzhiyun         unsigned short val;
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun         if ((val = ucontrol->value.enumerated.item[0]) > 4)
991*4882a593Smuzhiyun                 return -EINVAL;
992*4882a593Smuzhiyun 	return snd_fm801_update_bits(chip, FM801_REC_SRC, 7, val);
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -3450, 150, 0);
996*4882a593Smuzhiyun 
997*4882a593Smuzhiyun #define FM801_CONTROLS ARRAY_SIZE(snd_fm801_controls)
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_fm801_controls[] = {
1000*4882a593Smuzhiyun FM801_DOUBLE_TLV("Wave Playback Volume", FM801_PCM_VOL, 0, 8, 31, 1,
1001*4882a593Smuzhiyun 		 db_scale_dsp),
1002*4882a593Smuzhiyun FM801_SINGLE("Wave Playback Switch", FM801_PCM_VOL, 15, 1, 1),
1003*4882a593Smuzhiyun FM801_DOUBLE_TLV("I2S Playback Volume", FM801_I2S_VOL, 0, 8, 31, 1,
1004*4882a593Smuzhiyun 		 db_scale_dsp),
1005*4882a593Smuzhiyun FM801_SINGLE("I2S Playback Switch", FM801_I2S_VOL, 15, 1, 1),
1006*4882a593Smuzhiyun FM801_DOUBLE_TLV("FM Playback Volume", FM801_FM_VOL, 0, 8, 31, 1,
1007*4882a593Smuzhiyun 		 db_scale_dsp),
1008*4882a593Smuzhiyun FM801_SINGLE("FM Playback Switch", FM801_FM_VOL, 15, 1, 1),
1009*4882a593Smuzhiyun {
1010*4882a593Smuzhiyun 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1011*4882a593Smuzhiyun 	.name = "Digital Capture Source",
1012*4882a593Smuzhiyun 	.info = snd_fm801_info_mux,
1013*4882a593Smuzhiyun 	.get = snd_fm801_get_mux,
1014*4882a593Smuzhiyun 	.put = snd_fm801_put_mux,
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun };
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun #define FM801_CONTROLS_MULTI ARRAY_SIZE(snd_fm801_controls_multi)
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_fm801_controls_multi[] = {
1021*4882a593Smuzhiyun FM801_SINGLE("AC97 2ch->4ch Copy Switch", FM801_CODEC_CTRL, 7, 1, 0),
1022*4882a593Smuzhiyun FM801_SINGLE("AC97 18-bit Switch", FM801_CODEC_CTRL, 10, 1, 0),
1023*4882a593Smuzhiyun FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), FM801_I2S_MODE, 8, 1, 0),
1024*4882a593Smuzhiyun FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",PLAYBACK,SWITCH), FM801_I2S_MODE, 9, 1, 0),
1025*4882a593Smuzhiyun FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",CAPTURE,SWITCH), FM801_I2S_MODE, 10, 1, 0),
1026*4882a593Smuzhiyun FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), FM801_GEN_CTRL, 2, 1, 0),
1027*4882a593Smuzhiyun };
1028*4882a593Smuzhiyun 
snd_fm801_mixer_free_ac97_bus(struct snd_ac97_bus * bus)1029*4882a593Smuzhiyun static void snd_fm801_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1030*4882a593Smuzhiyun {
1031*4882a593Smuzhiyun 	struct fm801 *chip = bus->private_data;
1032*4882a593Smuzhiyun 	chip->ac97_bus = NULL;
1033*4882a593Smuzhiyun }
1034*4882a593Smuzhiyun 
snd_fm801_mixer_free_ac97(struct snd_ac97 * ac97)1035*4882a593Smuzhiyun static void snd_fm801_mixer_free_ac97(struct snd_ac97 *ac97)
1036*4882a593Smuzhiyun {
1037*4882a593Smuzhiyun 	struct fm801 *chip = ac97->private_data;
1038*4882a593Smuzhiyun 	if (ac97->num == 0) {
1039*4882a593Smuzhiyun 		chip->ac97 = NULL;
1040*4882a593Smuzhiyun 	} else {
1041*4882a593Smuzhiyun 		chip->ac97_sec = NULL;
1042*4882a593Smuzhiyun 	}
1043*4882a593Smuzhiyun }
1044*4882a593Smuzhiyun 
snd_fm801_mixer(struct fm801 * chip)1045*4882a593Smuzhiyun static int snd_fm801_mixer(struct fm801 *chip)
1046*4882a593Smuzhiyun {
1047*4882a593Smuzhiyun 	struct snd_ac97_template ac97;
1048*4882a593Smuzhiyun 	unsigned int i;
1049*4882a593Smuzhiyun 	int err;
1050*4882a593Smuzhiyun 	static const struct snd_ac97_bus_ops ops = {
1051*4882a593Smuzhiyun 		.write = snd_fm801_codec_write,
1052*4882a593Smuzhiyun 		.read = snd_fm801_codec_read,
1053*4882a593Smuzhiyun 	};
1054*4882a593Smuzhiyun 
1055*4882a593Smuzhiyun 	if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1056*4882a593Smuzhiyun 		return err;
1057*4882a593Smuzhiyun 	chip->ac97_bus->private_free = snd_fm801_mixer_free_ac97_bus;
1058*4882a593Smuzhiyun 
1059*4882a593Smuzhiyun 	memset(&ac97, 0, sizeof(ac97));
1060*4882a593Smuzhiyun 	ac97.private_data = chip;
1061*4882a593Smuzhiyun 	ac97.private_free = snd_fm801_mixer_free_ac97;
1062*4882a593Smuzhiyun 	if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1063*4882a593Smuzhiyun 		return err;
1064*4882a593Smuzhiyun 	if (chip->secondary) {
1065*4882a593Smuzhiyun 		ac97.num = 1;
1066*4882a593Smuzhiyun 		ac97.addr = chip->secondary_addr;
1067*4882a593Smuzhiyun 		if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_sec)) < 0)
1068*4882a593Smuzhiyun 			return err;
1069*4882a593Smuzhiyun 	}
1070*4882a593Smuzhiyun 	for (i = 0; i < FM801_CONTROLS; i++) {
1071*4882a593Smuzhiyun 		err = snd_ctl_add(chip->card,
1072*4882a593Smuzhiyun 			snd_ctl_new1(&snd_fm801_controls[i], chip));
1073*4882a593Smuzhiyun 		if (err < 0)
1074*4882a593Smuzhiyun 			return err;
1075*4882a593Smuzhiyun 	}
1076*4882a593Smuzhiyun 	if (chip->multichannel) {
1077*4882a593Smuzhiyun 		for (i = 0; i < FM801_CONTROLS_MULTI; i++) {
1078*4882a593Smuzhiyun 			err = snd_ctl_add(chip->card,
1079*4882a593Smuzhiyun 				snd_ctl_new1(&snd_fm801_controls_multi[i], chip));
1080*4882a593Smuzhiyun 			if (err < 0)
1081*4882a593Smuzhiyun 				return err;
1082*4882a593Smuzhiyun 		}
1083*4882a593Smuzhiyun 	}
1084*4882a593Smuzhiyun 	return 0;
1085*4882a593Smuzhiyun }
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun /*
1088*4882a593Smuzhiyun  *  initialization routines
1089*4882a593Smuzhiyun  */
1090*4882a593Smuzhiyun 
wait_for_codec(struct fm801 * chip,unsigned int codec_id,unsigned short reg,unsigned long waits)1091*4882a593Smuzhiyun static int wait_for_codec(struct fm801 *chip, unsigned int codec_id,
1092*4882a593Smuzhiyun 			  unsigned short reg, unsigned long waits)
1093*4882a593Smuzhiyun {
1094*4882a593Smuzhiyun 	unsigned long timeout = jiffies + waits;
1095*4882a593Smuzhiyun 
1096*4882a593Smuzhiyun 	fm801_writew(chip, AC97_CMD,
1097*4882a593Smuzhiyun 		     reg | (codec_id << FM801_AC97_ADDR_SHIFT) | FM801_AC97_READ);
1098*4882a593Smuzhiyun 	udelay(5);
1099*4882a593Smuzhiyun 	do {
1100*4882a593Smuzhiyun 		if ((fm801_readw(chip, AC97_CMD) &
1101*4882a593Smuzhiyun 		     (FM801_AC97_VALID | FM801_AC97_BUSY)) == FM801_AC97_VALID)
1102*4882a593Smuzhiyun 			return 0;
1103*4882a593Smuzhiyun 		schedule_timeout_uninterruptible(1);
1104*4882a593Smuzhiyun 	} while (time_after(timeout, jiffies));
1105*4882a593Smuzhiyun 	return -EIO;
1106*4882a593Smuzhiyun }
1107*4882a593Smuzhiyun 
reset_codec(struct fm801 * chip)1108*4882a593Smuzhiyun static int reset_codec(struct fm801 *chip)
1109*4882a593Smuzhiyun {
1110*4882a593Smuzhiyun 	/* codec cold reset + AC'97 warm reset */
1111*4882a593Smuzhiyun 	fm801_writew(chip, CODEC_CTRL, (1 << 5) | (1 << 6));
1112*4882a593Smuzhiyun 	fm801_readw(chip, CODEC_CTRL); /* flush posting data */
1113*4882a593Smuzhiyun 	udelay(100);
1114*4882a593Smuzhiyun 	fm801_writew(chip, CODEC_CTRL, 0);
1115*4882a593Smuzhiyun 
1116*4882a593Smuzhiyun 	return wait_for_codec(chip, 0, AC97_RESET, msecs_to_jiffies(750));
1117*4882a593Smuzhiyun }
1118*4882a593Smuzhiyun 
snd_fm801_chip_multichannel_init(struct fm801 * chip)1119*4882a593Smuzhiyun static void snd_fm801_chip_multichannel_init(struct fm801 *chip)
1120*4882a593Smuzhiyun {
1121*4882a593Smuzhiyun 	unsigned short cmdw;
1122*4882a593Smuzhiyun 
1123*4882a593Smuzhiyun 	if (chip->multichannel) {
1124*4882a593Smuzhiyun 		if (chip->secondary_addr) {
1125*4882a593Smuzhiyun 			wait_for_codec(chip, chip->secondary_addr,
1126*4882a593Smuzhiyun 				       AC97_VENDOR_ID1, msecs_to_jiffies(50));
1127*4882a593Smuzhiyun 		} else {
1128*4882a593Smuzhiyun 			/* my card has the secondary codec */
1129*4882a593Smuzhiyun 			/* at address #3, so the loop is inverted */
1130*4882a593Smuzhiyun 			int i;
1131*4882a593Smuzhiyun 			for (i = 3; i > 0; i--) {
1132*4882a593Smuzhiyun 				if (!wait_for_codec(chip, i, AC97_VENDOR_ID1,
1133*4882a593Smuzhiyun 						     msecs_to_jiffies(50))) {
1134*4882a593Smuzhiyun 					cmdw = fm801_readw(chip, AC97_DATA);
1135*4882a593Smuzhiyun 					if (cmdw != 0xffff && cmdw != 0) {
1136*4882a593Smuzhiyun 						chip->secondary = 1;
1137*4882a593Smuzhiyun 						chip->secondary_addr = i;
1138*4882a593Smuzhiyun 						break;
1139*4882a593Smuzhiyun 					}
1140*4882a593Smuzhiyun 				}
1141*4882a593Smuzhiyun 			}
1142*4882a593Smuzhiyun 		}
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun 		/* the recovery phase, it seems that probing for non-existing codec might */
1145*4882a593Smuzhiyun 		/* cause timeout problems */
1146*4882a593Smuzhiyun 		wait_for_codec(chip, 0, AC97_VENDOR_ID1, msecs_to_jiffies(750));
1147*4882a593Smuzhiyun 	}
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun 
snd_fm801_chip_init(struct fm801 * chip)1150*4882a593Smuzhiyun static void snd_fm801_chip_init(struct fm801 *chip)
1151*4882a593Smuzhiyun {
1152*4882a593Smuzhiyun 	unsigned short cmdw;
1153*4882a593Smuzhiyun 
1154*4882a593Smuzhiyun 	/* init volume */
1155*4882a593Smuzhiyun 	fm801_writew(chip, PCM_VOL, 0x0808);
1156*4882a593Smuzhiyun 	fm801_writew(chip, FM_VOL, 0x9f1f);
1157*4882a593Smuzhiyun 	fm801_writew(chip, I2S_VOL, 0x8808);
1158*4882a593Smuzhiyun 
1159*4882a593Smuzhiyun 	/* I2S control - I2S mode */
1160*4882a593Smuzhiyun 	fm801_writew(chip, I2S_MODE, 0x0003);
1161*4882a593Smuzhiyun 
1162*4882a593Smuzhiyun 	/* interrupt setup */
1163*4882a593Smuzhiyun 	cmdw = fm801_readw(chip, IRQ_MASK);
1164*4882a593Smuzhiyun 	if (chip->irq < 0)
1165*4882a593Smuzhiyun 		cmdw |= 0x00c3;		/* mask everything, no PCM nor MPU */
1166*4882a593Smuzhiyun 	else
1167*4882a593Smuzhiyun 		cmdw &= ~0x0083;	/* unmask MPU, PLAYBACK & CAPTURE */
1168*4882a593Smuzhiyun 	fm801_writew(chip, IRQ_MASK, cmdw);
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 	/* interrupt clear */
1171*4882a593Smuzhiyun 	fm801_writew(chip, IRQ_STATUS,
1172*4882a593Smuzhiyun 		     FM801_IRQ_PLAYBACK | FM801_IRQ_CAPTURE | FM801_IRQ_MPU);
1173*4882a593Smuzhiyun }
1174*4882a593Smuzhiyun 
snd_fm801_free(struct fm801 * chip)1175*4882a593Smuzhiyun static int snd_fm801_free(struct fm801 *chip)
1176*4882a593Smuzhiyun {
1177*4882a593Smuzhiyun 	unsigned short cmdw;
1178*4882a593Smuzhiyun 
1179*4882a593Smuzhiyun 	if (chip->irq < 0)
1180*4882a593Smuzhiyun 		goto __end_hw;
1181*4882a593Smuzhiyun 
1182*4882a593Smuzhiyun 	/* interrupt setup - mask everything */
1183*4882a593Smuzhiyun 	cmdw = fm801_readw(chip, IRQ_MASK);
1184*4882a593Smuzhiyun 	cmdw |= 0x00c3;
1185*4882a593Smuzhiyun 	fm801_writew(chip, IRQ_MASK, cmdw);
1186*4882a593Smuzhiyun 
1187*4882a593Smuzhiyun 	devm_free_irq(chip->dev, chip->irq, chip);
1188*4882a593Smuzhiyun 
1189*4882a593Smuzhiyun       __end_hw:
1190*4882a593Smuzhiyun #ifdef CONFIG_SND_FM801_TEA575X_BOOL
1191*4882a593Smuzhiyun 	if (!(chip->tea575x_tuner & TUNER_DISABLED)) {
1192*4882a593Smuzhiyun 		snd_tea575x_exit(&chip->tea);
1193*4882a593Smuzhiyun 		v4l2_device_unregister(&chip->v4l2_dev);
1194*4882a593Smuzhiyun 	}
1195*4882a593Smuzhiyun #endif
1196*4882a593Smuzhiyun 	return 0;
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun 
snd_fm801_dev_free(struct snd_device * device)1199*4882a593Smuzhiyun static int snd_fm801_dev_free(struct snd_device *device)
1200*4882a593Smuzhiyun {
1201*4882a593Smuzhiyun 	struct fm801 *chip = device->device_data;
1202*4882a593Smuzhiyun 	return snd_fm801_free(chip);
1203*4882a593Smuzhiyun }
1204*4882a593Smuzhiyun 
snd_fm801_create(struct snd_card * card,struct pci_dev * pci,int tea575x_tuner,int radio_nr,struct fm801 ** rchip)1205*4882a593Smuzhiyun static int snd_fm801_create(struct snd_card *card,
1206*4882a593Smuzhiyun 			    struct pci_dev *pci,
1207*4882a593Smuzhiyun 			    int tea575x_tuner,
1208*4882a593Smuzhiyun 			    int radio_nr,
1209*4882a593Smuzhiyun 			    struct fm801 **rchip)
1210*4882a593Smuzhiyun {
1211*4882a593Smuzhiyun 	struct fm801 *chip;
1212*4882a593Smuzhiyun 	int err;
1213*4882a593Smuzhiyun 	static const struct snd_device_ops ops = {
1214*4882a593Smuzhiyun 		.dev_free =	snd_fm801_dev_free,
1215*4882a593Smuzhiyun 	};
1216*4882a593Smuzhiyun 
1217*4882a593Smuzhiyun 	*rchip = NULL;
1218*4882a593Smuzhiyun 	if ((err = pcim_enable_device(pci)) < 0)
1219*4882a593Smuzhiyun 		return err;
1220*4882a593Smuzhiyun 	chip = devm_kzalloc(&pci->dev, sizeof(*chip), GFP_KERNEL);
1221*4882a593Smuzhiyun 	if (chip == NULL)
1222*4882a593Smuzhiyun 		return -ENOMEM;
1223*4882a593Smuzhiyun 	spin_lock_init(&chip->reg_lock);
1224*4882a593Smuzhiyun 	chip->card = card;
1225*4882a593Smuzhiyun 	chip->dev = &pci->dev;
1226*4882a593Smuzhiyun 	chip->irq = -1;
1227*4882a593Smuzhiyun 	chip->tea575x_tuner = tea575x_tuner;
1228*4882a593Smuzhiyun 	if ((err = pci_request_regions(pci, "FM801")) < 0)
1229*4882a593Smuzhiyun 		return err;
1230*4882a593Smuzhiyun 	chip->port = pci_resource_start(pci, 0);
1231*4882a593Smuzhiyun 
1232*4882a593Smuzhiyun 	if (pci->revision >= 0xb1)	/* FM801-AU */
1233*4882a593Smuzhiyun 		chip->multichannel = 1;
1234*4882a593Smuzhiyun 
1235*4882a593Smuzhiyun 	if (!(chip->tea575x_tuner & TUNER_ONLY)) {
1236*4882a593Smuzhiyun 		if (reset_codec(chip) < 0) {
1237*4882a593Smuzhiyun 			dev_info(chip->card->dev,
1238*4882a593Smuzhiyun 				 "Primary AC'97 codec not found, assume SF64-PCR (tuner-only)\n");
1239*4882a593Smuzhiyun 			chip->tea575x_tuner = 3 | TUNER_ONLY;
1240*4882a593Smuzhiyun 		} else {
1241*4882a593Smuzhiyun 			snd_fm801_chip_multichannel_init(chip);
1242*4882a593Smuzhiyun 		}
1243*4882a593Smuzhiyun 	}
1244*4882a593Smuzhiyun 
1245*4882a593Smuzhiyun 	if ((chip->tea575x_tuner & TUNER_ONLY) == 0) {
1246*4882a593Smuzhiyun 		if (devm_request_irq(&pci->dev, pci->irq, snd_fm801_interrupt,
1247*4882a593Smuzhiyun 				IRQF_SHARED, KBUILD_MODNAME, chip)) {
1248*4882a593Smuzhiyun 			dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1249*4882a593Smuzhiyun 			snd_fm801_free(chip);
1250*4882a593Smuzhiyun 			return -EBUSY;
1251*4882a593Smuzhiyun 		}
1252*4882a593Smuzhiyun 		chip->irq = pci->irq;
1253*4882a593Smuzhiyun 		card->sync_irq = chip->irq;
1254*4882a593Smuzhiyun 		pci_set_master(pci);
1255*4882a593Smuzhiyun 	}
1256*4882a593Smuzhiyun 
1257*4882a593Smuzhiyun 	snd_fm801_chip_init(chip);
1258*4882a593Smuzhiyun 
1259*4882a593Smuzhiyun 	if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1260*4882a593Smuzhiyun 		snd_fm801_free(chip);
1261*4882a593Smuzhiyun 		return err;
1262*4882a593Smuzhiyun 	}
1263*4882a593Smuzhiyun 
1264*4882a593Smuzhiyun #ifdef CONFIG_SND_FM801_TEA575X_BOOL
1265*4882a593Smuzhiyun 	err = v4l2_device_register(&pci->dev, &chip->v4l2_dev);
1266*4882a593Smuzhiyun 	if (err < 0) {
1267*4882a593Smuzhiyun 		snd_fm801_free(chip);
1268*4882a593Smuzhiyun 		return err;
1269*4882a593Smuzhiyun 	}
1270*4882a593Smuzhiyun 	chip->tea.v4l2_dev = &chip->v4l2_dev;
1271*4882a593Smuzhiyun 	chip->tea.radio_nr = radio_nr;
1272*4882a593Smuzhiyun 	chip->tea.private_data = chip;
1273*4882a593Smuzhiyun 	chip->tea.ops = &snd_fm801_tea_ops;
1274*4882a593Smuzhiyun 	sprintf(chip->tea.bus_info, "PCI:%s", pci_name(pci));
1275*4882a593Smuzhiyun 	if ((chip->tea575x_tuner & TUNER_TYPE_MASK) > 0 &&
1276*4882a593Smuzhiyun 	    (chip->tea575x_tuner & TUNER_TYPE_MASK) < 4) {
1277*4882a593Smuzhiyun 		if (snd_tea575x_init(&chip->tea, THIS_MODULE)) {
1278*4882a593Smuzhiyun 			dev_err(card->dev, "TEA575x radio not found\n");
1279*4882a593Smuzhiyun 			snd_fm801_free(chip);
1280*4882a593Smuzhiyun 			return -ENODEV;
1281*4882a593Smuzhiyun 		}
1282*4882a593Smuzhiyun 	} else if ((chip->tea575x_tuner & TUNER_TYPE_MASK) == 0) {
1283*4882a593Smuzhiyun 		unsigned int tuner_only = chip->tea575x_tuner & TUNER_ONLY;
1284*4882a593Smuzhiyun 
1285*4882a593Smuzhiyun 		/* autodetect tuner connection */
1286*4882a593Smuzhiyun 		for (tea575x_tuner = 1; tea575x_tuner <= 3; tea575x_tuner++) {
1287*4882a593Smuzhiyun 			chip->tea575x_tuner = tea575x_tuner;
1288*4882a593Smuzhiyun 			if (!snd_tea575x_init(&chip->tea, THIS_MODULE)) {
1289*4882a593Smuzhiyun 				dev_info(card->dev,
1290*4882a593Smuzhiyun 					 "detected TEA575x radio type %s\n",
1291*4882a593Smuzhiyun 					   get_tea575x_gpio(chip)->name);
1292*4882a593Smuzhiyun 				break;
1293*4882a593Smuzhiyun 			}
1294*4882a593Smuzhiyun 		}
1295*4882a593Smuzhiyun 		if (tea575x_tuner == 4) {
1296*4882a593Smuzhiyun 			dev_err(card->dev, "TEA575x radio not found\n");
1297*4882a593Smuzhiyun 			chip->tea575x_tuner = TUNER_DISABLED;
1298*4882a593Smuzhiyun 		}
1299*4882a593Smuzhiyun 
1300*4882a593Smuzhiyun 		chip->tea575x_tuner |= tuner_only;
1301*4882a593Smuzhiyun 	}
1302*4882a593Smuzhiyun 	if (!(chip->tea575x_tuner & TUNER_DISABLED)) {
1303*4882a593Smuzhiyun 		strlcpy(chip->tea.card, get_tea575x_gpio(chip)->name,
1304*4882a593Smuzhiyun 			sizeof(chip->tea.card));
1305*4882a593Smuzhiyun 	}
1306*4882a593Smuzhiyun #endif
1307*4882a593Smuzhiyun 
1308*4882a593Smuzhiyun 	*rchip = chip;
1309*4882a593Smuzhiyun 	return 0;
1310*4882a593Smuzhiyun }
1311*4882a593Smuzhiyun 
snd_card_fm801_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1312*4882a593Smuzhiyun static int snd_card_fm801_probe(struct pci_dev *pci,
1313*4882a593Smuzhiyun 				const struct pci_device_id *pci_id)
1314*4882a593Smuzhiyun {
1315*4882a593Smuzhiyun 	static int dev;
1316*4882a593Smuzhiyun 	struct snd_card *card;
1317*4882a593Smuzhiyun 	struct fm801 *chip;
1318*4882a593Smuzhiyun 	struct snd_opl3 *opl3;
1319*4882a593Smuzhiyun 	int err;
1320*4882a593Smuzhiyun 
1321*4882a593Smuzhiyun         if (dev >= SNDRV_CARDS)
1322*4882a593Smuzhiyun                 return -ENODEV;
1323*4882a593Smuzhiyun 	if (!enable[dev]) {
1324*4882a593Smuzhiyun 		dev++;
1325*4882a593Smuzhiyun 		return -ENOENT;
1326*4882a593Smuzhiyun 	}
1327*4882a593Smuzhiyun 
1328*4882a593Smuzhiyun 	err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1329*4882a593Smuzhiyun 			   0, &card);
1330*4882a593Smuzhiyun 	if (err < 0)
1331*4882a593Smuzhiyun 		return err;
1332*4882a593Smuzhiyun 	if ((err = snd_fm801_create(card, pci, tea575x_tuner[dev], radio_nr[dev], &chip)) < 0) {
1333*4882a593Smuzhiyun 		snd_card_free(card);
1334*4882a593Smuzhiyun 		return err;
1335*4882a593Smuzhiyun 	}
1336*4882a593Smuzhiyun 	card->private_data = chip;
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun 	strcpy(card->driver, "FM801");
1339*4882a593Smuzhiyun 	strcpy(card->shortname, "ForteMedia FM801-");
1340*4882a593Smuzhiyun 	strcat(card->shortname, chip->multichannel ? "AU" : "AS");
1341*4882a593Smuzhiyun 	sprintf(card->longname, "%s at 0x%lx, irq %i",
1342*4882a593Smuzhiyun 		card->shortname, chip->port, chip->irq);
1343*4882a593Smuzhiyun 
1344*4882a593Smuzhiyun 	if (chip->tea575x_tuner & TUNER_ONLY)
1345*4882a593Smuzhiyun 		goto __fm801_tuner_only;
1346*4882a593Smuzhiyun 
1347*4882a593Smuzhiyun 	if ((err = snd_fm801_pcm(chip, 0)) < 0) {
1348*4882a593Smuzhiyun 		snd_card_free(card);
1349*4882a593Smuzhiyun 		return err;
1350*4882a593Smuzhiyun 	}
1351*4882a593Smuzhiyun 	if ((err = snd_fm801_mixer(chip)) < 0) {
1352*4882a593Smuzhiyun 		snd_card_free(card);
1353*4882a593Smuzhiyun 		return err;
1354*4882a593Smuzhiyun 	}
1355*4882a593Smuzhiyun 	if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_FM801,
1356*4882a593Smuzhiyun 				       chip->port + FM801_MPU401_DATA,
1357*4882a593Smuzhiyun 				       MPU401_INFO_INTEGRATED |
1358*4882a593Smuzhiyun 				       MPU401_INFO_IRQ_HOOK,
1359*4882a593Smuzhiyun 				       -1, &chip->rmidi)) < 0) {
1360*4882a593Smuzhiyun 		snd_card_free(card);
1361*4882a593Smuzhiyun 		return err;
1362*4882a593Smuzhiyun 	}
1363*4882a593Smuzhiyun 	if ((err = snd_opl3_create(card, chip->port + FM801_OPL3_BANK0,
1364*4882a593Smuzhiyun 				   chip->port + FM801_OPL3_BANK1,
1365*4882a593Smuzhiyun 				   OPL3_HW_OPL3_FM801, 1, &opl3)) < 0) {
1366*4882a593Smuzhiyun 		snd_card_free(card);
1367*4882a593Smuzhiyun 		return err;
1368*4882a593Smuzhiyun 	}
1369*4882a593Smuzhiyun 	if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1370*4882a593Smuzhiyun 		snd_card_free(card);
1371*4882a593Smuzhiyun 		return err;
1372*4882a593Smuzhiyun 	}
1373*4882a593Smuzhiyun 
1374*4882a593Smuzhiyun       __fm801_tuner_only:
1375*4882a593Smuzhiyun 	if ((err = snd_card_register(card)) < 0) {
1376*4882a593Smuzhiyun 		snd_card_free(card);
1377*4882a593Smuzhiyun 		return err;
1378*4882a593Smuzhiyun 	}
1379*4882a593Smuzhiyun 	pci_set_drvdata(pci, card);
1380*4882a593Smuzhiyun 	dev++;
1381*4882a593Smuzhiyun 	return 0;
1382*4882a593Smuzhiyun }
1383*4882a593Smuzhiyun 
snd_card_fm801_remove(struct pci_dev * pci)1384*4882a593Smuzhiyun static void snd_card_fm801_remove(struct pci_dev *pci)
1385*4882a593Smuzhiyun {
1386*4882a593Smuzhiyun 	snd_card_free(pci_get_drvdata(pci));
1387*4882a593Smuzhiyun }
1388*4882a593Smuzhiyun 
1389*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
1390*4882a593Smuzhiyun static const unsigned char saved_regs[] = {
1391*4882a593Smuzhiyun 	FM801_PCM_VOL, FM801_I2S_VOL, FM801_FM_VOL, FM801_REC_SRC,
1392*4882a593Smuzhiyun 	FM801_PLY_CTRL, FM801_PLY_COUNT, FM801_PLY_BUF1, FM801_PLY_BUF2,
1393*4882a593Smuzhiyun 	FM801_CAP_CTRL, FM801_CAP_COUNT, FM801_CAP_BUF1, FM801_CAP_BUF2,
1394*4882a593Smuzhiyun 	FM801_CODEC_CTRL, FM801_I2S_MODE, FM801_VOLUME, FM801_GEN_CTRL,
1395*4882a593Smuzhiyun };
1396*4882a593Smuzhiyun 
snd_fm801_suspend(struct device * dev)1397*4882a593Smuzhiyun static int snd_fm801_suspend(struct device *dev)
1398*4882a593Smuzhiyun {
1399*4882a593Smuzhiyun 	struct snd_card *card = dev_get_drvdata(dev);
1400*4882a593Smuzhiyun 	struct fm801 *chip = card->private_data;
1401*4882a593Smuzhiyun 	int i;
1402*4882a593Smuzhiyun 
1403*4882a593Smuzhiyun 	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1404*4882a593Smuzhiyun 
1405*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1406*4882a593Smuzhiyun 		chip->saved_regs[i] = fm801_ioread16(chip, saved_regs[i]);
1407*4882a593Smuzhiyun 
1408*4882a593Smuzhiyun 	if (chip->tea575x_tuner & TUNER_ONLY) {
1409*4882a593Smuzhiyun 		/* FIXME: tea575x suspend */
1410*4882a593Smuzhiyun 	} else {
1411*4882a593Smuzhiyun 		snd_ac97_suspend(chip->ac97);
1412*4882a593Smuzhiyun 		snd_ac97_suspend(chip->ac97_sec);
1413*4882a593Smuzhiyun 	}
1414*4882a593Smuzhiyun 
1415*4882a593Smuzhiyun 	return 0;
1416*4882a593Smuzhiyun }
1417*4882a593Smuzhiyun 
snd_fm801_resume(struct device * dev)1418*4882a593Smuzhiyun static int snd_fm801_resume(struct device *dev)
1419*4882a593Smuzhiyun {
1420*4882a593Smuzhiyun 	struct snd_card *card = dev_get_drvdata(dev);
1421*4882a593Smuzhiyun 	struct fm801 *chip = card->private_data;
1422*4882a593Smuzhiyun 	int i;
1423*4882a593Smuzhiyun 
1424*4882a593Smuzhiyun 	if (chip->tea575x_tuner & TUNER_ONLY) {
1425*4882a593Smuzhiyun 		snd_fm801_chip_init(chip);
1426*4882a593Smuzhiyun 	} else {
1427*4882a593Smuzhiyun 		reset_codec(chip);
1428*4882a593Smuzhiyun 		snd_fm801_chip_multichannel_init(chip);
1429*4882a593Smuzhiyun 		snd_fm801_chip_init(chip);
1430*4882a593Smuzhiyun 		snd_ac97_resume(chip->ac97);
1431*4882a593Smuzhiyun 		snd_ac97_resume(chip->ac97_sec);
1432*4882a593Smuzhiyun 	}
1433*4882a593Smuzhiyun 
1434*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1435*4882a593Smuzhiyun 		fm801_iowrite16(chip, saved_regs[i], chip->saved_regs[i]);
1436*4882a593Smuzhiyun 
1437*4882a593Smuzhiyun #ifdef CONFIG_SND_FM801_TEA575X_BOOL
1438*4882a593Smuzhiyun 	if (!(chip->tea575x_tuner & TUNER_DISABLED))
1439*4882a593Smuzhiyun 		snd_tea575x_set_freq(&chip->tea);
1440*4882a593Smuzhiyun #endif
1441*4882a593Smuzhiyun 
1442*4882a593Smuzhiyun 	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1443*4882a593Smuzhiyun 	return 0;
1444*4882a593Smuzhiyun }
1445*4882a593Smuzhiyun 
1446*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(snd_fm801_pm, snd_fm801_suspend, snd_fm801_resume);
1447*4882a593Smuzhiyun #define SND_FM801_PM_OPS	&snd_fm801_pm
1448*4882a593Smuzhiyun #else
1449*4882a593Smuzhiyun #define SND_FM801_PM_OPS	NULL
1450*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
1451*4882a593Smuzhiyun 
1452*4882a593Smuzhiyun static struct pci_driver fm801_driver = {
1453*4882a593Smuzhiyun 	.name = KBUILD_MODNAME,
1454*4882a593Smuzhiyun 	.id_table = snd_fm801_ids,
1455*4882a593Smuzhiyun 	.probe = snd_card_fm801_probe,
1456*4882a593Smuzhiyun 	.remove = snd_card_fm801_remove,
1457*4882a593Smuzhiyun 	.driver = {
1458*4882a593Smuzhiyun 		.pm = SND_FM801_PM_OPS,
1459*4882a593Smuzhiyun 	},
1460*4882a593Smuzhiyun };
1461*4882a593Smuzhiyun 
1462*4882a593Smuzhiyun module_pci_driver(fm801_driver);
1463