1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for ESS Solo-1 (ES1938, ES1946, ES1969) soundcard
4*4882a593Smuzhiyun * Copyright (c) by Jaromir Koutek <miri@punknet.cz>,
5*4882a593Smuzhiyun * Jaroslav Kysela <perex@perex.cz>,
6*4882a593Smuzhiyun * Thomas Sailer <sailer@ife.ee.ethz.ch>,
7*4882a593Smuzhiyun * Abramo Bagnara <abramo@alsa-project.org>,
8*4882a593Smuzhiyun * Markus Gruber <gruber@eikon.tum.de>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Rewritten from sonicvibes.c source.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * TODO:
13*4882a593Smuzhiyun * Rewrite better spinlocks
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun NOTES:
18*4882a593Smuzhiyun - Capture data is written unaligned starting from dma_base + 1 so I need to
19*4882a593Smuzhiyun disable mmap and to add a copy callback.
20*4882a593Smuzhiyun - After several cycle of the following:
21*4882a593Smuzhiyun while : ; do arecord -d1 -f cd -t raw | aplay -f cd ; done
22*4882a593Smuzhiyun a "playback write error (DMA or IRQ trouble?)" may happen.
23*4882a593Smuzhiyun This is due to playback interrupts not generated.
24*4882a593Smuzhiyun I suspect a timing issue.
25*4882a593Smuzhiyun - Sometimes the interrupt handler is invoked wrongly during playback.
26*4882a593Smuzhiyun This generates some harmless "Unexpected hw_pointer: wrong interrupt
27*4882a593Smuzhiyun acknowledge".
28*4882a593Smuzhiyun I've seen that using small period sizes.
29*4882a593Smuzhiyun Reproducible with:
30*4882a593Smuzhiyun mpg123 test.mp3 &
31*4882a593Smuzhiyun hdparm -t -T /dev/hda
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #include <linux/init.h>
36*4882a593Smuzhiyun #include <linux/interrupt.h>
37*4882a593Smuzhiyun #include <linux/pci.h>
38*4882a593Smuzhiyun #include <linux/slab.h>
39*4882a593Smuzhiyun #include <linux/gameport.h>
40*4882a593Smuzhiyun #include <linux/module.h>
41*4882a593Smuzhiyun #include <linux/delay.h>
42*4882a593Smuzhiyun #include <linux/dma-mapping.h>
43*4882a593Smuzhiyun #include <linux/io.h>
44*4882a593Smuzhiyun #include <sound/core.h>
45*4882a593Smuzhiyun #include <sound/control.h>
46*4882a593Smuzhiyun #include <sound/pcm.h>
47*4882a593Smuzhiyun #include <sound/opl3.h>
48*4882a593Smuzhiyun #include <sound/mpu401.h>
49*4882a593Smuzhiyun #include <sound/initval.h>
50*4882a593Smuzhiyun #include <sound/tlv.h>
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun MODULE_AUTHOR("Jaromir Koutek <miri@punknet.cz>");
53*4882a593Smuzhiyun MODULE_DESCRIPTION("ESS Solo-1");
54*4882a593Smuzhiyun MODULE_LICENSE("GPL");
55*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{{ESS,ES1938},"
56*4882a593Smuzhiyun "{ESS,ES1946},"
57*4882a593Smuzhiyun "{ESS,ES1969},"
58*4882a593Smuzhiyun "{TerraTec,128i PCI}}");
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #if IS_REACHABLE(CONFIG_GAMEPORT)
61*4882a593Smuzhiyun #define SUPPORT_JOYSTICK 1
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
65*4882a593Smuzhiyun static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
66*4882a593Smuzhiyun static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun module_param_array(index, int, NULL, 0444);
69*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for ESS Solo-1 soundcard.");
70*4882a593Smuzhiyun module_param_array(id, charp, NULL, 0444);
71*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for ESS Solo-1 soundcard.");
72*4882a593Smuzhiyun module_param_array(enable, bool, NULL, 0444);
73*4882a593Smuzhiyun MODULE_PARM_DESC(enable, "Enable ESS Solo-1 soundcard.");
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define SLIO_REG(chip, x) ((chip)->io_port + ESSIO_REG_##x)
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define SLDM_REG(chip, x) ((chip)->ddma_port + ESSDM_REG_##x)
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define SLSB_REG(chip, x) ((chip)->sb_port + ESSSB_REG_##x)
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define SL_PCI_LEGACYCONTROL 0x40
82*4882a593Smuzhiyun #define SL_PCI_CONFIG 0x50
83*4882a593Smuzhiyun #define SL_PCI_DDMACONTROL 0x60
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define ESSIO_REG_AUDIO2DMAADDR 0
86*4882a593Smuzhiyun #define ESSIO_REG_AUDIO2DMACOUNT 4
87*4882a593Smuzhiyun #define ESSIO_REG_AUDIO2MODE 6
88*4882a593Smuzhiyun #define ESSIO_REG_IRQCONTROL 7
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #define ESSDM_REG_DMAADDR 0x00
91*4882a593Smuzhiyun #define ESSDM_REG_DMACOUNT 0x04
92*4882a593Smuzhiyun #define ESSDM_REG_DMACOMMAND 0x08
93*4882a593Smuzhiyun #define ESSDM_REG_DMASTATUS 0x08
94*4882a593Smuzhiyun #define ESSDM_REG_DMAMODE 0x0b
95*4882a593Smuzhiyun #define ESSDM_REG_DMACLEAR 0x0d
96*4882a593Smuzhiyun #define ESSDM_REG_DMAMASK 0x0f
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #define ESSSB_REG_FMLOWADDR 0x00
99*4882a593Smuzhiyun #define ESSSB_REG_FMHIGHADDR 0x02
100*4882a593Smuzhiyun #define ESSSB_REG_MIXERADDR 0x04
101*4882a593Smuzhiyun #define ESSSB_REG_MIXERDATA 0x05
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define ESSSB_IREG_AUDIO1 0x14
104*4882a593Smuzhiyun #define ESSSB_IREG_MICMIX 0x1a
105*4882a593Smuzhiyun #define ESSSB_IREG_RECSRC 0x1c
106*4882a593Smuzhiyun #define ESSSB_IREG_MASTER 0x32
107*4882a593Smuzhiyun #define ESSSB_IREG_FM 0x36
108*4882a593Smuzhiyun #define ESSSB_IREG_AUXACD 0x38
109*4882a593Smuzhiyun #define ESSSB_IREG_AUXB 0x3a
110*4882a593Smuzhiyun #define ESSSB_IREG_PCSPEAKER 0x3c
111*4882a593Smuzhiyun #define ESSSB_IREG_LINE 0x3e
112*4882a593Smuzhiyun #define ESSSB_IREG_SPATCONTROL 0x50
113*4882a593Smuzhiyun #define ESSSB_IREG_SPATLEVEL 0x52
114*4882a593Smuzhiyun #define ESSSB_IREG_MASTER_LEFT 0x60
115*4882a593Smuzhiyun #define ESSSB_IREG_MASTER_RIGHT 0x62
116*4882a593Smuzhiyun #define ESSSB_IREG_MPU401CONTROL 0x64
117*4882a593Smuzhiyun #define ESSSB_IREG_MICMIXRECORD 0x68
118*4882a593Smuzhiyun #define ESSSB_IREG_AUDIO2RECORD 0x69
119*4882a593Smuzhiyun #define ESSSB_IREG_AUXACDRECORD 0x6a
120*4882a593Smuzhiyun #define ESSSB_IREG_FMRECORD 0x6b
121*4882a593Smuzhiyun #define ESSSB_IREG_AUXBRECORD 0x6c
122*4882a593Smuzhiyun #define ESSSB_IREG_MONO 0x6d
123*4882a593Smuzhiyun #define ESSSB_IREG_LINERECORD 0x6e
124*4882a593Smuzhiyun #define ESSSB_IREG_MONORECORD 0x6f
125*4882a593Smuzhiyun #define ESSSB_IREG_AUDIO2SAMPLE 0x70
126*4882a593Smuzhiyun #define ESSSB_IREG_AUDIO2MODE 0x71
127*4882a593Smuzhiyun #define ESSSB_IREG_AUDIO2FILTER 0x72
128*4882a593Smuzhiyun #define ESSSB_IREG_AUDIO2TCOUNTL 0x74
129*4882a593Smuzhiyun #define ESSSB_IREG_AUDIO2TCOUNTH 0x76
130*4882a593Smuzhiyun #define ESSSB_IREG_AUDIO2CONTROL1 0x78
131*4882a593Smuzhiyun #define ESSSB_IREG_AUDIO2CONTROL2 0x7a
132*4882a593Smuzhiyun #define ESSSB_IREG_AUDIO2 0x7c
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun #define ESSSB_REG_RESET 0x06
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #define ESSSB_REG_READDATA 0x0a
137*4882a593Smuzhiyun #define ESSSB_REG_WRITEDATA 0x0c
138*4882a593Smuzhiyun #define ESSSB_REG_READSTATUS 0x0c
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #define ESSSB_REG_STATUS 0x0e
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #define ESS_CMD_EXTSAMPLERATE 0xa1
143*4882a593Smuzhiyun #define ESS_CMD_FILTERDIV 0xa2
144*4882a593Smuzhiyun #define ESS_CMD_DMACNTRELOADL 0xa4
145*4882a593Smuzhiyun #define ESS_CMD_DMACNTRELOADH 0xa5
146*4882a593Smuzhiyun #define ESS_CMD_ANALOGCONTROL 0xa8
147*4882a593Smuzhiyun #define ESS_CMD_IRQCONTROL 0xb1
148*4882a593Smuzhiyun #define ESS_CMD_DRQCONTROL 0xb2
149*4882a593Smuzhiyun #define ESS_CMD_RECLEVEL 0xb4
150*4882a593Smuzhiyun #define ESS_CMD_SETFORMAT 0xb6
151*4882a593Smuzhiyun #define ESS_CMD_SETFORMAT2 0xb7
152*4882a593Smuzhiyun #define ESS_CMD_DMACONTROL 0xb8
153*4882a593Smuzhiyun #define ESS_CMD_DMATYPE 0xb9
154*4882a593Smuzhiyun #define ESS_CMD_OFFSETLEFT 0xba
155*4882a593Smuzhiyun #define ESS_CMD_OFFSETRIGHT 0xbb
156*4882a593Smuzhiyun #define ESS_CMD_READREG 0xc0
157*4882a593Smuzhiyun #define ESS_CMD_ENABLEEXT 0xc6
158*4882a593Smuzhiyun #define ESS_CMD_PAUSEDMA 0xd0
159*4882a593Smuzhiyun #define ESS_CMD_ENABLEAUDIO1 0xd1
160*4882a593Smuzhiyun #define ESS_CMD_STOPAUDIO1 0xd3
161*4882a593Smuzhiyun #define ESS_CMD_AUDIO1STATUS 0xd8
162*4882a593Smuzhiyun #define ESS_CMD_CONTDMA 0xd4
163*4882a593Smuzhiyun #define ESS_CMD_TESTIRQ 0xf2
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun #define ESS_RECSRC_MIC 0
166*4882a593Smuzhiyun #define ESS_RECSRC_AUXACD 2
167*4882a593Smuzhiyun #define ESS_RECSRC_AUXB 5
168*4882a593Smuzhiyun #define ESS_RECSRC_LINE 6
169*4882a593Smuzhiyun #define ESS_RECSRC_NONE 7
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun #define DAC1 0x01
172*4882a593Smuzhiyun #define ADC1 0x02
173*4882a593Smuzhiyun #define DAC2 0x04
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /*
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun */
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun #define SAVED_REG_SIZE 32 /* max. number of registers to save */
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun struct es1938 {
182*4882a593Smuzhiyun int irq;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun unsigned long io_port;
185*4882a593Smuzhiyun unsigned long sb_port;
186*4882a593Smuzhiyun unsigned long vc_port;
187*4882a593Smuzhiyun unsigned long mpu_port;
188*4882a593Smuzhiyun unsigned long game_port;
189*4882a593Smuzhiyun unsigned long ddma_port;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun unsigned char irqmask;
192*4882a593Smuzhiyun unsigned char revision;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun struct snd_kcontrol *hw_volume;
195*4882a593Smuzhiyun struct snd_kcontrol *hw_switch;
196*4882a593Smuzhiyun struct snd_kcontrol *master_volume;
197*4882a593Smuzhiyun struct snd_kcontrol *master_switch;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun struct pci_dev *pci;
200*4882a593Smuzhiyun struct snd_card *card;
201*4882a593Smuzhiyun struct snd_pcm *pcm;
202*4882a593Smuzhiyun struct snd_pcm_substream *capture_substream;
203*4882a593Smuzhiyun struct snd_pcm_substream *playback1_substream;
204*4882a593Smuzhiyun struct snd_pcm_substream *playback2_substream;
205*4882a593Smuzhiyun struct snd_rawmidi *rmidi;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun unsigned int dma1_size;
208*4882a593Smuzhiyun unsigned int dma2_size;
209*4882a593Smuzhiyun unsigned int dma1_start;
210*4882a593Smuzhiyun unsigned int dma2_start;
211*4882a593Smuzhiyun unsigned int dma1_shift;
212*4882a593Smuzhiyun unsigned int dma2_shift;
213*4882a593Smuzhiyun unsigned int last_capture_dmaaddr;
214*4882a593Smuzhiyun unsigned int active;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun spinlock_t reg_lock;
217*4882a593Smuzhiyun spinlock_t mixer_lock;
218*4882a593Smuzhiyun struct snd_info_entry *proc_entry;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun #ifdef SUPPORT_JOYSTICK
221*4882a593Smuzhiyun struct gameport *gameport;
222*4882a593Smuzhiyun #endif
223*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
224*4882a593Smuzhiyun unsigned char saved_regs[SAVED_REG_SIZE];
225*4882a593Smuzhiyun #endif
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun static irqreturn_t snd_es1938_interrupt(int irq, void *dev_id);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun static const struct pci_device_id snd_es1938_ids[] = {
231*4882a593Smuzhiyun { PCI_VDEVICE(ESS, 0x1969), 0, }, /* Solo-1 */
232*4882a593Smuzhiyun { 0, }
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, snd_es1938_ids);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun #define RESET_LOOP_TIMEOUT 0x10000
238*4882a593Smuzhiyun #define WRITE_LOOP_TIMEOUT 0x10000
239*4882a593Smuzhiyun #define GET_LOOP_TIMEOUT 0x01000
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /* -----------------------------------------------------------------
242*4882a593Smuzhiyun * Write to a mixer register
243*4882a593Smuzhiyun * -----------------------------------------------------------------*/
snd_es1938_mixer_write(struct es1938 * chip,unsigned char reg,unsigned char val)244*4882a593Smuzhiyun static void snd_es1938_mixer_write(struct es1938 *chip, unsigned char reg, unsigned char val)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun unsigned long flags;
247*4882a593Smuzhiyun spin_lock_irqsave(&chip->mixer_lock, flags);
248*4882a593Smuzhiyun outb(reg, SLSB_REG(chip, MIXERADDR));
249*4882a593Smuzhiyun outb(val, SLSB_REG(chip, MIXERDATA));
250*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->mixer_lock, flags);
251*4882a593Smuzhiyun dev_dbg(chip->card->dev, "Mixer reg %02x set to %02x\n", reg, val);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun /* -----------------------------------------------------------------
255*4882a593Smuzhiyun * Read from a mixer register
256*4882a593Smuzhiyun * -----------------------------------------------------------------*/
snd_es1938_mixer_read(struct es1938 * chip,unsigned char reg)257*4882a593Smuzhiyun static int snd_es1938_mixer_read(struct es1938 *chip, unsigned char reg)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun int data;
260*4882a593Smuzhiyun unsigned long flags;
261*4882a593Smuzhiyun spin_lock_irqsave(&chip->mixer_lock, flags);
262*4882a593Smuzhiyun outb(reg, SLSB_REG(chip, MIXERADDR));
263*4882a593Smuzhiyun data = inb(SLSB_REG(chip, MIXERDATA));
264*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->mixer_lock, flags);
265*4882a593Smuzhiyun dev_dbg(chip->card->dev, "Mixer reg %02x now is %02x\n", reg, data);
266*4882a593Smuzhiyun return data;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /* -----------------------------------------------------------------
270*4882a593Smuzhiyun * Write to some bits of a mixer register (return old value)
271*4882a593Smuzhiyun * -----------------------------------------------------------------*/
snd_es1938_mixer_bits(struct es1938 * chip,unsigned char reg,unsigned char mask,unsigned char val)272*4882a593Smuzhiyun static int snd_es1938_mixer_bits(struct es1938 *chip, unsigned char reg,
273*4882a593Smuzhiyun unsigned char mask, unsigned char val)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun unsigned long flags;
276*4882a593Smuzhiyun unsigned char old, new, oval;
277*4882a593Smuzhiyun spin_lock_irqsave(&chip->mixer_lock, flags);
278*4882a593Smuzhiyun outb(reg, SLSB_REG(chip, MIXERADDR));
279*4882a593Smuzhiyun old = inb(SLSB_REG(chip, MIXERDATA));
280*4882a593Smuzhiyun oval = old & mask;
281*4882a593Smuzhiyun if (val != oval) {
282*4882a593Smuzhiyun new = (old & ~mask) | (val & mask);
283*4882a593Smuzhiyun outb(new, SLSB_REG(chip, MIXERDATA));
284*4882a593Smuzhiyun dev_dbg(chip->card->dev,
285*4882a593Smuzhiyun "Mixer reg %02x was %02x, set to %02x\n",
286*4882a593Smuzhiyun reg, old, new);
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->mixer_lock, flags);
289*4882a593Smuzhiyun return oval;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun /* -----------------------------------------------------------------
293*4882a593Smuzhiyun * Write command to Controller Registers
294*4882a593Smuzhiyun * -----------------------------------------------------------------*/
snd_es1938_write_cmd(struct es1938 * chip,unsigned char cmd)295*4882a593Smuzhiyun static void snd_es1938_write_cmd(struct es1938 *chip, unsigned char cmd)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun int i;
298*4882a593Smuzhiyun unsigned char v;
299*4882a593Smuzhiyun for (i = 0; i < WRITE_LOOP_TIMEOUT; i++) {
300*4882a593Smuzhiyun if (!(v = inb(SLSB_REG(chip, READSTATUS)) & 0x80)) {
301*4882a593Smuzhiyun outb(cmd, SLSB_REG(chip, WRITEDATA));
302*4882a593Smuzhiyun return;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun dev_err(chip->card->dev,
306*4882a593Smuzhiyun "snd_es1938_write_cmd timeout (0x02%x/0x02%x)\n", cmd, v);
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun /* -----------------------------------------------------------------
310*4882a593Smuzhiyun * Read the Read Data Buffer
311*4882a593Smuzhiyun * -----------------------------------------------------------------*/
snd_es1938_get_byte(struct es1938 * chip)312*4882a593Smuzhiyun static int snd_es1938_get_byte(struct es1938 *chip)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun int i;
315*4882a593Smuzhiyun unsigned char v;
316*4882a593Smuzhiyun for (i = GET_LOOP_TIMEOUT; i; i--)
317*4882a593Smuzhiyun if ((v = inb(SLSB_REG(chip, STATUS))) & 0x80)
318*4882a593Smuzhiyun return inb(SLSB_REG(chip, READDATA));
319*4882a593Smuzhiyun dev_err(chip->card->dev, "get_byte timeout: status 0x02%x\n", v);
320*4882a593Smuzhiyun return -ENODEV;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun /* -----------------------------------------------------------------
324*4882a593Smuzhiyun * Write value cmd register
325*4882a593Smuzhiyun * -----------------------------------------------------------------*/
snd_es1938_write(struct es1938 * chip,unsigned char reg,unsigned char val)326*4882a593Smuzhiyun static void snd_es1938_write(struct es1938 *chip, unsigned char reg, unsigned char val)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun unsigned long flags;
329*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
330*4882a593Smuzhiyun snd_es1938_write_cmd(chip, reg);
331*4882a593Smuzhiyun snd_es1938_write_cmd(chip, val);
332*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
333*4882a593Smuzhiyun dev_dbg(chip->card->dev, "Reg %02x set to %02x\n", reg, val);
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun /* -----------------------------------------------------------------
337*4882a593Smuzhiyun * Read data from cmd register and return it
338*4882a593Smuzhiyun * -----------------------------------------------------------------*/
snd_es1938_read(struct es1938 * chip,unsigned char reg)339*4882a593Smuzhiyun static unsigned char snd_es1938_read(struct es1938 *chip, unsigned char reg)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun unsigned char val;
342*4882a593Smuzhiyun unsigned long flags;
343*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
344*4882a593Smuzhiyun snd_es1938_write_cmd(chip, ESS_CMD_READREG);
345*4882a593Smuzhiyun snd_es1938_write_cmd(chip, reg);
346*4882a593Smuzhiyun val = snd_es1938_get_byte(chip);
347*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
348*4882a593Smuzhiyun dev_dbg(chip->card->dev, "Reg %02x now is %02x\n", reg, val);
349*4882a593Smuzhiyun return val;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun /* -----------------------------------------------------------------
353*4882a593Smuzhiyun * Write data to cmd register and return old value
354*4882a593Smuzhiyun * -----------------------------------------------------------------*/
snd_es1938_bits(struct es1938 * chip,unsigned char reg,unsigned char mask,unsigned char val)355*4882a593Smuzhiyun static int snd_es1938_bits(struct es1938 *chip, unsigned char reg, unsigned char mask,
356*4882a593Smuzhiyun unsigned char val)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun unsigned long flags;
359*4882a593Smuzhiyun unsigned char old, new, oval;
360*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
361*4882a593Smuzhiyun snd_es1938_write_cmd(chip, ESS_CMD_READREG);
362*4882a593Smuzhiyun snd_es1938_write_cmd(chip, reg);
363*4882a593Smuzhiyun old = snd_es1938_get_byte(chip);
364*4882a593Smuzhiyun oval = old & mask;
365*4882a593Smuzhiyun if (val != oval) {
366*4882a593Smuzhiyun snd_es1938_write_cmd(chip, reg);
367*4882a593Smuzhiyun new = (old & ~mask) | (val & mask);
368*4882a593Smuzhiyun snd_es1938_write_cmd(chip, new);
369*4882a593Smuzhiyun dev_dbg(chip->card->dev, "Reg %02x was %02x, set to %02x\n",
370*4882a593Smuzhiyun reg, old, new);
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
373*4882a593Smuzhiyun return oval;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun /* --------------------------------------------------------------------
377*4882a593Smuzhiyun * Reset the chip
378*4882a593Smuzhiyun * --------------------------------------------------------------------*/
snd_es1938_reset(struct es1938 * chip)379*4882a593Smuzhiyun static void snd_es1938_reset(struct es1938 *chip)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun int i;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun outb(3, SLSB_REG(chip, RESET));
384*4882a593Smuzhiyun inb(SLSB_REG(chip, RESET));
385*4882a593Smuzhiyun outb(0, SLSB_REG(chip, RESET));
386*4882a593Smuzhiyun for (i = 0; i < RESET_LOOP_TIMEOUT; i++) {
387*4882a593Smuzhiyun if (inb(SLSB_REG(chip, STATUS)) & 0x80) {
388*4882a593Smuzhiyun if (inb(SLSB_REG(chip, READDATA)) == 0xaa)
389*4882a593Smuzhiyun goto __next;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun dev_err(chip->card->dev, "ESS Solo-1 reset failed\n");
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun __next:
395*4882a593Smuzhiyun snd_es1938_write_cmd(chip, ESS_CMD_ENABLEEXT);
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun /* Demand transfer DMA: 4 bytes per DMA request */
398*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_DMATYPE, 2);
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun /* Change behaviour of register A1
401*4882a593Smuzhiyun 4x oversampling
402*4882a593Smuzhiyun 2nd channel DAC asynchronous */
403*4882a593Smuzhiyun snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2MODE, 0x32);
404*4882a593Smuzhiyun /* enable/select DMA channel and IRQ channel */
405*4882a593Smuzhiyun snd_es1938_bits(chip, ESS_CMD_IRQCONTROL, 0xf0, 0x50);
406*4882a593Smuzhiyun snd_es1938_bits(chip, ESS_CMD_DRQCONTROL, 0xf0, 0x50);
407*4882a593Smuzhiyun snd_es1938_write_cmd(chip, ESS_CMD_ENABLEAUDIO1);
408*4882a593Smuzhiyun /* Set spatializer parameters to recommended values */
409*4882a593Smuzhiyun snd_es1938_mixer_write(chip, 0x54, 0x8f);
410*4882a593Smuzhiyun snd_es1938_mixer_write(chip, 0x56, 0x95);
411*4882a593Smuzhiyun snd_es1938_mixer_write(chip, 0x58, 0x94);
412*4882a593Smuzhiyun snd_es1938_mixer_write(chip, 0x5a, 0x80);
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun /* --------------------------------------------------------------------
416*4882a593Smuzhiyun * Reset the FIFOs
417*4882a593Smuzhiyun * --------------------------------------------------------------------*/
snd_es1938_reset_fifo(struct es1938 * chip)418*4882a593Smuzhiyun static void snd_es1938_reset_fifo(struct es1938 *chip)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun outb(2, SLSB_REG(chip, RESET));
421*4882a593Smuzhiyun outb(0, SLSB_REG(chip, RESET));
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun static const struct snd_ratnum clocks[2] = {
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun .num = 793800,
427*4882a593Smuzhiyun .den_min = 1,
428*4882a593Smuzhiyun .den_max = 128,
429*4882a593Smuzhiyun .den_step = 1,
430*4882a593Smuzhiyun },
431*4882a593Smuzhiyun {
432*4882a593Smuzhiyun .num = 768000,
433*4882a593Smuzhiyun .den_min = 1,
434*4882a593Smuzhiyun .den_max = 128,
435*4882a593Smuzhiyun .den_step = 1,
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun };
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_ratnums hw_constraints_clocks = {
440*4882a593Smuzhiyun .nrats = 2,
441*4882a593Smuzhiyun .rats = clocks,
442*4882a593Smuzhiyun };
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun
snd_es1938_rate_set(struct es1938 * chip,struct snd_pcm_substream * substream,int mode)445*4882a593Smuzhiyun static void snd_es1938_rate_set(struct es1938 *chip,
446*4882a593Smuzhiyun struct snd_pcm_substream *substream,
447*4882a593Smuzhiyun int mode)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun unsigned int bits, div0;
450*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
451*4882a593Smuzhiyun if (runtime->rate_num == clocks[0].num)
452*4882a593Smuzhiyun bits = 128 - runtime->rate_den;
453*4882a593Smuzhiyun else
454*4882a593Smuzhiyun bits = 256 - runtime->rate_den;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun /* set filter register */
457*4882a593Smuzhiyun div0 = 256 - 7160000*20/(8*82*runtime->rate);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun if (mode == DAC2) {
460*4882a593Smuzhiyun snd_es1938_mixer_write(chip, 0x70, bits);
461*4882a593Smuzhiyun snd_es1938_mixer_write(chip, 0x72, div0);
462*4882a593Smuzhiyun } else {
463*4882a593Smuzhiyun snd_es1938_write(chip, 0xA1, bits);
464*4882a593Smuzhiyun snd_es1938_write(chip, 0xA2, div0);
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun /* --------------------------------------------------------------------
469*4882a593Smuzhiyun * Configure Solo1 builtin DMA Controller
470*4882a593Smuzhiyun * --------------------------------------------------------------------*/
471*4882a593Smuzhiyun
snd_es1938_playback1_setdma(struct es1938 * chip)472*4882a593Smuzhiyun static void snd_es1938_playback1_setdma(struct es1938 *chip)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun outb(0x00, SLIO_REG(chip, AUDIO2MODE));
475*4882a593Smuzhiyun outl(chip->dma2_start, SLIO_REG(chip, AUDIO2DMAADDR));
476*4882a593Smuzhiyun outw(0, SLIO_REG(chip, AUDIO2DMACOUNT));
477*4882a593Smuzhiyun outw(chip->dma2_size, SLIO_REG(chip, AUDIO2DMACOUNT));
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun
snd_es1938_playback2_setdma(struct es1938 * chip)480*4882a593Smuzhiyun static void snd_es1938_playback2_setdma(struct es1938 *chip)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun /* Enable DMA controller */
483*4882a593Smuzhiyun outb(0xc4, SLDM_REG(chip, DMACOMMAND));
484*4882a593Smuzhiyun /* 1. Master reset */
485*4882a593Smuzhiyun outb(0, SLDM_REG(chip, DMACLEAR));
486*4882a593Smuzhiyun /* 2. Mask DMA */
487*4882a593Smuzhiyun outb(1, SLDM_REG(chip, DMAMASK));
488*4882a593Smuzhiyun outb(0x18, SLDM_REG(chip, DMAMODE));
489*4882a593Smuzhiyun outl(chip->dma1_start, SLDM_REG(chip, DMAADDR));
490*4882a593Smuzhiyun outw(chip->dma1_size - 1, SLDM_REG(chip, DMACOUNT));
491*4882a593Smuzhiyun /* 3. Unmask DMA */
492*4882a593Smuzhiyun outb(0, SLDM_REG(chip, DMAMASK));
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun
snd_es1938_capture_setdma(struct es1938 * chip)495*4882a593Smuzhiyun static void snd_es1938_capture_setdma(struct es1938 *chip)
496*4882a593Smuzhiyun {
497*4882a593Smuzhiyun /* Enable DMA controller */
498*4882a593Smuzhiyun outb(0xc4, SLDM_REG(chip, DMACOMMAND));
499*4882a593Smuzhiyun /* 1. Master reset */
500*4882a593Smuzhiyun outb(0, SLDM_REG(chip, DMACLEAR));
501*4882a593Smuzhiyun /* 2. Mask DMA */
502*4882a593Smuzhiyun outb(1, SLDM_REG(chip, DMAMASK));
503*4882a593Smuzhiyun outb(0x14, SLDM_REG(chip, DMAMODE));
504*4882a593Smuzhiyun outl(chip->dma1_start, SLDM_REG(chip, DMAADDR));
505*4882a593Smuzhiyun chip->last_capture_dmaaddr = chip->dma1_start;
506*4882a593Smuzhiyun outw(chip->dma1_size - 1, SLDM_REG(chip, DMACOUNT));
507*4882a593Smuzhiyun /* 3. Unmask DMA */
508*4882a593Smuzhiyun outb(0, SLDM_REG(chip, DMAMASK));
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun /* ----------------------------------------------------------------------
512*4882a593Smuzhiyun *
513*4882a593Smuzhiyun * *** PCM part ***
514*4882a593Smuzhiyun */
515*4882a593Smuzhiyun
snd_es1938_capture_trigger(struct snd_pcm_substream * substream,int cmd)516*4882a593Smuzhiyun static int snd_es1938_capture_trigger(struct snd_pcm_substream *substream,
517*4882a593Smuzhiyun int cmd)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
520*4882a593Smuzhiyun int val;
521*4882a593Smuzhiyun switch (cmd) {
522*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
523*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
524*4882a593Smuzhiyun val = 0x0f;
525*4882a593Smuzhiyun chip->active |= ADC1;
526*4882a593Smuzhiyun break;
527*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
528*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
529*4882a593Smuzhiyun val = 0x00;
530*4882a593Smuzhiyun chip->active &= ~ADC1;
531*4882a593Smuzhiyun break;
532*4882a593Smuzhiyun default:
533*4882a593Smuzhiyun return -EINVAL;
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_DMACONTROL, val);
536*4882a593Smuzhiyun return 0;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
snd_es1938_playback1_trigger(struct snd_pcm_substream * substream,int cmd)539*4882a593Smuzhiyun static int snd_es1938_playback1_trigger(struct snd_pcm_substream *substream,
540*4882a593Smuzhiyun int cmd)
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
543*4882a593Smuzhiyun switch (cmd) {
544*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
545*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
546*4882a593Smuzhiyun /* According to the documentation this should be:
547*4882a593Smuzhiyun 0x13 but that value may randomly swap stereo channels */
548*4882a593Smuzhiyun snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0x92);
549*4882a593Smuzhiyun udelay(10);
550*4882a593Smuzhiyun snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0x93);
551*4882a593Smuzhiyun /* This two stage init gives the FIFO -> DAC connection time to
552*4882a593Smuzhiyun * settle before first data from DMA flows in. This should ensure
553*4882a593Smuzhiyun * no swapping of stereo channels. Report a bug if otherwise :-) */
554*4882a593Smuzhiyun outb(0x0a, SLIO_REG(chip, AUDIO2MODE));
555*4882a593Smuzhiyun chip->active |= DAC2;
556*4882a593Smuzhiyun break;
557*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
558*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
559*4882a593Smuzhiyun outb(0, SLIO_REG(chip, AUDIO2MODE));
560*4882a593Smuzhiyun snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0);
561*4882a593Smuzhiyun chip->active &= ~DAC2;
562*4882a593Smuzhiyun break;
563*4882a593Smuzhiyun default:
564*4882a593Smuzhiyun return -EINVAL;
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun return 0;
567*4882a593Smuzhiyun }
568*4882a593Smuzhiyun
snd_es1938_playback2_trigger(struct snd_pcm_substream * substream,int cmd)569*4882a593Smuzhiyun static int snd_es1938_playback2_trigger(struct snd_pcm_substream *substream,
570*4882a593Smuzhiyun int cmd)
571*4882a593Smuzhiyun {
572*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
573*4882a593Smuzhiyun int val;
574*4882a593Smuzhiyun switch (cmd) {
575*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
576*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
577*4882a593Smuzhiyun val = 5;
578*4882a593Smuzhiyun chip->active |= DAC1;
579*4882a593Smuzhiyun break;
580*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
581*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
582*4882a593Smuzhiyun val = 0;
583*4882a593Smuzhiyun chip->active &= ~DAC1;
584*4882a593Smuzhiyun break;
585*4882a593Smuzhiyun default:
586*4882a593Smuzhiyun return -EINVAL;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_DMACONTROL, val);
589*4882a593Smuzhiyun return 0;
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun
snd_es1938_playback_trigger(struct snd_pcm_substream * substream,int cmd)592*4882a593Smuzhiyun static int snd_es1938_playback_trigger(struct snd_pcm_substream *substream,
593*4882a593Smuzhiyun int cmd)
594*4882a593Smuzhiyun {
595*4882a593Smuzhiyun switch (substream->number) {
596*4882a593Smuzhiyun case 0:
597*4882a593Smuzhiyun return snd_es1938_playback1_trigger(substream, cmd);
598*4882a593Smuzhiyun case 1:
599*4882a593Smuzhiyun return snd_es1938_playback2_trigger(substream, cmd);
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun snd_BUG();
602*4882a593Smuzhiyun return -EINVAL;
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun /* --------------------------------------------------------------------
606*4882a593Smuzhiyun * First channel for Extended Mode Audio 1 ADC Operation
607*4882a593Smuzhiyun * --------------------------------------------------------------------*/
snd_es1938_capture_prepare(struct snd_pcm_substream * substream)608*4882a593Smuzhiyun static int snd_es1938_capture_prepare(struct snd_pcm_substream *substream)
609*4882a593Smuzhiyun {
610*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
611*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
612*4882a593Smuzhiyun int u, is8, mono;
613*4882a593Smuzhiyun unsigned int size = snd_pcm_lib_buffer_bytes(substream);
614*4882a593Smuzhiyun unsigned int count = snd_pcm_lib_period_bytes(substream);
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun chip->dma1_size = size;
617*4882a593Smuzhiyun chip->dma1_start = runtime->dma_addr;
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun mono = (runtime->channels > 1) ? 0 : 1;
620*4882a593Smuzhiyun is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1;
621*4882a593Smuzhiyun u = snd_pcm_format_unsigned(runtime->format);
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun chip->dma1_shift = 2 - mono - is8;
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun snd_es1938_reset_fifo(chip);
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun /* program type */
628*4882a593Smuzhiyun snd_es1938_bits(chip, ESS_CMD_ANALOGCONTROL, 0x03, (mono ? 2 : 1));
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun /* set clock and counters */
631*4882a593Smuzhiyun snd_es1938_rate_set(chip, substream, ADC1);
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun count = 0x10000 - count;
634*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_DMACNTRELOADL, count & 0xff);
635*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_DMACNTRELOADH, count >> 8);
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun /* initialize and configure ADC */
638*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_SETFORMAT2, u ? 0x51 : 0x71);
639*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_SETFORMAT2, 0x90 |
640*4882a593Smuzhiyun (u ? 0x00 : 0x20) |
641*4882a593Smuzhiyun (is8 ? 0x00 : 0x04) |
642*4882a593Smuzhiyun (mono ? 0x40 : 0x08));
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun // snd_es1938_reset_fifo(chip);
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun /* 11. configure system interrupt controller and DMA controller */
647*4882a593Smuzhiyun snd_es1938_capture_setdma(chip);
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun return 0;
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun /* ------------------------------------------------------------------------------
654*4882a593Smuzhiyun * Second Audio channel DAC Operation
655*4882a593Smuzhiyun * ------------------------------------------------------------------------------*/
snd_es1938_playback1_prepare(struct snd_pcm_substream * substream)656*4882a593Smuzhiyun static int snd_es1938_playback1_prepare(struct snd_pcm_substream *substream)
657*4882a593Smuzhiyun {
658*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
659*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
660*4882a593Smuzhiyun int u, is8, mono;
661*4882a593Smuzhiyun unsigned int size = snd_pcm_lib_buffer_bytes(substream);
662*4882a593Smuzhiyun unsigned int count = snd_pcm_lib_period_bytes(substream);
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun chip->dma2_size = size;
665*4882a593Smuzhiyun chip->dma2_start = runtime->dma_addr;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun mono = (runtime->channels > 1) ? 0 : 1;
668*4882a593Smuzhiyun is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1;
669*4882a593Smuzhiyun u = snd_pcm_format_unsigned(runtime->format);
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun chip->dma2_shift = 2 - mono - is8;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun snd_es1938_reset_fifo(chip);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun /* set clock and counters */
676*4882a593Smuzhiyun snd_es1938_rate_set(chip, substream, DAC2);
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun count >>= 1;
679*4882a593Smuzhiyun count = 0x10000 - count;
680*4882a593Smuzhiyun snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2TCOUNTL, count & 0xff);
681*4882a593Smuzhiyun snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2TCOUNTH, count >> 8);
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun /* initialize and configure Audio 2 DAC */
684*4882a593Smuzhiyun snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL2, 0x40 | (u ? 0 : 4) |
685*4882a593Smuzhiyun (mono ? 0 : 2) | (is8 ? 0 : 1));
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun /* program DMA */
688*4882a593Smuzhiyun snd_es1938_playback1_setdma(chip);
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun return 0;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
snd_es1938_playback2_prepare(struct snd_pcm_substream * substream)693*4882a593Smuzhiyun static int snd_es1938_playback2_prepare(struct snd_pcm_substream *substream)
694*4882a593Smuzhiyun {
695*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
696*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
697*4882a593Smuzhiyun int u, is8, mono;
698*4882a593Smuzhiyun unsigned int size = snd_pcm_lib_buffer_bytes(substream);
699*4882a593Smuzhiyun unsigned int count = snd_pcm_lib_period_bytes(substream);
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun chip->dma1_size = size;
702*4882a593Smuzhiyun chip->dma1_start = runtime->dma_addr;
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun mono = (runtime->channels > 1) ? 0 : 1;
705*4882a593Smuzhiyun is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1;
706*4882a593Smuzhiyun u = snd_pcm_format_unsigned(runtime->format);
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun chip->dma1_shift = 2 - mono - is8;
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun count = 0x10000 - count;
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun /* reset */
713*4882a593Smuzhiyun snd_es1938_reset_fifo(chip);
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun snd_es1938_bits(chip, ESS_CMD_ANALOGCONTROL, 0x03, (mono ? 2 : 1));
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun /* set clock and counters */
718*4882a593Smuzhiyun snd_es1938_rate_set(chip, substream, DAC1);
719*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_DMACNTRELOADL, count & 0xff);
720*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_DMACNTRELOADH, count >> 8);
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun /* initialized and configure DAC */
723*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_SETFORMAT, u ? 0x80 : 0x00);
724*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_SETFORMAT, u ? 0x51 : 0x71);
725*4882a593Smuzhiyun snd_es1938_write(chip, ESS_CMD_SETFORMAT2,
726*4882a593Smuzhiyun 0x90 | (mono ? 0x40 : 0x08) |
727*4882a593Smuzhiyun (is8 ? 0x00 : 0x04) | (u ? 0x00 : 0x20));
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun /* program DMA */
730*4882a593Smuzhiyun snd_es1938_playback2_setdma(chip);
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun return 0;
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun
snd_es1938_playback_prepare(struct snd_pcm_substream * substream)735*4882a593Smuzhiyun static int snd_es1938_playback_prepare(struct snd_pcm_substream *substream)
736*4882a593Smuzhiyun {
737*4882a593Smuzhiyun switch (substream->number) {
738*4882a593Smuzhiyun case 0:
739*4882a593Smuzhiyun return snd_es1938_playback1_prepare(substream);
740*4882a593Smuzhiyun case 1:
741*4882a593Smuzhiyun return snd_es1938_playback2_prepare(substream);
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun snd_BUG();
744*4882a593Smuzhiyun return -EINVAL;
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun /* during the incrementing of dma counters the DMA register reads sometimes
748*4882a593Smuzhiyun returns garbage. To ensure a valid hw pointer, the following checks which
749*4882a593Smuzhiyun should be very unlikely to fail are used:
750*4882a593Smuzhiyun - is the current DMA address in the valid DMA range ?
751*4882a593Smuzhiyun - is the sum of DMA address and DMA counter pointing to the last DMA byte ?
752*4882a593Smuzhiyun One can argue this could differ by one byte depending on which register is
753*4882a593Smuzhiyun updated first, so the implementation below allows for that.
754*4882a593Smuzhiyun */
snd_es1938_capture_pointer(struct snd_pcm_substream * substream)755*4882a593Smuzhiyun static snd_pcm_uframes_t snd_es1938_capture_pointer(struct snd_pcm_substream *substream)
756*4882a593Smuzhiyun {
757*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
758*4882a593Smuzhiyun size_t ptr;
759*4882a593Smuzhiyun #if 0
760*4882a593Smuzhiyun size_t old, new;
761*4882a593Smuzhiyun /* This stuff is *needed*, don't ask why - AB */
762*4882a593Smuzhiyun old = inw(SLDM_REG(chip, DMACOUNT));
763*4882a593Smuzhiyun while ((new = inw(SLDM_REG(chip, DMACOUNT))) != old)
764*4882a593Smuzhiyun old = new;
765*4882a593Smuzhiyun ptr = chip->dma1_size - 1 - new;
766*4882a593Smuzhiyun #else
767*4882a593Smuzhiyun size_t count;
768*4882a593Smuzhiyun unsigned int diff;
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun ptr = inl(SLDM_REG(chip, DMAADDR));
771*4882a593Smuzhiyun count = inw(SLDM_REG(chip, DMACOUNT));
772*4882a593Smuzhiyun diff = chip->dma1_start + chip->dma1_size - ptr - count;
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun if (diff > 3 || ptr < chip->dma1_start
775*4882a593Smuzhiyun || ptr >= chip->dma1_start+chip->dma1_size)
776*4882a593Smuzhiyun ptr = chip->last_capture_dmaaddr; /* bad, use last saved */
777*4882a593Smuzhiyun else
778*4882a593Smuzhiyun chip->last_capture_dmaaddr = ptr; /* good, remember it */
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun ptr -= chip->dma1_start;
781*4882a593Smuzhiyun #endif
782*4882a593Smuzhiyun return ptr >> chip->dma1_shift;
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun
snd_es1938_playback1_pointer(struct snd_pcm_substream * substream)785*4882a593Smuzhiyun static snd_pcm_uframes_t snd_es1938_playback1_pointer(struct snd_pcm_substream *substream)
786*4882a593Smuzhiyun {
787*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
788*4882a593Smuzhiyun size_t ptr;
789*4882a593Smuzhiyun #if 1
790*4882a593Smuzhiyun ptr = chip->dma2_size - inw(SLIO_REG(chip, AUDIO2DMACOUNT));
791*4882a593Smuzhiyun #else
792*4882a593Smuzhiyun ptr = inl(SLIO_REG(chip, AUDIO2DMAADDR)) - chip->dma2_start;
793*4882a593Smuzhiyun #endif
794*4882a593Smuzhiyun return ptr >> chip->dma2_shift;
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun
snd_es1938_playback2_pointer(struct snd_pcm_substream * substream)797*4882a593Smuzhiyun static snd_pcm_uframes_t snd_es1938_playback2_pointer(struct snd_pcm_substream *substream)
798*4882a593Smuzhiyun {
799*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
800*4882a593Smuzhiyun size_t ptr;
801*4882a593Smuzhiyun size_t old, new;
802*4882a593Smuzhiyun #if 1
803*4882a593Smuzhiyun /* This stuff is *needed*, don't ask why - AB */
804*4882a593Smuzhiyun old = inw(SLDM_REG(chip, DMACOUNT));
805*4882a593Smuzhiyun while ((new = inw(SLDM_REG(chip, DMACOUNT))) != old)
806*4882a593Smuzhiyun old = new;
807*4882a593Smuzhiyun ptr = chip->dma1_size - 1 - new;
808*4882a593Smuzhiyun #else
809*4882a593Smuzhiyun ptr = inl(SLDM_REG(chip, DMAADDR)) - chip->dma1_start;
810*4882a593Smuzhiyun #endif
811*4882a593Smuzhiyun return ptr >> chip->dma1_shift;
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun
snd_es1938_playback_pointer(struct snd_pcm_substream * substream)814*4882a593Smuzhiyun static snd_pcm_uframes_t snd_es1938_playback_pointer(struct snd_pcm_substream *substream)
815*4882a593Smuzhiyun {
816*4882a593Smuzhiyun switch (substream->number) {
817*4882a593Smuzhiyun case 0:
818*4882a593Smuzhiyun return snd_es1938_playback1_pointer(substream);
819*4882a593Smuzhiyun case 1:
820*4882a593Smuzhiyun return snd_es1938_playback2_pointer(substream);
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun snd_BUG();
823*4882a593Smuzhiyun return -EINVAL;
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun
snd_es1938_capture_copy(struct snd_pcm_substream * substream,int channel,unsigned long pos,void __user * dst,unsigned long count)826*4882a593Smuzhiyun static int snd_es1938_capture_copy(struct snd_pcm_substream *substream,
827*4882a593Smuzhiyun int channel, unsigned long pos,
828*4882a593Smuzhiyun void __user *dst, unsigned long count)
829*4882a593Smuzhiyun {
830*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
831*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun if (snd_BUG_ON(pos + count > chip->dma1_size))
834*4882a593Smuzhiyun return -EINVAL;
835*4882a593Smuzhiyun if (pos + count < chip->dma1_size) {
836*4882a593Smuzhiyun if (copy_to_user(dst, runtime->dma_area + pos + 1, count))
837*4882a593Smuzhiyun return -EFAULT;
838*4882a593Smuzhiyun } else {
839*4882a593Smuzhiyun if (copy_to_user(dst, runtime->dma_area + pos + 1, count - 1))
840*4882a593Smuzhiyun return -EFAULT;
841*4882a593Smuzhiyun if (put_user(runtime->dma_area[0],
842*4882a593Smuzhiyun ((unsigned char __user *)dst) + count - 1))
843*4882a593Smuzhiyun return -EFAULT;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun return 0;
846*4882a593Smuzhiyun }
847*4882a593Smuzhiyun
snd_es1938_capture_copy_kernel(struct snd_pcm_substream * substream,int channel,unsigned long pos,void * dst,unsigned long count)848*4882a593Smuzhiyun static int snd_es1938_capture_copy_kernel(struct snd_pcm_substream *substream,
849*4882a593Smuzhiyun int channel, unsigned long pos,
850*4882a593Smuzhiyun void *dst, unsigned long count)
851*4882a593Smuzhiyun {
852*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
853*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun if (snd_BUG_ON(pos + count > chip->dma1_size))
856*4882a593Smuzhiyun return -EINVAL;
857*4882a593Smuzhiyun if (pos + count < chip->dma1_size) {
858*4882a593Smuzhiyun memcpy(dst, runtime->dma_area + pos + 1, count);
859*4882a593Smuzhiyun } else {
860*4882a593Smuzhiyun memcpy(dst, runtime->dma_area + pos + 1, count - 1);
861*4882a593Smuzhiyun runtime->dma_area[0] = *((unsigned char *)dst + count - 1);
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun return 0;
864*4882a593Smuzhiyun }
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun /* ----------------------------------------------------------------------
867*4882a593Smuzhiyun * Audio1 Capture (ADC)
868*4882a593Smuzhiyun * ----------------------------------------------------------------------*/
869*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_es1938_capture =
870*4882a593Smuzhiyun {
871*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_INTERLEAVED |
872*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER),
873*4882a593Smuzhiyun .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
874*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE),
875*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
876*4882a593Smuzhiyun .rate_min = 6000,
877*4882a593Smuzhiyun .rate_max = 48000,
878*4882a593Smuzhiyun .channels_min = 1,
879*4882a593Smuzhiyun .channels_max = 2,
880*4882a593Smuzhiyun .buffer_bytes_max = 0x8000, /* DMA controller screws on higher values */
881*4882a593Smuzhiyun .period_bytes_min = 64,
882*4882a593Smuzhiyun .period_bytes_max = 0x8000,
883*4882a593Smuzhiyun .periods_min = 1,
884*4882a593Smuzhiyun .periods_max = 1024,
885*4882a593Smuzhiyun .fifo_size = 256,
886*4882a593Smuzhiyun };
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun /* -----------------------------------------------------------------------
889*4882a593Smuzhiyun * Audio2 Playback (DAC)
890*4882a593Smuzhiyun * -----------------------------------------------------------------------*/
891*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_es1938_playback =
892*4882a593Smuzhiyun {
893*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
894*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
895*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID),
896*4882a593Smuzhiyun .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
897*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE),
898*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
899*4882a593Smuzhiyun .rate_min = 6000,
900*4882a593Smuzhiyun .rate_max = 48000,
901*4882a593Smuzhiyun .channels_min = 1,
902*4882a593Smuzhiyun .channels_max = 2,
903*4882a593Smuzhiyun .buffer_bytes_max = 0x8000, /* DMA controller screws on higher values */
904*4882a593Smuzhiyun .period_bytes_min = 64,
905*4882a593Smuzhiyun .period_bytes_max = 0x8000,
906*4882a593Smuzhiyun .periods_min = 1,
907*4882a593Smuzhiyun .periods_max = 1024,
908*4882a593Smuzhiyun .fifo_size = 256,
909*4882a593Smuzhiyun };
910*4882a593Smuzhiyun
snd_es1938_capture_open(struct snd_pcm_substream * substream)911*4882a593Smuzhiyun static int snd_es1938_capture_open(struct snd_pcm_substream *substream)
912*4882a593Smuzhiyun {
913*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
914*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun if (chip->playback2_substream)
917*4882a593Smuzhiyun return -EAGAIN;
918*4882a593Smuzhiyun chip->capture_substream = substream;
919*4882a593Smuzhiyun runtime->hw = snd_es1938_capture;
920*4882a593Smuzhiyun snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
921*4882a593Smuzhiyun &hw_constraints_clocks);
922*4882a593Smuzhiyun snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 0, 0xff00);
923*4882a593Smuzhiyun return 0;
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun
snd_es1938_playback_open(struct snd_pcm_substream * substream)926*4882a593Smuzhiyun static int snd_es1938_playback_open(struct snd_pcm_substream *substream)
927*4882a593Smuzhiyun {
928*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
929*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun switch (substream->number) {
932*4882a593Smuzhiyun case 0:
933*4882a593Smuzhiyun chip->playback1_substream = substream;
934*4882a593Smuzhiyun break;
935*4882a593Smuzhiyun case 1:
936*4882a593Smuzhiyun if (chip->capture_substream)
937*4882a593Smuzhiyun return -EAGAIN;
938*4882a593Smuzhiyun chip->playback2_substream = substream;
939*4882a593Smuzhiyun break;
940*4882a593Smuzhiyun default:
941*4882a593Smuzhiyun snd_BUG();
942*4882a593Smuzhiyun return -EINVAL;
943*4882a593Smuzhiyun }
944*4882a593Smuzhiyun runtime->hw = snd_es1938_playback;
945*4882a593Smuzhiyun snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
946*4882a593Smuzhiyun &hw_constraints_clocks);
947*4882a593Smuzhiyun snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 0, 0xff00);
948*4882a593Smuzhiyun return 0;
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun
snd_es1938_capture_close(struct snd_pcm_substream * substream)951*4882a593Smuzhiyun static int snd_es1938_capture_close(struct snd_pcm_substream *substream)
952*4882a593Smuzhiyun {
953*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun chip->capture_substream = NULL;
956*4882a593Smuzhiyun return 0;
957*4882a593Smuzhiyun }
958*4882a593Smuzhiyun
snd_es1938_playback_close(struct snd_pcm_substream * substream)959*4882a593Smuzhiyun static int snd_es1938_playback_close(struct snd_pcm_substream *substream)
960*4882a593Smuzhiyun {
961*4882a593Smuzhiyun struct es1938 *chip = snd_pcm_substream_chip(substream);
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun switch (substream->number) {
964*4882a593Smuzhiyun case 0:
965*4882a593Smuzhiyun chip->playback1_substream = NULL;
966*4882a593Smuzhiyun break;
967*4882a593Smuzhiyun case 1:
968*4882a593Smuzhiyun chip->playback2_substream = NULL;
969*4882a593Smuzhiyun break;
970*4882a593Smuzhiyun default:
971*4882a593Smuzhiyun snd_BUG();
972*4882a593Smuzhiyun return -EINVAL;
973*4882a593Smuzhiyun }
974*4882a593Smuzhiyun return 0;
975*4882a593Smuzhiyun }
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun static const struct snd_pcm_ops snd_es1938_playback_ops = {
978*4882a593Smuzhiyun .open = snd_es1938_playback_open,
979*4882a593Smuzhiyun .close = snd_es1938_playback_close,
980*4882a593Smuzhiyun .prepare = snd_es1938_playback_prepare,
981*4882a593Smuzhiyun .trigger = snd_es1938_playback_trigger,
982*4882a593Smuzhiyun .pointer = snd_es1938_playback_pointer,
983*4882a593Smuzhiyun };
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun static const struct snd_pcm_ops snd_es1938_capture_ops = {
986*4882a593Smuzhiyun .open = snd_es1938_capture_open,
987*4882a593Smuzhiyun .close = snd_es1938_capture_close,
988*4882a593Smuzhiyun .prepare = snd_es1938_capture_prepare,
989*4882a593Smuzhiyun .trigger = snd_es1938_capture_trigger,
990*4882a593Smuzhiyun .pointer = snd_es1938_capture_pointer,
991*4882a593Smuzhiyun .copy_user = snd_es1938_capture_copy,
992*4882a593Smuzhiyun .copy_kernel = snd_es1938_capture_copy_kernel,
993*4882a593Smuzhiyun };
994*4882a593Smuzhiyun
snd_es1938_new_pcm(struct es1938 * chip,int device)995*4882a593Smuzhiyun static int snd_es1938_new_pcm(struct es1938 *chip, int device)
996*4882a593Smuzhiyun {
997*4882a593Smuzhiyun struct snd_pcm *pcm;
998*4882a593Smuzhiyun int err;
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun if ((err = snd_pcm_new(chip->card, "es-1938-1946", device, 2, 1, &pcm)) < 0)
1001*4882a593Smuzhiyun return err;
1002*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1938_playback_ops);
1003*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1938_capture_ops);
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun pcm->private_data = chip;
1006*4882a593Smuzhiyun pcm->info_flags = 0;
1007*4882a593Smuzhiyun strcpy(pcm->name, "ESS Solo-1");
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1010*4882a593Smuzhiyun &chip->pci->dev, 64*1024, 64*1024);
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun chip->pcm = pcm;
1013*4882a593Smuzhiyun return 0;
1014*4882a593Smuzhiyun }
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun /* -------------------------------------------------------------------
1017*4882a593Smuzhiyun *
1018*4882a593Smuzhiyun * *** Mixer part ***
1019*4882a593Smuzhiyun */
1020*4882a593Smuzhiyun
snd_es1938_info_mux(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1021*4882a593Smuzhiyun static int snd_es1938_info_mux(struct snd_kcontrol *kcontrol,
1022*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1023*4882a593Smuzhiyun {
1024*4882a593Smuzhiyun static const char * const texts[8] = {
1025*4882a593Smuzhiyun "Mic", "Mic Master", "CD", "AOUT",
1026*4882a593Smuzhiyun "Mic1", "Mix", "Line", "Master"
1027*4882a593Smuzhiyun };
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun return snd_ctl_enum_info(uinfo, 1, 8, texts);
1030*4882a593Smuzhiyun }
1031*4882a593Smuzhiyun
snd_es1938_get_mux(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1032*4882a593Smuzhiyun static int snd_es1938_get_mux(struct snd_kcontrol *kcontrol,
1033*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1034*4882a593Smuzhiyun {
1035*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1036*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = snd_es1938_mixer_read(chip, 0x1c) & 0x07;
1037*4882a593Smuzhiyun return 0;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun
snd_es1938_put_mux(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1040*4882a593Smuzhiyun static int snd_es1938_put_mux(struct snd_kcontrol *kcontrol,
1041*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1042*4882a593Smuzhiyun {
1043*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1044*4882a593Smuzhiyun unsigned char val = ucontrol->value.enumerated.item[0];
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun if (val > 7)
1047*4882a593Smuzhiyun return -EINVAL;
1048*4882a593Smuzhiyun return snd_es1938_mixer_bits(chip, 0x1c, 0x07, val) != val;
1049*4882a593Smuzhiyun }
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun #define snd_es1938_info_spatializer_enable snd_ctl_boolean_mono_info
1052*4882a593Smuzhiyun
snd_es1938_get_spatializer_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1053*4882a593Smuzhiyun static int snd_es1938_get_spatializer_enable(struct snd_kcontrol *kcontrol,
1054*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1055*4882a593Smuzhiyun {
1056*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1057*4882a593Smuzhiyun unsigned char val = snd_es1938_mixer_read(chip, 0x50);
1058*4882a593Smuzhiyun ucontrol->value.integer.value[0] = !!(val & 8);
1059*4882a593Smuzhiyun return 0;
1060*4882a593Smuzhiyun }
1061*4882a593Smuzhiyun
snd_es1938_put_spatializer_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1062*4882a593Smuzhiyun static int snd_es1938_put_spatializer_enable(struct snd_kcontrol *kcontrol,
1063*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1064*4882a593Smuzhiyun {
1065*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1066*4882a593Smuzhiyun unsigned char oval, nval;
1067*4882a593Smuzhiyun int change;
1068*4882a593Smuzhiyun nval = ucontrol->value.integer.value[0] ? 0x0c : 0x04;
1069*4882a593Smuzhiyun oval = snd_es1938_mixer_read(chip, 0x50) & 0x0c;
1070*4882a593Smuzhiyun change = nval != oval;
1071*4882a593Smuzhiyun if (change) {
1072*4882a593Smuzhiyun snd_es1938_mixer_write(chip, 0x50, nval & ~0x04);
1073*4882a593Smuzhiyun snd_es1938_mixer_write(chip, 0x50, nval);
1074*4882a593Smuzhiyun }
1075*4882a593Smuzhiyun return change;
1076*4882a593Smuzhiyun }
1077*4882a593Smuzhiyun
snd_es1938_info_hw_volume(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1078*4882a593Smuzhiyun static int snd_es1938_info_hw_volume(struct snd_kcontrol *kcontrol,
1079*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1080*4882a593Smuzhiyun {
1081*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1082*4882a593Smuzhiyun uinfo->count = 2;
1083*4882a593Smuzhiyun uinfo->value.integer.min = 0;
1084*4882a593Smuzhiyun uinfo->value.integer.max = 63;
1085*4882a593Smuzhiyun return 0;
1086*4882a593Smuzhiyun }
1087*4882a593Smuzhiyun
snd_es1938_get_hw_volume(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1088*4882a593Smuzhiyun static int snd_es1938_get_hw_volume(struct snd_kcontrol *kcontrol,
1089*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1090*4882a593Smuzhiyun {
1091*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1092*4882a593Smuzhiyun ucontrol->value.integer.value[0] = snd_es1938_mixer_read(chip, 0x61) & 0x3f;
1093*4882a593Smuzhiyun ucontrol->value.integer.value[1] = snd_es1938_mixer_read(chip, 0x63) & 0x3f;
1094*4882a593Smuzhiyun return 0;
1095*4882a593Smuzhiyun }
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun #define snd_es1938_info_hw_switch snd_ctl_boolean_stereo_info
1098*4882a593Smuzhiyun
snd_es1938_get_hw_switch(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1099*4882a593Smuzhiyun static int snd_es1938_get_hw_switch(struct snd_kcontrol *kcontrol,
1100*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1101*4882a593Smuzhiyun {
1102*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1103*4882a593Smuzhiyun ucontrol->value.integer.value[0] = !(snd_es1938_mixer_read(chip, 0x61) & 0x40);
1104*4882a593Smuzhiyun ucontrol->value.integer.value[1] = !(snd_es1938_mixer_read(chip, 0x63) & 0x40);
1105*4882a593Smuzhiyun return 0;
1106*4882a593Smuzhiyun }
1107*4882a593Smuzhiyun
snd_es1938_hwv_free(struct snd_kcontrol * kcontrol)1108*4882a593Smuzhiyun static void snd_es1938_hwv_free(struct snd_kcontrol *kcontrol)
1109*4882a593Smuzhiyun {
1110*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1111*4882a593Smuzhiyun chip->master_volume = NULL;
1112*4882a593Smuzhiyun chip->master_switch = NULL;
1113*4882a593Smuzhiyun chip->hw_volume = NULL;
1114*4882a593Smuzhiyun chip->hw_switch = NULL;
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun
snd_es1938_reg_bits(struct es1938 * chip,unsigned char reg,unsigned char mask,unsigned char val)1117*4882a593Smuzhiyun static int snd_es1938_reg_bits(struct es1938 *chip, unsigned char reg,
1118*4882a593Smuzhiyun unsigned char mask, unsigned char val)
1119*4882a593Smuzhiyun {
1120*4882a593Smuzhiyun if (reg < 0xa0)
1121*4882a593Smuzhiyun return snd_es1938_mixer_bits(chip, reg, mask, val);
1122*4882a593Smuzhiyun else
1123*4882a593Smuzhiyun return snd_es1938_bits(chip, reg, mask, val);
1124*4882a593Smuzhiyun }
1125*4882a593Smuzhiyun
snd_es1938_reg_read(struct es1938 * chip,unsigned char reg)1126*4882a593Smuzhiyun static int snd_es1938_reg_read(struct es1938 *chip, unsigned char reg)
1127*4882a593Smuzhiyun {
1128*4882a593Smuzhiyun if (reg < 0xa0)
1129*4882a593Smuzhiyun return snd_es1938_mixer_read(chip, reg);
1130*4882a593Smuzhiyun else
1131*4882a593Smuzhiyun return snd_es1938_read(chip, reg);
1132*4882a593Smuzhiyun }
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun #define ES1938_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
1135*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1136*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,\
1137*4882a593Smuzhiyun .name = xname, .index = xindex, \
1138*4882a593Smuzhiyun .info = snd_es1938_info_single, \
1139*4882a593Smuzhiyun .get = snd_es1938_get_single, .put = snd_es1938_put_single, \
1140*4882a593Smuzhiyun .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \
1141*4882a593Smuzhiyun .tlv = { .p = xtlv } }
1142*4882a593Smuzhiyun #define ES1938_SINGLE(xname, xindex, reg, shift, mask, invert) \
1143*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1144*4882a593Smuzhiyun .info = snd_es1938_info_single, \
1145*4882a593Smuzhiyun .get = snd_es1938_get_single, .put = snd_es1938_put_single, \
1146*4882a593Smuzhiyun .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
1147*4882a593Smuzhiyun
snd_es1938_info_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1148*4882a593Smuzhiyun static int snd_es1938_info_single(struct snd_kcontrol *kcontrol,
1149*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1150*4882a593Smuzhiyun {
1151*4882a593Smuzhiyun int mask = (kcontrol->private_value >> 16) & 0xff;
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1154*4882a593Smuzhiyun uinfo->count = 1;
1155*4882a593Smuzhiyun uinfo->value.integer.min = 0;
1156*4882a593Smuzhiyun uinfo->value.integer.max = mask;
1157*4882a593Smuzhiyun return 0;
1158*4882a593Smuzhiyun }
1159*4882a593Smuzhiyun
snd_es1938_get_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1160*4882a593Smuzhiyun static int snd_es1938_get_single(struct snd_kcontrol *kcontrol,
1161*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1162*4882a593Smuzhiyun {
1163*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1164*4882a593Smuzhiyun int reg = kcontrol->private_value & 0xff;
1165*4882a593Smuzhiyun int shift = (kcontrol->private_value >> 8) & 0xff;
1166*4882a593Smuzhiyun int mask = (kcontrol->private_value >> 16) & 0xff;
1167*4882a593Smuzhiyun int invert = (kcontrol->private_value >> 24) & 0xff;
1168*4882a593Smuzhiyun int val;
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun val = snd_es1938_reg_read(chip, reg);
1171*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (val >> shift) & mask;
1172*4882a593Smuzhiyun if (invert)
1173*4882a593Smuzhiyun ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1174*4882a593Smuzhiyun return 0;
1175*4882a593Smuzhiyun }
1176*4882a593Smuzhiyun
snd_es1938_put_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1177*4882a593Smuzhiyun static int snd_es1938_put_single(struct snd_kcontrol *kcontrol,
1178*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1179*4882a593Smuzhiyun {
1180*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1181*4882a593Smuzhiyun int reg = kcontrol->private_value & 0xff;
1182*4882a593Smuzhiyun int shift = (kcontrol->private_value >> 8) & 0xff;
1183*4882a593Smuzhiyun int mask = (kcontrol->private_value >> 16) & 0xff;
1184*4882a593Smuzhiyun int invert = (kcontrol->private_value >> 24) & 0xff;
1185*4882a593Smuzhiyun unsigned char val;
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun val = (ucontrol->value.integer.value[0] & mask);
1188*4882a593Smuzhiyun if (invert)
1189*4882a593Smuzhiyun val = mask - val;
1190*4882a593Smuzhiyun mask <<= shift;
1191*4882a593Smuzhiyun val <<= shift;
1192*4882a593Smuzhiyun return snd_es1938_reg_bits(chip, reg, mask, val) != val;
1193*4882a593Smuzhiyun }
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun #define ES1938_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \
1196*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1197*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,\
1198*4882a593Smuzhiyun .name = xname, .index = xindex, \
1199*4882a593Smuzhiyun .info = snd_es1938_info_double, \
1200*4882a593Smuzhiyun .get = snd_es1938_get_double, .put = snd_es1938_put_double, \
1201*4882a593Smuzhiyun .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22), \
1202*4882a593Smuzhiyun .tlv = { .p = xtlv } }
1203*4882a593Smuzhiyun #define ES1938_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
1204*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1205*4882a593Smuzhiyun .info = snd_es1938_info_double, \
1206*4882a593Smuzhiyun .get = snd_es1938_get_double, .put = snd_es1938_put_double, \
1207*4882a593Smuzhiyun .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
1208*4882a593Smuzhiyun
snd_es1938_info_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1209*4882a593Smuzhiyun static int snd_es1938_info_double(struct snd_kcontrol *kcontrol,
1210*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
1211*4882a593Smuzhiyun {
1212*4882a593Smuzhiyun int mask = (kcontrol->private_value >> 24) & 0xff;
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1215*4882a593Smuzhiyun uinfo->count = 2;
1216*4882a593Smuzhiyun uinfo->value.integer.min = 0;
1217*4882a593Smuzhiyun uinfo->value.integer.max = mask;
1218*4882a593Smuzhiyun return 0;
1219*4882a593Smuzhiyun }
1220*4882a593Smuzhiyun
snd_es1938_get_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1221*4882a593Smuzhiyun static int snd_es1938_get_double(struct snd_kcontrol *kcontrol,
1222*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1223*4882a593Smuzhiyun {
1224*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1225*4882a593Smuzhiyun int left_reg = kcontrol->private_value & 0xff;
1226*4882a593Smuzhiyun int right_reg = (kcontrol->private_value >> 8) & 0xff;
1227*4882a593Smuzhiyun int shift_left = (kcontrol->private_value >> 16) & 0x07;
1228*4882a593Smuzhiyun int shift_right = (kcontrol->private_value >> 19) & 0x07;
1229*4882a593Smuzhiyun int mask = (kcontrol->private_value >> 24) & 0xff;
1230*4882a593Smuzhiyun int invert = (kcontrol->private_value >> 22) & 1;
1231*4882a593Smuzhiyun unsigned char left, right;
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun left = snd_es1938_reg_read(chip, left_reg);
1234*4882a593Smuzhiyun if (left_reg != right_reg)
1235*4882a593Smuzhiyun right = snd_es1938_reg_read(chip, right_reg);
1236*4882a593Smuzhiyun else
1237*4882a593Smuzhiyun right = left;
1238*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (left >> shift_left) & mask;
1239*4882a593Smuzhiyun ucontrol->value.integer.value[1] = (right >> shift_right) & mask;
1240*4882a593Smuzhiyun if (invert) {
1241*4882a593Smuzhiyun ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1242*4882a593Smuzhiyun ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
1243*4882a593Smuzhiyun }
1244*4882a593Smuzhiyun return 0;
1245*4882a593Smuzhiyun }
1246*4882a593Smuzhiyun
snd_es1938_put_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1247*4882a593Smuzhiyun static int snd_es1938_put_double(struct snd_kcontrol *kcontrol,
1248*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1249*4882a593Smuzhiyun {
1250*4882a593Smuzhiyun struct es1938 *chip = snd_kcontrol_chip(kcontrol);
1251*4882a593Smuzhiyun int left_reg = kcontrol->private_value & 0xff;
1252*4882a593Smuzhiyun int right_reg = (kcontrol->private_value >> 8) & 0xff;
1253*4882a593Smuzhiyun int shift_left = (kcontrol->private_value >> 16) & 0x07;
1254*4882a593Smuzhiyun int shift_right = (kcontrol->private_value >> 19) & 0x07;
1255*4882a593Smuzhiyun int mask = (kcontrol->private_value >> 24) & 0xff;
1256*4882a593Smuzhiyun int invert = (kcontrol->private_value >> 22) & 1;
1257*4882a593Smuzhiyun int change;
1258*4882a593Smuzhiyun unsigned char val1, val2, mask1, mask2;
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun val1 = ucontrol->value.integer.value[0] & mask;
1261*4882a593Smuzhiyun val2 = ucontrol->value.integer.value[1] & mask;
1262*4882a593Smuzhiyun if (invert) {
1263*4882a593Smuzhiyun val1 = mask - val1;
1264*4882a593Smuzhiyun val2 = mask - val2;
1265*4882a593Smuzhiyun }
1266*4882a593Smuzhiyun val1 <<= shift_left;
1267*4882a593Smuzhiyun val2 <<= shift_right;
1268*4882a593Smuzhiyun mask1 = mask << shift_left;
1269*4882a593Smuzhiyun mask2 = mask << shift_right;
1270*4882a593Smuzhiyun if (left_reg != right_reg) {
1271*4882a593Smuzhiyun change = 0;
1272*4882a593Smuzhiyun if (snd_es1938_reg_bits(chip, left_reg, mask1, val1) != val1)
1273*4882a593Smuzhiyun change = 1;
1274*4882a593Smuzhiyun if (snd_es1938_reg_bits(chip, right_reg, mask2, val2) != val2)
1275*4882a593Smuzhiyun change = 1;
1276*4882a593Smuzhiyun } else {
1277*4882a593Smuzhiyun change = (snd_es1938_reg_bits(chip, left_reg, mask1 | mask2,
1278*4882a593Smuzhiyun val1 | val2) != (val1 | val2));
1279*4882a593Smuzhiyun }
1280*4882a593Smuzhiyun return change;
1281*4882a593Smuzhiyun }
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(db_scale_master,
1284*4882a593Smuzhiyun 0, 54, TLV_DB_SCALE_ITEM(-3600, 50, 1),
1285*4882a593Smuzhiyun 54, 63, TLV_DB_SCALE_ITEM(-900, 100, 0),
1286*4882a593Smuzhiyun );
1287*4882a593Smuzhiyun
1288*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(db_scale_audio1,
1289*4882a593Smuzhiyun 0, 8, TLV_DB_SCALE_ITEM(-3300, 300, 1),
1290*4882a593Smuzhiyun 8, 15, TLV_DB_SCALE_ITEM(-900, 150, 0),
1291*4882a593Smuzhiyun );
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(db_scale_audio2,
1294*4882a593Smuzhiyun 0, 8, TLV_DB_SCALE_ITEM(-3450, 300, 1),
1295*4882a593Smuzhiyun 8, 15, TLV_DB_SCALE_ITEM(-1050, 150, 0),
1296*4882a593Smuzhiyun );
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(db_scale_mic,
1299*4882a593Smuzhiyun 0, 8, TLV_DB_SCALE_ITEM(-2400, 300, 1),
1300*4882a593Smuzhiyun 8, 15, TLV_DB_SCALE_ITEM(0, 150, 0),
1301*4882a593Smuzhiyun );
1302*4882a593Smuzhiyun
1303*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(db_scale_line,
1304*4882a593Smuzhiyun 0, 8, TLV_DB_SCALE_ITEM(-3150, 300, 1),
1305*4882a593Smuzhiyun 8, 15, TLV_DB_SCALE_ITEM(-750, 150, 0),
1306*4882a593Smuzhiyun );
1307*4882a593Smuzhiyun
1308*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_capture, 0, 150, 0);
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_es1938_controls[] = {
1311*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Master Playback Volume", 0, 0x60, 0x62, 0, 0, 63, 0,
1312*4882a593Smuzhiyun db_scale_master),
1313*4882a593Smuzhiyun ES1938_DOUBLE("Master Playback Switch", 0, 0x60, 0x62, 6, 6, 1, 1),
1314*4882a593Smuzhiyun {
1315*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1316*4882a593Smuzhiyun .name = "Hardware Master Playback Volume",
1317*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ,
1318*4882a593Smuzhiyun .info = snd_es1938_info_hw_volume,
1319*4882a593Smuzhiyun .get = snd_es1938_get_hw_volume,
1320*4882a593Smuzhiyun },
1321*4882a593Smuzhiyun {
1322*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1323*4882a593Smuzhiyun .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1324*4882a593Smuzhiyun SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1325*4882a593Smuzhiyun .name = "Hardware Master Playback Switch",
1326*4882a593Smuzhiyun .info = snd_es1938_info_hw_switch,
1327*4882a593Smuzhiyun .get = snd_es1938_get_hw_switch,
1328*4882a593Smuzhiyun .tlv = { .p = db_scale_master },
1329*4882a593Smuzhiyun },
1330*4882a593Smuzhiyun ES1938_SINGLE("Hardware Volume Split", 0, 0x64, 7, 1, 0),
1331*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Line Playback Volume", 0, 0x3e, 0x3e, 4, 0, 15, 0,
1332*4882a593Smuzhiyun db_scale_line),
1333*4882a593Smuzhiyun ES1938_DOUBLE("CD Playback Volume", 0, 0x38, 0x38, 4, 0, 15, 0),
1334*4882a593Smuzhiyun ES1938_DOUBLE_TLV("FM Playback Volume", 0, 0x36, 0x36, 4, 0, 15, 0,
1335*4882a593Smuzhiyun db_scale_mic),
1336*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Mono Playback Volume", 0, 0x6d, 0x6d, 4, 0, 15, 0,
1337*4882a593Smuzhiyun db_scale_line),
1338*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Mic Playback Volume", 0, 0x1a, 0x1a, 4, 0, 15, 0,
1339*4882a593Smuzhiyun db_scale_mic),
1340*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Aux Playback Volume", 0, 0x3a, 0x3a, 4, 0, 15, 0,
1341*4882a593Smuzhiyun db_scale_line),
1342*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Capture Volume", 0, 0xb4, 0xb4, 4, 0, 15, 0,
1343*4882a593Smuzhiyun db_scale_capture),
1344*4882a593Smuzhiyun ES1938_SINGLE("Beep Volume", 0, 0x3c, 0, 7, 0),
1345*4882a593Smuzhiyun ES1938_SINGLE("Record Monitor", 0, 0xa8, 3, 1, 0),
1346*4882a593Smuzhiyun ES1938_SINGLE("Capture Switch", 0, 0x1c, 4, 1, 1),
1347*4882a593Smuzhiyun {
1348*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1349*4882a593Smuzhiyun .name = "Capture Source",
1350*4882a593Smuzhiyun .info = snd_es1938_info_mux,
1351*4882a593Smuzhiyun .get = snd_es1938_get_mux,
1352*4882a593Smuzhiyun .put = snd_es1938_put_mux,
1353*4882a593Smuzhiyun },
1354*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Mono Input Playback Volume", 0, 0x6d, 0x6d, 4, 0, 15, 0,
1355*4882a593Smuzhiyun db_scale_line),
1356*4882a593Smuzhiyun ES1938_DOUBLE_TLV("PCM Capture Volume", 0, 0x69, 0x69, 4, 0, 15, 0,
1357*4882a593Smuzhiyun db_scale_audio2),
1358*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Mic Capture Volume", 0, 0x68, 0x68, 4, 0, 15, 0,
1359*4882a593Smuzhiyun db_scale_mic),
1360*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Line Capture Volume", 0, 0x6e, 0x6e, 4, 0, 15, 0,
1361*4882a593Smuzhiyun db_scale_line),
1362*4882a593Smuzhiyun ES1938_DOUBLE_TLV("FM Capture Volume", 0, 0x6b, 0x6b, 4, 0, 15, 0,
1363*4882a593Smuzhiyun db_scale_mic),
1364*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Mono Capture Volume", 0, 0x6f, 0x6f, 4, 0, 15, 0,
1365*4882a593Smuzhiyun db_scale_line),
1366*4882a593Smuzhiyun ES1938_DOUBLE_TLV("CD Capture Volume", 0, 0x6a, 0x6a, 4, 0, 15, 0,
1367*4882a593Smuzhiyun db_scale_line),
1368*4882a593Smuzhiyun ES1938_DOUBLE_TLV("Aux Capture Volume", 0, 0x6c, 0x6c, 4, 0, 15, 0,
1369*4882a593Smuzhiyun db_scale_line),
1370*4882a593Smuzhiyun ES1938_DOUBLE_TLV("PCM Playback Volume", 0, 0x7c, 0x7c, 4, 0, 15, 0,
1371*4882a593Smuzhiyun db_scale_audio2),
1372*4882a593Smuzhiyun ES1938_DOUBLE_TLV("PCM Playback Volume", 1, 0x14, 0x14, 4, 0, 15, 0,
1373*4882a593Smuzhiyun db_scale_audio1),
1374*4882a593Smuzhiyun ES1938_SINGLE("3D Control - Level", 0, 0x52, 0, 63, 0),
1375*4882a593Smuzhiyun {
1376*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1377*4882a593Smuzhiyun .name = "3D Control - Switch",
1378*4882a593Smuzhiyun .info = snd_es1938_info_spatializer_enable,
1379*4882a593Smuzhiyun .get = snd_es1938_get_spatializer_enable,
1380*4882a593Smuzhiyun .put = snd_es1938_put_spatializer_enable,
1381*4882a593Smuzhiyun },
1382*4882a593Smuzhiyun ES1938_SINGLE("Mic Boost (+26dB)", 0, 0x7d, 3, 1, 0)
1383*4882a593Smuzhiyun };
1384*4882a593Smuzhiyun
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- */
1387*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- */
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun /*
1390*4882a593Smuzhiyun * initialize the chip - used by resume callback, too
1391*4882a593Smuzhiyun */
snd_es1938_chip_init(struct es1938 * chip)1392*4882a593Smuzhiyun static void snd_es1938_chip_init(struct es1938 *chip)
1393*4882a593Smuzhiyun {
1394*4882a593Smuzhiyun /* reset chip */
1395*4882a593Smuzhiyun snd_es1938_reset(chip);
1396*4882a593Smuzhiyun
1397*4882a593Smuzhiyun /* configure native mode */
1398*4882a593Smuzhiyun
1399*4882a593Smuzhiyun /* enable bus master */
1400*4882a593Smuzhiyun pci_set_master(chip->pci);
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun /* disable legacy audio */
1403*4882a593Smuzhiyun pci_write_config_word(chip->pci, SL_PCI_LEGACYCONTROL, 0x805f);
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun /* set DDMA base */
1406*4882a593Smuzhiyun pci_write_config_word(chip->pci, SL_PCI_DDMACONTROL, chip->ddma_port | 1);
1407*4882a593Smuzhiyun
1408*4882a593Smuzhiyun /* set DMA/IRQ policy */
1409*4882a593Smuzhiyun pci_write_config_dword(chip->pci, SL_PCI_CONFIG, 0);
1410*4882a593Smuzhiyun
1411*4882a593Smuzhiyun /* enable Audio 1, Audio 2, MPU401 IRQ and HW volume IRQ*/
1412*4882a593Smuzhiyun outb(0xf0, SLIO_REG(chip, IRQCONTROL));
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun /* reset DMA */
1415*4882a593Smuzhiyun outb(0, SLDM_REG(chip, DMACLEAR));
1416*4882a593Smuzhiyun }
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
1419*4882a593Smuzhiyun /*
1420*4882a593Smuzhiyun * PM support
1421*4882a593Smuzhiyun */
1422*4882a593Smuzhiyun
1423*4882a593Smuzhiyun static const unsigned char saved_regs[SAVED_REG_SIZE+1] = {
1424*4882a593Smuzhiyun 0x14, 0x1a, 0x1c, 0x3a, 0x3c, 0x3e, 0x36, 0x38,
1425*4882a593Smuzhiyun 0x50, 0x52, 0x60, 0x61, 0x62, 0x63, 0x64, 0x68,
1426*4882a593Smuzhiyun 0x69, 0x6a, 0x6b, 0x6d, 0x6e, 0x6f, 0x7c, 0x7d,
1427*4882a593Smuzhiyun 0xa8, 0xb4,
1428*4882a593Smuzhiyun };
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun
es1938_suspend(struct device * dev)1431*4882a593Smuzhiyun static int es1938_suspend(struct device *dev)
1432*4882a593Smuzhiyun {
1433*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
1434*4882a593Smuzhiyun struct es1938 *chip = card->private_data;
1435*4882a593Smuzhiyun const unsigned char *s;
1436*4882a593Smuzhiyun unsigned char *d;
1437*4882a593Smuzhiyun
1438*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1439*4882a593Smuzhiyun
1440*4882a593Smuzhiyun /* save mixer-related registers */
1441*4882a593Smuzhiyun for (s = saved_regs, d = chip->saved_regs; *s; s++, d++)
1442*4882a593Smuzhiyun *d = snd_es1938_reg_read(chip, *s);
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun outb(0x00, SLIO_REG(chip, IRQCONTROL)); /* disable irqs */
1445*4882a593Smuzhiyun if (chip->irq >= 0) {
1446*4882a593Smuzhiyun free_irq(chip->irq, chip);
1447*4882a593Smuzhiyun chip->irq = -1;
1448*4882a593Smuzhiyun card->sync_irq = -1;
1449*4882a593Smuzhiyun }
1450*4882a593Smuzhiyun return 0;
1451*4882a593Smuzhiyun }
1452*4882a593Smuzhiyun
es1938_resume(struct device * dev)1453*4882a593Smuzhiyun static int es1938_resume(struct device *dev)
1454*4882a593Smuzhiyun {
1455*4882a593Smuzhiyun struct pci_dev *pci = to_pci_dev(dev);
1456*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
1457*4882a593Smuzhiyun struct es1938 *chip = card->private_data;
1458*4882a593Smuzhiyun const unsigned char *s;
1459*4882a593Smuzhiyun unsigned char *d;
1460*4882a593Smuzhiyun
1461*4882a593Smuzhiyun if (request_irq(pci->irq, snd_es1938_interrupt,
1462*4882a593Smuzhiyun IRQF_SHARED, KBUILD_MODNAME, chip)) {
1463*4882a593Smuzhiyun dev_err(dev, "unable to grab IRQ %d, disabling device\n",
1464*4882a593Smuzhiyun pci->irq);
1465*4882a593Smuzhiyun snd_card_disconnect(card);
1466*4882a593Smuzhiyun return -EIO;
1467*4882a593Smuzhiyun }
1468*4882a593Smuzhiyun chip->irq = pci->irq;
1469*4882a593Smuzhiyun card->sync_irq = chip->irq;
1470*4882a593Smuzhiyun snd_es1938_chip_init(chip);
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun /* restore mixer-related registers */
1473*4882a593Smuzhiyun for (s = saved_regs, d = chip->saved_regs; *s; s++, d++) {
1474*4882a593Smuzhiyun if (*s < 0xa0)
1475*4882a593Smuzhiyun snd_es1938_mixer_write(chip, *s, *d);
1476*4882a593Smuzhiyun else
1477*4882a593Smuzhiyun snd_es1938_write(chip, *s, *d);
1478*4882a593Smuzhiyun }
1479*4882a593Smuzhiyun
1480*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1481*4882a593Smuzhiyun return 0;
1482*4882a593Smuzhiyun }
1483*4882a593Smuzhiyun
1484*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(es1938_pm, es1938_suspend, es1938_resume);
1485*4882a593Smuzhiyun #define ES1938_PM_OPS &es1938_pm
1486*4882a593Smuzhiyun #else
1487*4882a593Smuzhiyun #define ES1938_PM_OPS NULL
1488*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
1489*4882a593Smuzhiyun
1490*4882a593Smuzhiyun #ifdef SUPPORT_JOYSTICK
snd_es1938_create_gameport(struct es1938 * chip)1491*4882a593Smuzhiyun static int snd_es1938_create_gameport(struct es1938 *chip)
1492*4882a593Smuzhiyun {
1493*4882a593Smuzhiyun struct gameport *gp;
1494*4882a593Smuzhiyun
1495*4882a593Smuzhiyun chip->gameport = gp = gameport_allocate_port();
1496*4882a593Smuzhiyun if (!gp) {
1497*4882a593Smuzhiyun dev_err(chip->card->dev,
1498*4882a593Smuzhiyun "cannot allocate memory for gameport\n");
1499*4882a593Smuzhiyun return -ENOMEM;
1500*4882a593Smuzhiyun }
1501*4882a593Smuzhiyun
1502*4882a593Smuzhiyun gameport_set_name(gp, "ES1938");
1503*4882a593Smuzhiyun gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1504*4882a593Smuzhiyun gameport_set_dev_parent(gp, &chip->pci->dev);
1505*4882a593Smuzhiyun gp->io = chip->game_port;
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun gameport_register_port(gp);
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun return 0;
1510*4882a593Smuzhiyun }
1511*4882a593Smuzhiyun
snd_es1938_free_gameport(struct es1938 * chip)1512*4882a593Smuzhiyun static void snd_es1938_free_gameport(struct es1938 *chip)
1513*4882a593Smuzhiyun {
1514*4882a593Smuzhiyun if (chip->gameport) {
1515*4882a593Smuzhiyun gameport_unregister_port(chip->gameport);
1516*4882a593Smuzhiyun chip->gameport = NULL;
1517*4882a593Smuzhiyun }
1518*4882a593Smuzhiyun }
1519*4882a593Smuzhiyun #else
snd_es1938_create_gameport(struct es1938 * chip)1520*4882a593Smuzhiyun static inline int snd_es1938_create_gameport(struct es1938 *chip) { return -ENOSYS; }
snd_es1938_free_gameport(struct es1938 * chip)1521*4882a593Smuzhiyun static inline void snd_es1938_free_gameport(struct es1938 *chip) { }
1522*4882a593Smuzhiyun #endif /* SUPPORT_JOYSTICK */
1523*4882a593Smuzhiyun
snd_es1938_free(struct es1938 * chip)1524*4882a593Smuzhiyun static int snd_es1938_free(struct es1938 *chip)
1525*4882a593Smuzhiyun {
1526*4882a593Smuzhiyun /* disable irqs */
1527*4882a593Smuzhiyun outb(0x00, SLIO_REG(chip, IRQCONTROL));
1528*4882a593Smuzhiyun if (chip->rmidi)
1529*4882a593Smuzhiyun snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0);
1530*4882a593Smuzhiyun
1531*4882a593Smuzhiyun snd_es1938_free_gameport(chip);
1532*4882a593Smuzhiyun
1533*4882a593Smuzhiyun if (chip->irq >= 0)
1534*4882a593Smuzhiyun free_irq(chip->irq, chip);
1535*4882a593Smuzhiyun pci_release_regions(chip->pci);
1536*4882a593Smuzhiyun pci_disable_device(chip->pci);
1537*4882a593Smuzhiyun kfree(chip);
1538*4882a593Smuzhiyun return 0;
1539*4882a593Smuzhiyun }
1540*4882a593Smuzhiyun
snd_es1938_dev_free(struct snd_device * device)1541*4882a593Smuzhiyun static int snd_es1938_dev_free(struct snd_device *device)
1542*4882a593Smuzhiyun {
1543*4882a593Smuzhiyun struct es1938 *chip = device->device_data;
1544*4882a593Smuzhiyun return snd_es1938_free(chip);
1545*4882a593Smuzhiyun }
1546*4882a593Smuzhiyun
snd_es1938_create(struct snd_card * card,struct pci_dev * pci,struct es1938 ** rchip)1547*4882a593Smuzhiyun static int snd_es1938_create(struct snd_card *card,
1548*4882a593Smuzhiyun struct pci_dev *pci,
1549*4882a593Smuzhiyun struct es1938 **rchip)
1550*4882a593Smuzhiyun {
1551*4882a593Smuzhiyun struct es1938 *chip;
1552*4882a593Smuzhiyun int err;
1553*4882a593Smuzhiyun static const struct snd_device_ops ops = {
1554*4882a593Smuzhiyun .dev_free = snd_es1938_dev_free,
1555*4882a593Smuzhiyun };
1556*4882a593Smuzhiyun
1557*4882a593Smuzhiyun *rchip = NULL;
1558*4882a593Smuzhiyun
1559*4882a593Smuzhiyun /* enable PCI device */
1560*4882a593Smuzhiyun if ((err = pci_enable_device(pci)) < 0)
1561*4882a593Smuzhiyun return err;
1562*4882a593Smuzhiyun /* check, if we can restrict PCI DMA transfers to 24 bits */
1563*4882a593Smuzhiyun if (dma_set_mask(&pci->dev, DMA_BIT_MASK(24)) < 0 ||
1564*4882a593Smuzhiyun dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(24)) < 0) {
1565*4882a593Smuzhiyun dev_err(card->dev,
1566*4882a593Smuzhiyun "architecture does not support 24bit PCI busmaster DMA\n");
1567*4882a593Smuzhiyun pci_disable_device(pci);
1568*4882a593Smuzhiyun return -ENXIO;
1569*4882a593Smuzhiyun }
1570*4882a593Smuzhiyun
1571*4882a593Smuzhiyun chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1572*4882a593Smuzhiyun if (chip == NULL) {
1573*4882a593Smuzhiyun pci_disable_device(pci);
1574*4882a593Smuzhiyun return -ENOMEM;
1575*4882a593Smuzhiyun }
1576*4882a593Smuzhiyun spin_lock_init(&chip->reg_lock);
1577*4882a593Smuzhiyun spin_lock_init(&chip->mixer_lock);
1578*4882a593Smuzhiyun chip->card = card;
1579*4882a593Smuzhiyun chip->pci = pci;
1580*4882a593Smuzhiyun chip->irq = -1;
1581*4882a593Smuzhiyun if ((err = pci_request_regions(pci, "ESS Solo-1")) < 0) {
1582*4882a593Smuzhiyun kfree(chip);
1583*4882a593Smuzhiyun pci_disable_device(pci);
1584*4882a593Smuzhiyun return err;
1585*4882a593Smuzhiyun }
1586*4882a593Smuzhiyun chip->io_port = pci_resource_start(pci, 0);
1587*4882a593Smuzhiyun chip->sb_port = pci_resource_start(pci, 1);
1588*4882a593Smuzhiyun chip->vc_port = pci_resource_start(pci, 2);
1589*4882a593Smuzhiyun chip->mpu_port = pci_resource_start(pci, 3);
1590*4882a593Smuzhiyun chip->game_port = pci_resource_start(pci, 4);
1591*4882a593Smuzhiyun if (request_irq(pci->irq, snd_es1938_interrupt, IRQF_SHARED,
1592*4882a593Smuzhiyun KBUILD_MODNAME, chip)) {
1593*4882a593Smuzhiyun dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1594*4882a593Smuzhiyun snd_es1938_free(chip);
1595*4882a593Smuzhiyun return -EBUSY;
1596*4882a593Smuzhiyun }
1597*4882a593Smuzhiyun chip->irq = pci->irq;
1598*4882a593Smuzhiyun card->sync_irq = chip->irq;
1599*4882a593Smuzhiyun dev_dbg(card->dev,
1600*4882a593Smuzhiyun "create: io: 0x%lx, sb: 0x%lx, vc: 0x%lx, mpu: 0x%lx, game: 0x%lx\n",
1601*4882a593Smuzhiyun chip->io_port, chip->sb_port, chip->vc_port, chip->mpu_port, chip->game_port);
1602*4882a593Smuzhiyun
1603*4882a593Smuzhiyun chip->ddma_port = chip->vc_port + 0x00; /* fix from Thomas Sailer */
1604*4882a593Smuzhiyun
1605*4882a593Smuzhiyun snd_es1938_chip_init(chip);
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1608*4882a593Smuzhiyun snd_es1938_free(chip);
1609*4882a593Smuzhiyun return err;
1610*4882a593Smuzhiyun }
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun *rchip = chip;
1613*4882a593Smuzhiyun return 0;
1614*4882a593Smuzhiyun }
1615*4882a593Smuzhiyun
1616*4882a593Smuzhiyun /* --------------------------------------------------------------------
1617*4882a593Smuzhiyun * Interrupt handler
1618*4882a593Smuzhiyun * -------------------------------------------------------------------- */
snd_es1938_interrupt(int irq,void * dev_id)1619*4882a593Smuzhiyun static irqreturn_t snd_es1938_interrupt(int irq, void *dev_id)
1620*4882a593Smuzhiyun {
1621*4882a593Smuzhiyun struct es1938 *chip = dev_id;
1622*4882a593Smuzhiyun unsigned char status;
1623*4882a593Smuzhiyun __always_unused unsigned char audiostatus;
1624*4882a593Smuzhiyun int handled = 0;
1625*4882a593Smuzhiyun
1626*4882a593Smuzhiyun status = inb(SLIO_REG(chip, IRQCONTROL));
1627*4882a593Smuzhiyun #if 0
1628*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1629*4882a593Smuzhiyun "Es1938debug - interrupt status: =0x%x\n", status);
1630*4882a593Smuzhiyun #endif
1631*4882a593Smuzhiyun
1632*4882a593Smuzhiyun /* AUDIO 1 */
1633*4882a593Smuzhiyun if (status & 0x10) {
1634*4882a593Smuzhiyun #if 0
1635*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1636*4882a593Smuzhiyun "Es1938debug - AUDIO channel 1 interrupt\n");
1637*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1638*4882a593Smuzhiyun "Es1938debug - AUDIO channel 1 DMAC DMA count: %u\n",
1639*4882a593Smuzhiyun inw(SLDM_REG(chip, DMACOUNT)));
1640*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1641*4882a593Smuzhiyun "Es1938debug - AUDIO channel 1 DMAC DMA base: %u\n",
1642*4882a593Smuzhiyun inl(SLDM_REG(chip, DMAADDR)));
1643*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1644*4882a593Smuzhiyun "Es1938debug - AUDIO channel 1 DMAC DMA status: 0x%x\n",
1645*4882a593Smuzhiyun inl(SLDM_REG(chip, DMASTATUS)));
1646*4882a593Smuzhiyun #endif
1647*4882a593Smuzhiyun /* clear irq */
1648*4882a593Smuzhiyun handled = 1;
1649*4882a593Smuzhiyun audiostatus = inb(SLSB_REG(chip, STATUS));
1650*4882a593Smuzhiyun if (chip->active & ADC1)
1651*4882a593Smuzhiyun snd_pcm_period_elapsed(chip->capture_substream);
1652*4882a593Smuzhiyun else if (chip->active & DAC1)
1653*4882a593Smuzhiyun snd_pcm_period_elapsed(chip->playback2_substream);
1654*4882a593Smuzhiyun }
1655*4882a593Smuzhiyun
1656*4882a593Smuzhiyun /* AUDIO 2 */
1657*4882a593Smuzhiyun if (status & 0x20) {
1658*4882a593Smuzhiyun #if 0
1659*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1660*4882a593Smuzhiyun "Es1938debug - AUDIO channel 2 interrupt\n");
1661*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1662*4882a593Smuzhiyun "Es1938debug - AUDIO channel 2 DMAC DMA count: %u\n",
1663*4882a593Smuzhiyun inw(SLIO_REG(chip, AUDIO2DMACOUNT)));
1664*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1665*4882a593Smuzhiyun "Es1938debug - AUDIO channel 2 DMAC DMA base: %u\n",
1666*4882a593Smuzhiyun inl(SLIO_REG(chip, AUDIO2DMAADDR)));
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun #endif
1669*4882a593Smuzhiyun /* clear irq */
1670*4882a593Smuzhiyun handled = 1;
1671*4882a593Smuzhiyun snd_es1938_mixer_bits(chip, ESSSB_IREG_AUDIO2CONTROL2, 0x80, 0);
1672*4882a593Smuzhiyun if (chip->active & DAC2)
1673*4882a593Smuzhiyun snd_pcm_period_elapsed(chip->playback1_substream);
1674*4882a593Smuzhiyun }
1675*4882a593Smuzhiyun
1676*4882a593Smuzhiyun /* Hardware volume */
1677*4882a593Smuzhiyun if (status & 0x40) {
1678*4882a593Smuzhiyun int split = snd_es1938_mixer_read(chip, 0x64) & 0x80;
1679*4882a593Smuzhiyun handled = 1;
1680*4882a593Smuzhiyun snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->hw_switch->id);
1681*4882a593Smuzhiyun snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->hw_volume->id);
1682*4882a593Smuzhiyun if (!split) {
1683*4882a593Smuzhiyun snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1684*4882a593Smuzhiyun &chip->master_switch->id);
1685*4882a593Smuzhiyun snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1686*4882a593Smuzhiyun &chip->master_volume->id);
1687*4882a593Smuzhiyun }
1688*4882a593Smuzhiyun /* ack interrupt */
1689*4882a593Smuzhiyun snd_es1938_mixer_write(chip, 0x66, 0x00);
1690*4882a593Smuzhiyun }
1691*4882a593Smuzhiyun
1692*4882a593Smuzhiyun /* MPU401 */
1693*4882a593Smuzhiyun if (status & 0x80) {
1694*4882a593Smuzhiyun // the following line is evil! It switches off MIDI interrupt handling after the first interrupt received.
1695*4882a593Smuzhiyun // replacing the last 0 by 0x40 works for ESS-Solo1, but just doing nothing works as well!
1696*4882a593Smuzhiyun // andreas@flying-snail.de
1697*4882a593Smuzhiyun // snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0); /* ack? */
1698*4882a593Smuzhiyun if (chip->rmidi) {
1699*4882a593Smuzhiyun handled = 1;
1700*4882a593Smuzhiyun snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1701*4882a593Smuzhiyun }
1702*4882a593Smuzhiyun }
1703*4882a593Smuzhiyun return IRQ_RETVAL(handled);
1704*4882a593Smuzhiyun }
1705*4882a593Smuzhiyun
1706*4882a593Smuzhiyun #define ES1938_DMA_SIZE 64
1707*4882a593Smuzhiyun
snd_es1938_mixer(struct es1938 * chip)1708*4882a593Smuzhiyun static int snd_es1938_mixer(struct es1938 *chip)
1709*4882a593Smuzhiyun {
1710*4882a593Smuzhiyun struct snd_card *card;
1711*4882a593Smuzhiyun unsigned int idx;
1712*4882a593Smuzhiyun int err;
1713*4882a593Smuzhiyun
1714*4882a593Smuzhiyun card = chip->card;
1715*4882a593Smuzhiyun
1716*4882a593Smuzhiyun strcpy(card->mixername, "ESS Solo-1");
1717*4882a593Smuzhiyun
1718*4882a593Smuzhiyun for (idx = 0; idx < ARRAY_SIZE(snd_es1938_controls); idx++) {
1719*4882a593Smuzhiyun struct snd_kcontrol *kctl;
1720*4882a593Smuzhiyun kctl = snd_ctl_new1(&snd_es1938_controls[idx], chip);
1721*4882a593Smuzhiyun switch (idx) {
1722*4882a593Smuzhiyun case 0:
1723*4882a593Smuzhiyun chip->master_volume = kctl;
1724*4882a593Smuzhiyun kctl->private_free = snd_es1938_hwv_free;
1725*4882a593Smuzhiyun break;
1726*4882a593Smuzhiyun case 1:
1727*4882a593Smuzhiyun chip->master_switch = kctl;
1728*4882a593Smuzhiyun kctl->private_free = snd_es1938_hwv_free;
1729*4882a593Smuzhiyun break;
1730*4882a593Smuzhiyun case 2:
1731*4882a593Smuzhiyun chip->hw_volume = kctl;
1732*4882a593Smuzhiyun kctl->private_free = snd_es1938_hwv_free;
1733*4882a593Smuzhiyun break;
1734*4882a593Smuzhiyun case 3:
1735*4882a593Smuzhiyun chip->hw_switch = kctl;
1736*4882a593Smuzhiyun kctl->private_free = snd_es1938_hwv_free;
1737*4882a593Smuzhiyun break;
1738*4882a593Smuzhiyun }
1739*4882a593Smuzhiyun if ((err = snd_ctl_add(card, kctl)) < 0)
1740*4882a593Smuzhiyun return err;
1741*4882a593Smuzhiyun }
1742*4882a593Smuzhiyun return 0;
1743*4882a593Smuzhiyun }
1744*4882a593Smuzhiyun
1745*4882a593Smuzhiyun
snd_es1938_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1746*4882a593Smuzhiyun static int snd_es1938_probe(struct pci_dev *pci,
1747*4882a593Smuzhiyun const struct pci_device_id *pci_id)
1748*4882a593Smuzhiyun {
1749*4882a593Smuzhiyun static int dev;
1750*4882a593Smuzhiyun struct snd_card *card;
1751*4882a593Smuzhiyun struct es1938 *chip;
1752*4882a593Smuzhiyun struct snd_opl3 *opl3;
1753*4882a593Smuzhiyun int idx, err;
1754*4882a593Smuzhiyun
1755*4882a593Smuzhiyun if (dev >= SNDRV_CARDS)
1756*4882a593Smuzhiyun return -ENODEV;
1757*4882a593Smuzhiyun if (!enable[dev]) {
1758*4882a593Smuzhiyun dev++;
1759*4882a593Smuzhiyun return -ENOENT;
1760*4882a593Smuzhiyun }
1761*4882a593Smuzhiyun
1762*4882a593Smuzhiyun err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1763*4882a593Smuzhiyun 0, &card);
1764*4882a593Smuzhiyun if (err < 0)
1765*4882a593Smuzhiyun return err;
1766*4882a593Smuzhiyun for (idx = 0; idx < 5; idx++) {
1767*4882a593Smuzhiyun if (pci_resource_start(pci, idx) == 0 ||
1768*4882a593Smuzhiyun !(pci_resource_flags(pci, idx) & IORESOURCE_IO)) {
1769*4882a593Smuzhiyun snd_card_free(card);
1770*4882a593Smuzhiyun return -ENODEV;
1771*4882a593Smuzhiyun }
1772*4882a593Smuzhiyun }
1773*4882a593Smuzhiyun if ((err = snd_es1938_create(card, pci, &chip)) < 0) {
1774*4882a593Smuzhiyun snd_card_free(card);
1775*4882a593Smuzhiyun return err;
1776*4882a593Smuzhiyun }
1777*4882a593Smuzhiyun card->private_data = chip;
1778*4882a593Smuzhiyun
1779*4882a593Smuzhiyun strcpy(card->driver, "ES1938");
1780*4882a593Smuzhiyun strcpy(card->shortname, "ESS ES1938 (Solo-1)");
1781*4882a593Smuzhiyun sprintf(card->longname, "%s rev %i, irq %i",
1782*4882a593Smuzhiyun card->shortname,
1783*4882a593Smuzhiyun chip->revision,
1784*4882a593Smuzhiyun chip->irq);
1785*4882a593Smuzhiyun
1786*4882a593Smuzhiyun if ((err = snd_es1938_new_pcm(chip, 0)) < 0) {
1787*4882a593Smuzhiyun snd_card_free(card);
1788*4882a593Smuzhiyun return err;
1789*4882a593Smuzhiyun }
1790*4882a593Smuzhiyun if ((err = snd_es1938_mixer(chip)) < 0) {
1791*4882a593Smuzhiyun snd_card_free(card);
1792*4882a593Smuzhiyun return err;
1793*4882a593Smuzhiyun }
1794*4882a593Smuzhiyun if (snd_opl3_create(card,
1795*4882a593Smuzhiyun SLSB_REG(chip, FMLOWADDR),
1796*4882a593Smuzhiyun SLSB_REG(chip, FMHIGHADDR),
1797*4882a593Smuzhiyun OPL3_HW_OPL3, 1, &opl3) < 0) {
1798*4882a593Smuzhiyun dev_err(card->dev, "OPL3 not detected at 0x%lx\n",
1799*4882a593Smuzhiyun SLSB_REG(chip, FMLOWADDR));
1800*4882a593Smuzhiyun } else {
1801*4882a593Smuzhiyun if ((err = snd_opl3_timer_new(opl3, 0, 1)) < 0) {
1802*4882a593Smuzhiyun snd_card_free(card);
1803*4882a593Smuzhiyun return err;
1804*4882a593Smuzhiyun }
1805*4882a593Smuzhiyun if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1806*4882a593Smuzhiyun snd_card_free(card);
1807*4882a593Smuzhiyun return err;
1808*4882a593Smuzhiyun }
1809*4882a593Smuzhiyun }
1810*4882a593Smuzhiyun if (snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
1811*4882a593Smuzhiyun chip->mpu_port,
1812*4882a593Smuzhiyun MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
1813*4882a593Smuzhiyun -1, &chip->rmidi) < 0) {
1814*4882a593Smuzhiyun dev_err(card->dev, "unable to initialize MPU-401\n");
1815*4882a593Smuzhiyun } else {
1816*4882a593Smuzhiyun // this line is vital for MIDI interrupt handling on ess-solo1
1817*4882a593Smuzhiyun // andreas@flying-snail.de
1818*4882a593Smuzhiyun snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0x40);
1819*4882a593Smuzhiyun }
1820*4882a593Smuzhiyun
1821*4882a593Smuzhiyun snd_es1938_create_gameport(chip);
1822*4882a593Smuzhiyun
1823*4882a593Smuzhiyun if ((err = snd_card_register(card)) < 0) {
1824*4882a593Smuzhiyun snd_card_free(card);
1825*4882a593Smuzhiyun return err;
1826*4882a593Smuzhiyun }
1827*4882a593Smuzhiyun
1828*4882a593Smuzhiyun pci_set_drvdata(pci, card);
1829*4882a593Smuzhiyun dev++;
1830*4882a593Smuzhiyun return 0;
1831*4882a593Smuzhiyun }
1832*4882a593Smuzhiyun
snd_es1938_remove(struct pci_dev * pci)1833*4882a593Smuzhiyun static void snd_es1938_remove(struct pci_dev *pci)
1834*4882a593Smuzhiyun {
1835*4882a593Smuzhiyun snd_card_free(pci_get_drvdata(pci));
1836*4882a593Smuzhiyun }
1837*4882a593Smuzhiyun
1838*4882a593Smuzhiyun static struct pci_driver es1938_driver = {
1839*4882a593Smuzhiyun .name = KBUILD_MODNAME,
1840*4882a593Smuzhiyun .id_table = snd_es1938_ids,
1841*4882a593Smuzhiyun .probe = snd_es1938_probe,
1842*4882a593Smuzhiyun .remove = snd_es1938_remove,
1843*4882a593Smuzhiyun .driver = {
1844*4882a593Smuzhiyun .pm = ES1938_PM_OPS,
1845*4882a593Smuzhiyun },
1846*4882a593Smuzhiyun };
1847*4882a593Smuzhiyun
1848*4882a593Smuzhiyun module_pci_driver(es1938_driver);
1849