1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk> 4*4882a593Smuzhiyun * Driver p17v chips 5*4882a593Smuzhiyun * Version: 0.01 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /******************************************************************************/ 9*4882a593Smuzhiyun /* Audigy2Value Tina (P17V) pointer-offset register set, 10*4882a593Smuzhiyun * accessed through the PTR20 and DATA24 registers */ 11*4882a593Smuzhiyun /******************************************************************************/ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 00 - 07: Not used */ 14*4882a593Smuzhiyun #define P17V_PLAYBACK_FIFO_PTR 0x08 /* Current playback fifo pointer 15*4882a593Smuzhiyun * and number of sound samples in cache. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun /* 09 - 12: Not used */ 18*4882a593Smuzhiyun #define P17V_CAPTURE_FIFO_PTR 0x13 /* Current capture fifo pointer 19*4882a593Smuzhiyun * and number of sound samples in cache. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun /* 14 - 17: Not used */ 22*4882a593Smuzhiyun #define P17V_PB_CHN_SEL 0x18 /* P17v playback channel select */ 23*4882a593Smuzhiyun #define P17V_SE_SLOT_SEL_L 0x19 /* Sound Engine slot select low */ 24*4882a593Smuzhiyun #define P17V_SE_SLOT_SEL_H 0x1a /* Sound Engine slot select high */ 25*4882a593Smuzhiyun /* 1b - 1f: Not used */ 26*4882a593Smuzhiyun /* 20 - 2f: Not used */ 27*4882a593Smuzhiyun /* 30 - 3b: Not used */ 28*4882a593Smuzhiyun #define P17V_SPI 0x3c /* SPI interface register */ 29*4882a593Smuzhiyun #define P17V_I2C_ADDR 0x3d /* I2C Address */ 30*4882a593Smuzhiyun #define P17V_I2C_0 0x3e /* I2C Data */ 31*4882a593Smuzhiyun #define P17V_I2C_1 0x3f /* I2C Data */ 32*4882a593Smuzhiyun /* I2C values */ 33*4882a593Smuzhiyun #define I2C_A_ADC_ADD_MASK 0x000000fe /*The address is a 7 bit address */ 34*4882a593Smuzhiyun #define I2C_A_ADC_RW_MASK 0x00000001 /*bit mask for R/W */ 35*4882a593Smuzhiyun #define I2C_A_ADC_TRANS_MASK 0x00000010 /*Bit mask for I2c address DAC value */ 36*4882a593Smuzhiyun #define I2C_A_ADC_ABORT_MASK 0x00000020 /*Bit mask for I2C transaction abort flag */ 37*4882a593Smuzhiyun #define I2C_A_ADC_LAST_MASK 0x00000040 /*Bit mask for Last word transaction */ 38*4882a593Smuzhiyun #define I2C_A_ADC_BYTE_MASK 0x00000080 /*Bit mask for Byte Mode */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define I2C_A_ADC_ADD 0x00000034 /*This is the Device address for ADC */ 41*4882a593Smuzhiyun #define I2C_A_ADC_READ 0x00000001 /*To perform a read operation */ 42*4882a593Smuzhiyun #define I2C_A_ADC_START 0x00000100 /*Start I2C transaction */ 43*4882a593Smuzhiyun #define I2C_A_ADC_ABORT 0x00000200 /*I2C transaction abort */ 44*4882a593Smuzhiyun #define I2C_A_ADC_LAST 0x00000400 /*I2C last transaction */ 45*4882a593Smuzhiyun #define I2C_A_ADC_BYTE 0x00000800 /*I2C one byte mode */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define I2C_D_ADC_REG_MASK 0xfe000000 /*ADC address register */ 48*4882a593Smuzhiyun #define I2C_D_ADC_DAT_MASK 0x01ff0000 /*ADC data register */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define ADC_TIMEOUT 0x00000007 /*ADC Timeout Clock Disable */ 51*4882a593Smuzhiyun #define ADC_IFC_CTRL 0x0000000b /*ADC Interface Control */ 52*4882a593Smuzhiyun #define ADC_MASTER 0x0000000c /*ADC Master Mode Control */ 53*4882a593Smuzhiyun #define ADC_POWER 0x0000000d /*ADC PowerDown Control */ 54*4882a593Smuzhiyun #define ADC_ATTEN_ADCL 0x0000000e /*ADC Attenuation ADCL */ 55*4882a593Smuzhiyun #define ADC_ATTEN_ADCR 0x0000000f /*ADC Attenuation ADCR */ 56*4882a593Smuzhiyun #define ADC_ALC_CTRL1 0x00000010 /*ADC ALC Control 1 */ 57*4882a593Smuzhiyun #define ADC_ALC_CTRL2 0x00000011 /*ADC ALC Control 2 */ 58*4882a593Smuzhiyun #define ADC_ALC_CTRL3 0x00000012 /*ADC ALC Control 3 */ 59*4882a593Smuzhiyun #define ADC_NOISE_CTRL 0x00000013 /*ADC Noise Gate Control */ 60*4882a593Smuzhiyun #define ADC_LIMIT_CTRL 0x00000014 /*ADC Limiter Control */ 61*4882a593Smuzhiyun #define ADC_MUX 0x00000015 /*ADC Mux offset */ 62*4882a593Smuzhiyun #if 0 63*4882a593Smuzhiyun /* FIXME: Not tested yet. */ 64*4882a593Smuzhiyun #define ADC_GAIN_MASK 0x000000ff //Mask for ADC Gain 65*4882a593Smuzhiyun #define ADC_ZERODB 0x000000cf //Value to set ADC to 0dB 66*4882a593Smuzhiyun #define ADC_MUTE_MASK 0x000000c0 //Mask for ADC mute 67*4882a593Smuzhiyun #define ADC_MUTE 0x000000c0 //Value to mute ADC 68*4882a593Smuzhiyun #define ADC_OSR 0x00000008 //Mask for ADC oversample rate select 69*4882a593Smuzhiyun #define ADC_TIMEOUT_DISABLE 0x00000008 //Value and mask to disable Timeout clock 70*4882a593Smuzhiyun #define ADC_HPF_DISABLE 0x00000100 //Value and mask to disable High pass filter 71*4882a593Smuzhiyun #define ADC_TRANWIN_MASK 0x00000070 //Mask for Length of Transient Window 72*4882a593Smuzhiyun #endif 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define ADC_MUX_MASK 0x0000000f //Mask for ADC Mux 75*4882a593Smuzhiyun #define ADC_MUX_0 0x00000001 //Value to select Unknown at ADC Mux (Not used) 76*4882a593Smuzhiyun #define ADC_MUX_1 0x00000002 //Value to select Unknown at ADC Mux (Not used) 77*4882a593Smuzhiyun #define ADC_MUX_2 0x00000004 //Value to select Mic at ADC Mux 78*4882a593Smuzhiyun #define ADC_MUX_3 0x00000008 //Value to select Line-In at ADC Mux 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define P17V_START_AUDIO 0x40 /* Start Audio bit */ 81*4882a593Smuzhiyun /* 41 - 47: Reserved */ 82*4882a593Smuzhiyun #define P17V_START_CAPTURE 0x48 /* Start Capture bit */ 83*4882a593Smuzhiyun #define P17V_CAPTURE_FIFO_BASE 0x49 /* Record FIFO base address */ 84*4882a593Smuzhiyun #define P17V_CAPTURE_FIFO_SIZE 0x4a /* Record FIFO buffer size */ 85*4882a593Smuzhiyun #define P17V_CAPTURE_FIFO_INDEX 0x4b /* Record FIFO capture index */ 86*4882a593Smuzhiyun #define P17V_CAPTURE_VOL_H 0x4c /* P17v capture volume control */ 87*4882a593Smuzhiyun #define P17V_CAPTURE_VOL_L 0x4d /* P17v capture volume control */ 88*4882a593Smuzhiyun /* 4e - 4f: Not used */ 89*4882a593Smuzhiyun /* 50 - 5f: Not used */ 90*4882a593Smuzhiyun #define P17V_SRCSel 0x60 /* SRC48 and SRCMulti sample rate select 91*4882a593Smuzhiyun * and output select 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun #define P17V_MIXER_AC97_10K1_VOL_L 0x61 /* 10K to Mixer_AC97 input volume control */ 94*4882a593Smuzhiyun #define P17V_MIXER_AC97_10K1_VOL_H 0x62 /* 10K to Mixer_AC97 input volume control */ 95*4882a593Smuzhiyun #define P17V_MIXER_AC97_P17V_VOL_L 0x63 /* P17V to Mixer_AC97 input volume control */ 96*4882a593Smuzhiyun #define P17V_MIXER_AC97_P17V_VOL_H 0x64 /* P17V to Mixer_AC97 input volume control */ 97*4882a593Smuzhiyun #define P17V_MIXER_AC97_SRP_REC_VOL_L 0x65 /* SRP Record to Mixer_AC97 input volume control */ 98*4882a593Smuzhiyun #define P17V_MIXER_AC97_SRP_REC_VOL_H 0x66 /* SRP Record to Mixer_AC97 input volume control */ 99*4882a593Smuzhiyun /* 67 - 68: Reserved */ 100*4882a593Smuzhiyun #define P17V_MIXER_Spdif_10K1_VOL_L 0x69 /* 10K to Mixer_Spdif input volume control */ 101*4882a593Smuzhiyun #define P17V_MIXER_Spdif_10K1_VOL_H 0x6A /* 10K to Mixer_Spdif input volume control */ 102*4882a593Smuzhiyun #define P17V_MIXER_Spdif_P17V_VOL_L 0x6B /* P17V to Mixer_Spdif input volume control */ 103*4882a593Smuzhiyun #define P17V_MIXER_Spdif_P17V_VOL_H 0x6C /* P17V to Mixer_Spdif input volume control */ 104*4882a593Smuzhiyun #define P17V_MIXER_Spdif_SRP_REC_VOL_L 0x6D /* SRP Record to Mixer_Spdif input volume control */ 105*4882a593Smuzhiyun #define P17V_MIXER_Spdif_SRP_REC_VOL_H 0x6E /* SRP Record to Mixer_Spdif input volume control */ 106*4882a593Smuzhiyun /* 6f - 70: Reserved */ 107*4882a593Smuzhiyun #define P17V_MIXER_I2S_10K1_VOL_L 0x71 /* 10K to Mixer_I2S input volume control */ 108*4882a593Smuzhiyun #define P17V_MIXER_I2S_10K1_VOL_H 0x72 /* 10K to Mixer_I2S input volume control */ 109*4882a593Smuzhiyun #define P17V_MIXER_I2S_P17V_VOL_L 0x73 /* P17V to Mixer_I2S input volume control */ 110*4882a593Smuzhiyun #define P17V_MIXER_I2S_P17V_VOL_H 0x74 /* P17V to Mixer_I2S input volume control */ 111*4882a593Smuzhiyun #define P17V_MIXER_I2S_SRP_REC_VOL_L 0x75 /* SRP Record to Mixer_I2S input volume control */ 112*4882a593Smuzhiyun #define P17V_MIXER_I2S_SRP_REC_VOL_H 0x76 /* SRP Record to Mixer_I2S input volume control */ 113*4882a593Smuzhiyun /* 77 - 78: Reserved */ 114*4882a593Smuzhiyun #define P17V_MIXER_AC97_ENABLE 0x79 /* Mixer AC97 input audio enable */ 115*4882a593Smuzhiyun #define P17V_MIXER_SPDIF_ENABLE 0x7A /* Mixer SPDIF input audio enable */ 116*4882a593Smuzhiyun #define P17V_MIXER_I2S_ENABLE 0x7B /* Mixer I2S input audio enable */ 117*4882a593Smuzhiyun #define P17V_AUDIO_OUT_ENABLE 0x7C /* Audio out enable */ 118*4882a593Smuzhiyun #define P17V_MIXER_ATT 0x7D /* SRP Mixer Attenuation Select */ 119*4882a593Smuzhiyun #define P17V_SRP_RECORD_SRR 0x7E /* SRP Record channel source Select */ 120*4882a593Smuzhiyun #define P17V_SOFT_RESET_SRP_MIXER 0x7F /* SRP and mixer soft reset */ 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define P17V_AC97_OUT_MASTER_VOL_L 0x80 /* AC97 Output master volume control */ 123*4882a593Smuzhiyun #define P17V_AC97_OUT_MASTER_VOL_H 0x81 /* AC97 Output master volume control */ 124*4882a593Smuzhiyun #define P17V_SPDIF_OUT_MASTER_VOL_L 0x82 /* SPDIF Output master volume control */ 125*4882a593Smuzhiyun #define P17V_SPDIF_OUT_MASTER_VOL_H 0x83 /* SPDIF Output master volume control */ 126*4882a593Smuzhiyun #define P17V_I2S_OUT_MASTER_VOL_L 0x84 /* I2S Output master volume control */ 127*4882a593Smuzhiyun #define P17V_I2S_OUT_MASTER_VOL_H 0x85 /* I2S Output master volume control */ 128*4882a593Smuzhiyun /* 86 - 87: Not used */ 129*4882a593Smuzhiyun #define P17V_I2S_CHANNEL_SWAP_PHASE_INVERSE 0x88 /* I2S out mono channel swap 130*4882a593Smuzhiyun * and phase inverse */ 131*4882a593Smuzhiyun #define P17V_SPDIF_CHANNEL_SWAP_PHASE_INVERSE 0x89 /* SPDIF out mono channel swap 132*4882a593Smuzhiyun * and phase inverse */ 133*4882a593Smuzhiyun /* 8A: Not used */ 134*4882a593Smuzhiyun #define P17V_SRP_P17V_ESR 0x8B /* SRP_P17V estimated sample rate and rate lock */ 135*4882a593Smuzhiyun #define P17V_SRP_REC_ESR 0x8C /* SRP_REC estimated sample rate and rate lock */ 136*4882a593Smuzhiyun #define P17V_SRP_BYPASS 0x8D /* srps channel bypass and srps bypass */ 137*4882a593Smuzhiyun /* 8E - 92: Not used */ 138*4882a593Smuzhiyun #define P17V_I2S_SRC_SEL 0x93 /* I2SIN mode sel */ 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun 145